2 * Ethernet driver for TI K2HK EVM.
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/ti-common/keystone_nav.h>
16 #include <asm/ti-common/keystone_net.h>
17 #include <asm/ti-common/keystone_serdes.h>
19 unsigned int emac_open;
20 static struct mii_dev *mdio_bus;
21 static unsigned int sys_has_mdio = 1;
23 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
24 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
26 #define emac_gigabit_enable(x) /* no gigabit to enable */
29 #define RX_BUFF_NUMS 24
30 #define RX_BUFF_LEN 1520
31 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
33 static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
35 struct rx_buff_desc net_rx_buffs = {
37 .num_buffs = RX_BUFF_NUMS,
38 .buff_len = RX_BUFF_LEN,
42 static void keystone2_net_serdes_setup(void);
44 static int gen_get_link_speed(int phy_addr);
46 int keystone2_eth_read_mac_addr(struct eth_device *dev)
48 struct eth_priv_t *eth_priv;
52 eth_priv = (struct eth_priv_t *)dev->priv;
54 /* Read the e-fuse mac address */
55 if (eth_priv->slave_port == 1) {
56 maca = __raw_readl(MAC_ID_BASE_ADDR);
57 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
60 dev->enetaddr[0] = (macb >> 8) & 0xff;
61 dev->enetaddr[1] = (macb >> 0) & 0xff;
62 dev->enetaddr[2] = (maca >> 24) & 0xff;
63 dev->enetaddr[3] = (maca >> 16) & 0xff;
64 dev->enetaddr[4] = (maca >> 8) & 0xff;
65 dev->enetaddr[5] = (maca >> 0) & 0xff;
72 static int keystone2_mdio_reset(struct mii_dev *bus)
75 struct mdio_regs *adap_mdio = bus->priv;
77 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
79 writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE |
80 MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
83 while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
90 * keystone2_mdio_read - read a PHY register via MDIO interface.
91 * Blocks until operation is complete.
93 static int keystone2_mdio_read(struct mii_dev *bus,
94 int addr, int devad, int reg)
97 struct mdio_regs *adap_mdio = bus->priv;
99 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
102 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
103 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16),
104 &adap_mdio->useraccess0);
106 /* Wait for command to complete */
107 while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
110 if (tmp & MDIO_USERACCESS0_ACK)
117 * keystone2_mdio_write - write to a PHY register via MDIO interface.
118 * Blocks until operation is complete.
120 static int keystone2_mdio_write(struct mii_dev *bus,
121 int addr, int devad, int reg, u16 val)
123 struct mdio_regs *adap_mdio = bus->priv;
125 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
128 writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
129 ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) |
130 (val & 0xffff), &adap_mdio->useraccess0);
132 /* Wait for command to complete */
133 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
139 /* PHY functions for a generic PHY */
140 static int gen_get_link_speed(int phy_addr)
144 tmp = mdio_bus->read(mdio_bus, phy_addr,
145 MDIO_DEVAD_NONE, MII_STATUS_REG);
152 static void __attribute__((unused))
153 keystone2_eth_gigabit_enable(struct eth_device *dev)
156 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
159 data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr,
161 /* speed selection MSB */
162 if (!(data & (1 << 6)))
167 * Check if link detected is giga-bit
168 * If Gigabit mode detected, enable gigbit in MAC
170 writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
172 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
173 DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
176 int keystone_sgmii_link_status(int port)
180 status = __raw_readl(SGMII_STATUS_REG(port));
182 return status & SGMII_REG_STATUS_LINK;
186 int keystone_get_link_status(struct eth_device *dev)
188 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
191 #if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1
194 for (j = 0; (j < CONFIG_GET_LINK_STATUS_ATTEMPTS) && (link_state == 0);
198 keystone_sgmii_link_status(eth_priv->slave_port - 1);
203 if (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY)
204 if (gen_get_link_speed(eth_priv->phy_addr))
207 #if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1
213 int keystone_sgmii_config(int port, int interface)
215 unsigned int i, status, mask;
216 unsigned int mr_adv_ability, control;
219 case SGMII_LINK_MAC_MAC_AUTONEG:
220 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
221 SGMII_REG_MR_ADV_LINK |
222 SGMII_REG_MR_ADV_FULL_DUPLEX |
223 SGMII_REG_MR_ADV_GIG_MODE);
224 control = (SGMII_REG_CONTROL_MASTER |
225 SGMII_REG_CONTROL_AUTONEG);
228 case SGMII_LINK_MAC_PHY:
229 case SGMII_LINK_MAC_PHY_FORCED:
230 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
231 control = SGMII_REG_CONTROL_AUTONEG;
234 case SGMII_LINK_MAC_MAC_FORCED:
235 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
236 SGMII_REG_MR_ADV_LINK |
237 SGMII_REG_MR_ADV_FULL_DUPLEX |
238 SGMII_REG_MR_ADV_GIG_MODE);
239 control = SGMII_REG_CONTROL_MASTER;
242 case SGMII_LINK_MAC_FIBER:
243 mr_adv_ability = 0x20;
244 control = SGMII_REG_CONTROL_AUTONEG;
248 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
249 control = SGMII_REG_CONTROL_AUTONEG;
252 __raw_writel(0, SGMII_CTL_REG(port));
255 * Wait for the SerDes pll to lock,
256 * but don't trap if lock is never read
258 for (i = 0; i < 1000; i++) {
260 status = __raw_readl(SGMII_STATUS_REG(port));
261 if ((status & SGMII_REG_STATUS_LOCK) != 0)
265 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
266 __raw_writel(control, SGMII_CTL_REG(port));
269 mask = SGMII_REG_STATUS_LINK;
271 if (control & SGMII_REG_CONTROL_AUTONEG)
272 mask |= SGMII_REG_STATUS_AUTONEG;
274 for (i = 0; i < 1000; i++) {
275 status = __raw_readl(SGMII_STATUS_REG(port));
276 if ((status & mask) == mask)
283 int mac_sl_reset(u32 port)
287 if (port >= DEVICE_N_GMACSL_PORTS)
288 return GMACSL_RET_INVALID_PORT;
290 /* Set the soft reset bit */
291 writel(CPGMAC_REG_RESET_VAL_RESET,
292 DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
294 /* Wait for the bit to clear */
295 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
296 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
297 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
298 CPGMAC_REG_RESET_VAL_RESET)
299 return GMACSL_RET_OK;
302 /* Timeout on the reset */
303 return GMACSL_RET_WARN_RESET_INCOMPLETE;
306 int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
309 int ret = GMACSL_RET_OK;
311 if (port >= DEVICE_N_GMACSL_PORTS)
312 return GMACSL_RET_INVALID_PORT;
314 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
315 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
316 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
319 /* Must wait if the device is undergoing reset */
320 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
321 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
322 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
323 CPGMAC_REG_RESET_VAL_RESET)
327 if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
328 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
330 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
331 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
336 int ethss_config(u32 ctl, u32 max_pkt_size)
340 /* Max length register */
341 writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
343 /* Control register */
344 writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
346 /* All statistics enabled by default */
347 writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
348 DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
350 /* Reset and enable the ALE */
351 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
352 CPSW_REG_VAL_ALE_CTL_BYPASS,
353 DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
355 /* All ports put into forward mode */
356 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
357 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
358 DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
363 int ethss_start(void)
366 struct mac_sl_cfg cfg;
368 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
369 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
371 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
373 mac_sl_config(i, &cfg);
383 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
389 int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
391 if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
392 num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
394 return ksnav_send(&netcp_pktdma, buffer,
395 num_bytes, (slave_port_num) << 16);
398 /* Eth device open */
399 static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
402 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
404 debug("+ emac_open\n");
406 net_rx_buffs.rx_flow = eth_priv->rx_flow;
409 (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
411 keystone2_net_serdes_setup();
413 keystone_sgmii_config(eth_priv->slave_port - 1,
414 eth_priv->sgmii_link_type);
418 /* On chip switch configuration */
419 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
421 /* TODO: add error handling code */
423 printf("ERROR: qm_init()\n");
426 if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
428 printf("ERROR: netcp_init()\n");
433 * Streaming switch configuration. If not present this
434 * statement is defined to void in target.h.
435 * If present this is usually defined to a series of register writes
437 hw_config_streaming_switch();
440 keystone2_mdio_reset(mdio_bus);
442 link = keystone_get_link_status(dev);
444 ksnav_close(&netcp_pktdma);
450 emac_gigabit_enable(dev);
454 debug("- emac_open\n");
461 /* Eth device close */
462 void keystone2_eth_close(struct eth_device *dev)
464 debug("+ emac_close\n");
471 ksnav_close(&netcp_pktdma);
476 debug("- emac_close\n");
480 * This function sends a single packet on the network and returns
481 * positive number (number of bytes transmitted) or negative for error
483 static int keystone2_eth_send_packet(struct eth_device *dev,
484 void *packet, int length)
487 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
489 if (keystone_get_link_status(dev) == 0)
492 if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
499 * This function handles receipt of a packet from the network
501 static int keystone2_eth_rcv_packet(struct eth_device *dev)
507 hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
511 NetReceive((uchar *)pkt, pkt_size);
513 ksnav_release_rxhd(&netcp_pktdma, hd);
519 * This function initializes the EMAC hardware.
521 int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
524 struct eth_device *dev;
526 dev = malloc(sizeof(struct eth_device));
530 memset(dev, 0, sizeof(struct eth_device));
532 strcpy(dev->name, eth_priv->int_name);
533 dev->priv = eth_priv;
535 keystone2_eth_read_mac_addr(dev);
538 dev->init = keystone2_eth_open;
539 dev->halt = keystone2_eth_close;
540 dev->send = keystone2_eth_send_packet;
541 dev->recv = keystone2_eth_rcv_packet;
545 /* Register MDIO bus if it's not registered yet */
547 mdio_bus = mdio_alloc();
548 mdio_bus->read = keystone2_mdio_read;
549 mdio_bus->write = keystone2_mdio_write;
550 mdio_bus->reset = keystone2_mdio_reset;
551 mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR;
552 sprintf(mdio_bus->name, "ethernet-mdio");
554 res = mdio_register(mdio_bus);
562 struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
563 .clk = SERDES_CLOCK_156P25M,
564 .rate = SERDES_RATE_5G,
565 .rate_mode = SERDES_QUARTER_RATE,
566 .intf = SERDES_PHY_SGMII,
570 static void keystone2_net_serdes_setup(void)
572 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
573 &ks2_serdes_sgmii_156p25mhz,
574 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
576 /* wait till setup */