2 * Ethernet driver for TI K2HK EVM.
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/psc_defs.h>
16 #include <asm/ti-common/keystone_nav.h>
17 #include <asm/ti-common/keystone_net.h>
19 unsigned int emac_dbg;
21 unsigned int emac_open;
22 static unsigned int sys_has_mdio = 1;
24 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
25 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
27 #define emac_gigabit_enable(x) /* no gigabit to enable */
30 #define RX_BUFF_NUMS 24
31 #define RX_BUFF_LEN 1520
32 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
34 static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
36 struct rx_buff_desc net_rx_buffs = {
38 .num_buffs = RX_BUFF_NUMS,
39 .buff_len = RX_BUFF_LEN,
43 static void keystone2_eth_mdio_enable(void);
45 static int gen_get_link_speed(int phy_addr);
48 static volatile struct mdio_regs *adap_mdio =
49 (struct mdio_regs *)EMAC_MDIO_BASE_ADDR;
51 int keystone2_eth_read_mac_addr(struct eth_device *dev)
53 struct eth_priv_t *eth_priv;
57 eth_priv = (struct eth_priv_t *)dev->priv;
59 /* Read the e-fuse mac address */
60 if (eth_priv->slave_port == 1) {
61 maca = __raw_readl(MAC_ID_BASE_ADDR);
62 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
65 dev->enetaddr[0] = (macb >> 8) & 0xff;
66 dev->enetaddr[1] = (macb >> 0) & 0xff;
67 dev->enetaddr[2] = (maca >> 24) & 0xff;
68 dev->enetaddr[3] = (maca >> 16) & 0xff;
69 dev->enetaddr[4] = (maca >> 8) & 0xff;
70 dev->enetaddr[5] = (maca >> 0) & 0xff;
75 static void keystone2_eth_mdio_enable(void)
79 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
81 writel((clkdiv & 0xffff) |
84 MDIO_CONTROL_FAULT_ENABLE,
87 while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
91 /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
92 int keystone2_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
96 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
99 writel(MDIO_USERACCESS0_GO |
100 MDIO_USERACCESS0_WRITE_READ |
101 ((reg_num & 0x1f) << 21) |
102 ((phy_addr & 0x1f) << 16),
103 &adap_mdio->useraccess0);
105 /* Wait for command to complete */
106 while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
109 if (tmp & MDIO_USERACCESS0_ACK) {
110 *data = tmp & 0xffff;
119 * Write to a PHY register via MDIO inteface.
120 * Blocks until operation is complete.
122 int keystone2_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
124 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
127 writel(MDIO_USERACCESS0_GO |
128 MDIO_USERACCESS0_WRITE_WRITE |
129 ((reg_num & 0x1f) << 21) |
130 ((phy_addr & 0x1f) << 16) |
132 &adap_mdio->useraccess0);
134 /* Wait for command to complete */
135 while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
141 /* PHY functions for a generic PHY */
142 static int gen_get_link_speed(int phy_addr)
146 if ((!keystone2_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp)) &&
154 static void __attribute__((unused))
155 keystone2_eth_gigabit_enable(struct eth_device *dev)
158 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
161 if (keystone2_eth_phy_read(eth_priv->phy_addr, 0, &data) ||
162 !(data & (1 << 6))) /* speed selection MSB */
167 * Check if link detected is giga-bit
168 * If Gigabit mode detected, enable gigbit in MAC
170 writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
172 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
173 DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
176 int keystone_sgmii_link_status(int port)
180 status = __raw_readl(SGMII_STATUS_REG(port));
182 return status & SGMII_REG_STATUS_LINK;
186 int keystone_get_link_status(struct eth_device *dev)
188 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
191 #if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1
194 for (j = 0; (j < CONFIG_GET_LINK_STATUS_ATTEMPTS) && (link_state == 0);
198 keystone_sgmii_link_status(eth_priv->slave_port - 1);
203 if (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY)
204 if (gen_get_link_speed(eth_priv->phy_addr))
207 #if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1
213 int keystone_sgmii_config(int port, int interface)
215 unsigned int i, status, mask;
216 unsigned int mr_adv_ability, control;
219 case SGMII_LINK_MAC_MAC_AUTONEG:
220 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
221 SGMII_REG_MR_ADV_LINK |
222 SGMII_REG_MR_ADV_FULL_DUPLEX |
223 SGMII_REG_MR_ADV_GIG_MODE);
224 control = (SGMII_REG_CONTROL_MASTER |
225 SGMII_REG_CONTROL_AUTONEG);
228 case SGMII_LINK_MAC_PHY:
229 case SGMII_LINK_MAC_PHY_FORCED:
230 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
231 control = SGMII_REG_CONTROL_AUTONEG;
234 case SGMII_LINK_MAC_MAC_FORCED:
235 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
236 SGMII_REG_MR_ADV_LINK |
237 SGMII_REG_MR_ADV_FULL_DUPLEX |
238 SGMII_REG_MR_ADV_GIG_MODE);
239 control = SGMII_REG_CONTROL_MASTER;
242 case SGMII_LINK_MAC_FIBER:
243 mr_adv_ability = 0x20;
244 control = SGMII_REG_CONTROL_AUTONEG;
248 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
249 control = SGMII_REG_CONTROL_AUTONEG;
252 __raw_writel(0, SGMII_CTL_REG(port));
255 * Wait for the SerDes pll to lock,
256 * but don't trap if lock is never read
258 for (i = 0; i < 1000; i++) {
260 status = __raw_readl(SGMII_STATUS_REG(port));
261 if ((status & SGMII_REG_STATUS_LOCK) != 0)
265 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
266 __raw_writel(control, SGMII_CTL_REG(port));
269 mask = SGMII_REG_STATUS_LINK;
271 if (control & SGMII_REG_CONTROL_AUTONEG)
272 mask |= SGMII_REG_STATUS_AUTONEG;
274 for (i = 0; i < 1000; i++) {
275 status = __raw_readl(SGMII_STATUS_REG(port));
276 if ((status & mask) == mask)
283 int mac_sl_reset(u32 port)
287 if (port >= DEVICE_N_GMACSL_PORTS)
288 return GMACSL_RET_INVALID_PORT;
290 /* Set the soft reset bit */
291 writel(CPGMAC_REG_RESET_VAL_RESET,
292 DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
294 /* Wait for the bit to clear */
295 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
296 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
297 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
298 CPGMAC_REG_RESET_VAL_RESET)
299 return GMACSL_RET_OK;
302 /* Timeout on the reset */
303 return GMACSL_RET_WARN_RESET_INCOMPLETE;
306 int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
309 int ret = GMACSL_RET_OK;
311 if (port >= DEVICE_N_GMACSL_PORTS)
312 return GMACSL_RET_INVALID_PORT;
314 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
315 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
316 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
319 /* Must wait if the device is undergoing reset */
320 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
321 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
322 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
323 CPGMAC_REG_RESET_VAL_RESET)
327 if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
328 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
330 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
331 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
336 int ethss_config(u32 ctl, u32 max_pkt_size)
340 /* Max length register */
341 writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
343 /* Control register */
344 writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
346 /* All statistics enabled by default */
347 writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
348 DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
350 /* Reset and enable the ALE */
351 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
352 CPSW_REG_VAL_ALE_CTL_BYPASS,
353 DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
355 /* All ports put into forward mode */
356 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
357 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
358 DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
363 int ethss_start(void)
366 struct mac_sl_cfg cfg;
368 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
369 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
371 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
373 mac_sl_config(i, &cfg);
383 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
389 int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
391 if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
392 num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
394 return ksnav_send(&netcp_pktdma, buffer,
395 num_bytes, (slave_port_num) << 16);
398 /* Eth device open */
399 static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
403 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
405 debug("+ emac_open\n");
407 net_rx_buffs.rx_flow = eth_priv->rx_flow;
410 (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
412 psc_enable_module(KS2_LPSC_PA);
413 psc_enable_module(KS2_LPSC_CPGMAC);
415 sgmii_serdes_setup_156p25mhz();
418 keystone2_eth_mdio_enable();
420 keystone_sgmii_config(eth_priv->slave_port - 1,
421 eth_priv->sgmii_link_type);
425 /* On chip switch configuration */
426 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
428 /* TODO: add error handling code */
430 printf("ERROR: qm_init()\n");
433 if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
435 printf("ERROR: netcp_init()\n");
440 * Streaming switch configuration. If not present this
441 * statement is defined to void in target.h.
442 * If present this is usually defined to a series of register writes
444 hw_config_streaming_switch();
447 /* Init MDIO & get link state */
448 clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
449 writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE |
450 MDIO_CONTROL_FAULT, &adap_mdio->control)
453 /* We need to wait for MDIO to start */
456 link = keystone_get_link_status(dev);
458 ksnav_close(&netcp_pktdma);
464 emac_gigabit_enable(dev);
468 debug("- emac_open\n");
475 /* Eth device close */
476 void keystone2_eth_close(struct eth_device *dev)
478 debug("+ emac_close\n");
485 ksnav_close(&netcp_pktdma);
490 debug("- emac_close\n");
493 static int tx_send_loop;
496 * This function sends a single packet on the network and returns
497 * positive number (number of bytes transmitted) or negative for error
499 static int keystone2_eth_send_packet(struct eth_device *dev,
500 void *packet, int length)
503 struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
507 if (keystone_get_link_status(dev) == 0)
510 emac_gigabit_enable(dev);
512 if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
515 if (keystone_get_link_status(dev) == 0)
518 emac_gigabit_enable(dev);
524 * This function handles receipt of a packet from the network
526 static int keystone2_eth_rcv_packet(struct eth_device *dev)
532 hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
536 NetReceive((uchar *)pkt, pkt_size);
538 ksnav_release_rxhd(&netcp_pktdma, hd);
544 * This function initializes the EMAC hardware.
546 int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
548 struct eth_device *dev;
550 dev = malloc(sizeof(struct eth_device));
554 memset(dev, 0, sizeof(struct eth_device));
556 strcpy(dev->name, eth_priv->int_name);
557 dev->priv = eth_priv;
559 keystone2_eth_read_mac_addr(dev);
562 dev->init = keystone2_eth_open;
563 dev->halt = keystone2_eth_close;
564 dev->send = keystone2_eth_send_packet;
565 dev->recv = keystone2_eth_rcv_packet;
572 void sgmii_serdes_setup_156p25mhz(void)
577 * configure Serializer/Deserializer (SerDes) hardware. SerDes IP
578 * hardware vendor published only register addresses and their values
579 * to be used for configuring SerDes. So had to use hardcoded values
582 clrsetbits_le32(0x0232a000, 0xffff0000, 0x00800000);
583 clrsetbits_le32(0x0232a014, 0x0000ffff, 0x00008282);
584 clrsetbits_le32(0x0232a060, 0x00ffffff, 0x00142438);
585 clrsetbits_le32(0x0232a064, 0x00ffff00, 0x00c3c700);
586 clrsetbits_le32(0x0232a078, 0x0000ff00, 0x0000c000);
588 clrsetbits_le32(0x0232a204, 0xff0000ff, 0x38000080);
589 clrsetbits_le32(0x0232a208, 0x000000ff, 0x00000000);
590 clrsetbits_le32(0x0232a20c, 0xff000000, 0x02000000);
591 clrsetbits_le32(0x0232a210, 0xff000000, 0x1b000000);
592 clrsetbits_le32(0x0232a214, 0x0000ffff, 0x00006fb8);
593 clrsetbits_le32(0x0232a218, 0xffff00ff, 0x758000e4);
594 clrsetbits_le32(0x0232a2ac, 0x0000ff00, 0x00004400);
595 clrsetbits_le32(0x0232a22c, 0x00ffff00, 0x00200800);
596 clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082);
597 clrsetbits_le32(0x0232a284, 0xffffffff, 0x1d0f0385);
599 clrsetbits_le32(0x0232a404, 0xff0000ff, 0x38000080);
600 clrsetbits_le32(0x0232a408, 0x000000ff, 0x00000000);
601 clrsetbits_le32(0x0232a40c, 0xff000000, 0x02000000);
602 clrsetbits_le32(0x0232a410, 0xff000000, 0x1b000000);
603 clrsetbits_le32(0x0232a414, 0x0000ffff, 0x00006fb8);
604 clrsetbits_le32(0x0232a418, 0xffff00ff, 0x758000e4);
605 clrsetbits_le32(0x0232a4ac, 0x0000ff00, 0x00004400);
606 clrsetbits_le32(0x0232a42c, 0x00ffff00, 0x00200800);
607 clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082);
608 clrsetbits_le32(0x0232a484, 0xffffffff, 0x1d0f0385);
610 clrsetbits_le32(0x0232a604, 0xff0000ff, 0x38000080);
611 clrsetbits_le32(0x0232a608, 0x000000ff, 0x00000000);
612 clrsetbits_le32(0x0232a60c, 0xff000000, 0x02000000);
613 clrsetbits_le32(0x0232a610, 0xff000000, 0x1b000000);
614 clrsetbits_le32(0x0232a614, 0x0000ffff, 0x00006fb8);
615 clrsetbits_le32(0x0232a618, 0xffff00ff, 0x758000e4);
616 clrsetbits_le32(0x0232a6ac, 0x0000ff00, 0x00004400);
617 clrsetbits_le32(0x0232a62c, 0x00ffff00, 0x00200800);
618 clrsetbits_le32(0x0232a680, 0x00ff00ff, 0x00820082);
619 clrsetbits_le32(0x0232a684, 0xffffffff, 0x1d0f0385);
621 clrsetbits_le32(0x0232a804, 0xff0000ff, 0x38000080);
622 clrsetbits_le32(0x0232a808, 0x000000ff, 0x00000000);
623 clrsetbits_le32(0x0232a80c, 0xff000000, 0x02000000);
624 clrsetbits_le32(0x0232a810, 0xff000000, 0x1b000000);
625 clrsetbits_le32(0x0232a814, 0x0000ffff, 0x00006fb8);
626 clrsetbits_le32(0x0232a818, 0xffff00ff, 0x758000e4);
627 clrsetbits_le32(0x0232a8ac, 0x0000ff00, 0x00004400);
628 clrsetbits_le32(0x0232a82c, 0x00ffff00, 0x00200800);
629 clrsetbits_le32(0x0232a880, 0x00ff00ff, 0x00820082);
630 clrsetbits_le32(0x0232a884, 0xffffffff, 0x1d0f0385);
632 clrsetbits_le32(0x0232aa00, 0x0000ff00, 0x00000800);
633 clrsetbits_le32(0x0232aa08, 0xffff0000, 0x38a20000);
634 clrsetbits_le32(0x0232aa30, 0x00ffff00, 0x008a8a00);
635 clrsetbits_le32(0x0232aa84, 0x0000ff00, 0x00000600);
636 clrsetbits_le32(0x0232aa94, 0xff000000, 0x10000000);
637 clrsetbits_le32(0x0232aaa0, 0xff000000, 0x81000000);
638 clrsetbits_le32(0x0232aabc, 0xff000000, 0xff000000);
639 clrsetbits_le32(0x0232aac0, 0x000000ff, 0x0000008b);
640 clrsetbits_le32(0x0232ab08, 0xffff0000, 0x583f0000);
641 clrsetbits_le32(0x0232ab0c, 0x000000ff, 0x0000004e);
642 clrsetbits_le32(0x0232a000, 0x000000ff, 0x00000003);
643 clrsetbits_le32(0x0232aa00, 0x000000ff, 0x0000005f);
645 clrsetbits_le32(0x0232aa48, 0x00ffff00, 0x00fd8c00);
646 clrsetbits_le32(0x0232aa54, 0x00ffffff, 0x002fec72);
647 clrsetbits_le32(0x0232aa58, 0xffffff00, 0x00f92100);
648 clrsetbits_le32(0x0232aa5c, 0xffffffff, 0x00040060);
649 clrsetbits_le32(0x0232aa60, 0xffffffff, 0x00008000);
650 clrsetbits_le32(0x0232aa64, 0xffffffff, 0x0c581220);
651 clrsetbits_le32(0x0232aa68, 0xffffffff, 0xe13b0602);
652 clrsetbits_le32(0x0232aa6c, 0xffffffff, 0xb8074cc1);
653 clrsetbits_le32(0x0232aa70, 0xffffffff, 0x3f02e989);
654 clrsetbits_le32(0x0232aa74, 0x000000ff, 0x00000001);
655 clrsetbits_le32(0x0232ab20, 0x00ff0000, 0x00370000);
656 clrsetbits_le32(0x0232ab1c, 0xff000000, 0x37000000);
657 clrsetbits_le32(0x0232ab20, 0x000000ff, 0x0000005d);
659 /*Bring SerDes out of Reset if SerDes is Shutdown & is in Reset Mode*/
660 clrbits_le32(0x0232a010, 1 << 28);
662 /* Enable TX and RX via the LANExCTL_STS 0x0000 + x*4 */
663 clrbits_le32(0x0232a228, 1 << 29);
664 writel(0xF800F8C0, 0x0232bfe0);
665 clrbits_le32(0x0232a428, 1 << 29);
666 writel(0xF800F8C0, 0x0232bfe4);
667 clrbits_le32(0x0232a628, 1 << 29);
668 writel(0xF800F8C0, 0x0232bfe8);
669 clrbits_le32(0x0232a828, 1 << 29);
670 writel(0xF800F8C0, 0x0232bfec);
672 /*Enable pll via the pll_ctrl 0x0014*/
673 writel(0xe0000000, 0x0232bff4)
676 /*Waiting for SGMII Serdes PLL lock.*/
677 for (cnt = 10000; cnt > 0 && ((readl(0x02090114) & 0x10) == 0); cnt--)
680 for (cnt = 10000; cnt > 0 && ((readl(0x02090214) & 0x10) == 0); cnt--)
683 for (cnt = 10000; cnt > 0 && ((readl(0x02090414) & 0x10) == 0); cnt--)
686 for (cnt = 10000; cnt > 0 && ((readl(0x02090514) & 0x10) == 0); cnt--)
692 void sgmii_serdes_shutdown(void)
695 * shutdown SerDes hardware. SerDes hardware vendor published only
696 * register addresses and their values. So had to use hardcoded
699 clrbits_le32(0x0232bfe0, 3 << 29 | 3 << 13);
700 setbits_le32(0x02320228, 1 << 29);
701 clrbits_le32(0x0232bfe4, 3 << 29 | 3 << 13);
702 setbits_le32(0x02320428, 1 << 29);
703 clrbits_le32(0x0232bfe8, 3 << 29 | 3 << 13);
704 setbits_le32(0x02320628, 1 << 29);
705 clrbits_le32(0x0232bfec, 3 << 29 | 3 << 13);
706 setbits_le32(0x02320828, 1 << 29);
708 clrbits_le32(0x02320034, 3 << 29);
709 setbits_le32(0x02320010, 1 << 28);