4 * SPDX-License-Identifier: GPL-2.0+
8 #include <fsl-mc/ldpaa_wriop.h>
10 #include <asm/arch/fsl_serdes.h>
12 u32 dpmac_to_devdisr[] = {
13 [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
14 [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
15 [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
16 [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
17 [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
18 [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
19 [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
20 [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
21 [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
22 [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
25 static int is_device_disabled(int dpmac_id)
27 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
28 u32 devdisr2 = in_le32(&gur->devdisr2);
30 return dpmac_to_devdisr[dpmac_id] & devdisr2;
33 void wriop_dpmac_disable(int dpmac_id)
35 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
37 setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
40 void wriop_dpmac_enable(int dpmac_id)
42 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
44 clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
47 phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
51 if (is_device_disabled(dpmac_id + 1))
52 return PHY_INTERFACE_MODE_NONE;
59 return PHY_INTERFACE_MODE_SGMII;
62 if (lane_prtcl >= XFI1 && lane_prtcl <= XFI2)
63 return PHY_INTERFACE_MODE_XGMII;
65 if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_B)
66 return PHY_INTERFACE_MODE_QSGMII;
68 return PHY_INTERFACE_MODE_NONE;
71 void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
75 wriop_init_dpmac(sd, 3, (int)lane_prtcl);
76 wriop_init_dpmac(sd, 4, (int)lane_prtcl);
77 wriop_init_dpmac(sd, 5, (int)lane_prtcl);
78 wriop_init_dpmac(sd, 6, (int)lane_prtcl);
81 wriop_init_dpmac(sd, 7, (int)lane_prtcl);
82 wriop_init_dpmac(sd, 8, (int)lane_prtcl);
83 wriop_init_dpmac(sd, 9, (int)lane_prtcl);
84 wriop_init_dpmac(sd, 10, (int)lane_prtcl);