2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/immap.h>
42 /* Ethernet Transmit and Receive Buffers */
43 #define DBUF_LENGTH 1520
45 #define PKT_MAXBUF_SIZE 1518
46 #define PKT_MINBUF_SIZE 64
47 #define PKT_MAXBLR_SIZE 1520
48 #define LAST_PKTBUFSRX PKTBUFSRX - 1
49 #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
50 #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
52 DECLARE_GLOBAL_DATA_PTR;
54 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
56 struct fec_info_s fec_info[] = {
57 #ifdef CFG_FEC0_IOBASE
60 CFG_FEC0_IOBASE, /* io base */
61 CFG_FEC0_PINMUX, /* gpio pin muxing */
62 CFG_FEC0_MIIBASE, /* mii base */
64 0, /* duplex and speed */
72 0, /* initialized flag */
75 #ifdef CFG_FEC1_IOBASE
78 CFG_FEC1_IOBASE, /* io base */
79 CFG_FEC1_PINMUX, /* gpio pin muxing */
80 CFG_FEC1_MIIBASE, /* mii base */
82 0, /* duplex and speed */
84 0, /* phy name init */
90 0, /* initialized flag */
95 int fec_send(struct eth_device *dev, volatile void *packet, int length);
96 int fec_recv(struct eth_device *dev);
97 int fec_init(struct eth_device *dev, bd_t * bd);
98 void fec_halt(struct eth_device *dev);
99 void fec_reset(struct eth_device *dev);
101 extern int fecpin_setclear(struct eth_device *dev, int setclear);
103 #ifdef CFG_DISCOVER_PHY
104 extern void __mii_init(void);
105 extern uint mii_send(uint mii_cmd);
106 extern int mii_discover_phy(struct eth_device *dev);
107 extern int mcffec_miiphy_read(char *devname, unsigned char addr,
108 unsigned char reg, unsigned short *value);
109 extern int mcffec_miiphy_write(char *devname, unsigned char addr,
110 unsigned char reg, unsigned short value);
113 void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
115 if ((dup_spd >> 16) == FULL) {
116 /* Set maximum frame length */
117 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
118 FEC_RCR_PROM | 0x100;
119 fecp->tcr = FEC_TCR_FDEN;
121 /* Half duplex mode */
122 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
123 FEC_RCR_MII_MODE | FEC_RCR_DRT;
124 fecp->tcr &= ~FEC_TCR_FDEN;
127 if ((dup_spd & 0xFFFF) == _100BASET) {
128 #ifdef CONFIG_MCF5445x
129 fecp->rcr &= ~0x200; /* disabled 10T base */
134 bd->bi_ethspeed = 100;
136 #ifdef CONFIG_MCF5445x
137 fecp->rcr |= 0x200; /* enabled 10T base */
142 bd->bi_ethspeed = 10;
146 int fec_send(struct eth_device *dev, volatile void *packet, int length)
148 struct fec_info_s *info = dev->priv;
149 volatile fec_t *fecp = (fec_t *) (info->iobase);
153 miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus);
159 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
160 (j < MCFFEC_TOUT_LOOP)) {
164 if (j >= MCFFEC_TOUT_LOOP) {
165 printf("TX not ready\n");
168 info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
169 info->txbd[info->txIdx].cbd_datlen = length;
170 info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;
172 /* Activate transmit Buffer Descriptor polling */
173 fecp->tdar = 0x01000000; /* Descriptor polling active */
175 /* FEC fix for MCF5275, FEC unable to initial transmit data packet.
176 * A nop will ensure the descriptor polling active completed.
182 #ifdef CFG_UNIFY_CACHE
186 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
187 (j < MCFFEC_TOUT_LOOP)) {
191 if (j >= MCFFEC_TOUT_LOOP) {
192 printf("TX timeout\n");
196 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
197 __FILE__, __LINE__, __FUNCTION__, j,
198 info->txbd[info->txIdx].cbd_sc,
199 (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
202 /* return only status bits */
203 rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
204 info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
209 int fec_recv(struct eth_device *dev)
211 struct fec_info_s *info = dev->priv;
212 volatile fec_t *fecp = (fec_t *) (info->iobase);
216 #ifdef CFG_UNIFY_CACHE
219 /* section 16.9.23.2 */
220 if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
222 break; /* nothing received - leave for() loop */
225 length = info->rxbd[info->rxIdx].cbd_datlen;
227 if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) {
228 printf("%s[%d] err: %x\n",
229 __FUNCTION__, __LINE__,
230 info->rxbd[info->rxIdx].cbd_sc);
232 printf("%s[%d] err: %x\n",
233 __FUNCTION__, __LINE__,
234 info->rxbd[info->rxIdx].cbd_sc);
239 /* Pass the packet up to the protocol layers. */
240 NetReceive(NetRxPackets[info->rxIdx], length);
242 fecp->eir |= FEC_EIR_RXF;
245 /* Give the buffer back to the FEC. */
246 info->rxbd[info->rxIdx].cbd_datlen = 0;
248 /* wrap around buffer index when necessary */
249 if (info->rxIdx == LAST_PKTBUFSRX) {
250 info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
253 info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
257 /* Try to fill Buffer Descriptors */
258 fecp->rdar = 0x01000000; /* Descriptor polling active */
265 void dbgFecRegs(struct eth_device *dev)
267 struct fec_info_s *info = dev->priv;
268 volatile fec_t *fecp = (fec_t *) (info->iobase);
271 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
272 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
273 printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar);
274 printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar);
275 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
276 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
277 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
278 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
279 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
280 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
281 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
282 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
283 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
284 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
285 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
286 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
287 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
288 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
289 printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr);
290 printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr);
291 printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr);
292 printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr);
293 printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr);
296 printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop,
298 printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets,
299 fecp->rmon_t_packets);
300 printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt,
301 fecp->rmon_t_bc_pkt);
302 printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt,
303 fecp->rmon_t_mc_pkt);
304 printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align,
305 fecp->rmon_t_crc_align);
306 printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize,
307 fecp->rmon_t_undersize);
308 printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize,
309 fecp->rmon_t_oversize);
310 printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag,
312 printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab,
314 printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col,
316 printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64,
318 printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127,
319 fecp->rmon_t_p65to127);
320 printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255,
321 fecp->rmon_t_p128to255);
322 printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511,
323 fecp->rmon_t_p256to511);
324 printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023,
325 fecp->rmon_t_p512to1023);
326 printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047,
327 fecp->rmon_t_p1024to2047);
328 printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048,
329 fecp->rmon_t_p_gte2048);
330 printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets,
331 fecp->rmon_t_octets);
334 printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop,
336 printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok,
337 fecp->ieee_t_frame_ok);
338 printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col,
340 printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol,
342 printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def,
344 printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol,
346 printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol,
348 printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr,
349 fecp->ieee_t_macerr);
350 printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr,
352 printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe,
354 printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc,
356 printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok,
357 fecp->ieee_t_octets_ok);
360 printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop,
362 printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets,
363 fecp->rmon_r_packets);
364 printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt,
365 fecp->rmon_r_bc_pkt);
366 printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt,
367 fecp->rmon_r_mc_pkt);
368 printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align,
369 fecp->rmon_r_crc_align);
370 printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize,
371 fecp->rmon_r_undersize);
372 printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize,
373 fecp->rmon_r_oversize);
374 printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag,
376 printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab,
378 printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64,
380 printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127,
381 fecp->rmon_r_p65to127);
382 printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255,
383 fecp->rmon_r_p128to255);
384 printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511,
385 fecp->rmon_r_p256to511);
386 printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023,
387 fecp->rmon_r_p512to1023);
388 printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047,
389 fecp->rmon_r_p1024to2047);
390 printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048,
391 fecp->rmon_r_p_gte2048);
392 printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets,
393 fecp->rmon_r_octets);
396 printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop,
398 printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok,
399 fecp->ieee_r_frame_ok);
400 printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc,
402 printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align,
404 printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr,
405 fecp->ieee_r_macerr);
406 printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc,
408 printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok,
409 fecp->ieee_r_octets_ok);
415 int fec_init(struct eth_device *dev, bd_t * bd)
417 struct fec_info_s *info = dev->priv;
418 volatile fec_t *fecp = (fec_t *) (info->iobase);
422 fecpin_setclear(dev, 1);
426 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
427 defined (CFG_DISCOVER_PHY)
431 setFecDuplexSpeed(fecp, bd, info->dup_spd);
433 #ifndef CFG_DISCOVER_PHY
434 setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
435 #endif /* ifndef CFG_DISCOVER_PHY */
436 #endif /* CONFIG_CMD_MII || CONFIG_MII */
438 /* We use strictly polling mode only */
441 /* Clear any pending interrupt */
442 fecp->eir = 0xffffffff;
444 /* Set station address */
445 if ((u32) fecp == CFG_FEC0_IOBASE) {
446 #ifdef CFG_FEC1_IOBASE
447 volatile fec_t *fecp1 = (fec_t *) (CFG_FEC1_IOBASE);
448 ea = &bd->bi_enet1addr[0];
450 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
451 fecp1->paur = (ea[4] << 24) | (ea[5] << 16);
453 ea = &bd->bi_enetaddr[0];
455 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
456 fecp->paur = (ea[4] << 24) | (ea[5] << 16);
458 #ifdef CFG_FEC0_IOBASE
459 volatile fec_t *fecp0 = (fec_t *) (CFG_FEC0_IOBASE);
460 ea = &bd->bi_enetaddr[0];
462 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
463 fecp0->paur = (ea[4] << 24) | (ea[5] << 16);
465 #ifdef CFG_FEC1_IOBASE
466 ea = &bd->bi_enet1addr[0];
468 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
469 fecp->paur = (ea[4] << 24) | (ea[5] << 16);
473 /* Clear unicast address hash table */
477 /* Clear multicast address hash table */
481 /* Set maximum receive buffer size. */
482 fecp->emrbr = PKT_MAXBLR_SIZE;
485 * Setup Buffers and Buffer Desriptors
491 * Setup Receiver Buffer Descriptors (13.14.24.18)
495 for (i = 0; i < PKTBUFSRX; i++) {
496 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
497 info->rxbd[i].cbd_datlen = 0; /* Reset */
498 info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
500 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
503 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
507 for (i = 0; i < TX_BUF_CNT; i++) {
508 info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
509 info->txbd[i].cbd_datlen = 0; /* Reset */
510 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
512 info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
514 /* Set receive and transmit descriptor base */
515 fecp->erdsr = (unsigned int)(&info->rxbd[0]);
516 fecp->etdsr = (unsigned int)(&info->txbd[0]);
518 /* Now enable the transmit and receive processing */
519 fecp->ecr |= FEC_ECR_ETHER_EN;
521 /* And last, try to fill Rx Buffer Descriptors */
522 fecp->rdar = 0x01000000; /* Descriptor polling active */
527 void fec_reset(struct eth_device *dev)
529 struct fec_info_s *info = dev->priv;
530 volatile fec_t *fecp = (fec_t *) (info->iobase);
533 fecp->ecr = FEC_ECR_RESET;
534 for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
537 if (i == FEC_RESET_DELAY) {
538 printf("FEC_RESET_DELAY timeout\n");
542 void fec_halt(struct eth_device *dev)
544 struct fec_info_s *info = dev->priv;
548 fecpin_setclear(dev, 0);
550 info->rxIdx = info->txIdx = 0;
551 memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
552 memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
553 memset(info->txbuf, 0, DBUF_LENGTH);
556 int mcffec_initialize(bd_t * bis)
558 struct eth_device *dev;
561 for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) {
564 (struct eth_device *)memalign(CFG_CACHELINE_SIZE,
569 memset(dev, 0, sizeof(*dev));
571 sprintf(dev->name, "FEC%d", fec_info[i].index);
573 dev->priv = &fec_info[i];
574 dev->init = fec_init;
575 dev->halt = fec_halt;
576 dev->send = fec_send;
577 dev->recv = fec_recv;
579 /* setup Receive and Transmit buffer descriptor */
581 (cbd_t *) memalign(CFG_CACHELINE_SIZE,
582 (PKTBUFSRX * sizeof(cbd_t)));
584 (cbd_t *) memalign(CFG_CACHELINE_SIZE,
585 (TX_BUF_CNT * sizeof(cbd_t)));
587 (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH);
589 printf("rxbd %x txbd %x\n",
590 (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
593 fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32);
597 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
598 miiphy_register(dev->name,
599 mcffec_miiphy_read, mcffec_miiphy_write);
604 bis->bi_ethspeed = 10;
609 #endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
610 #endif /* CONFIG_MCFFEC */