2 * (C) Copyright 2003-2010
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
11 #include <mpc5xxx_sdma.h>
16 #include "mpc5xxx_fec.h"
18 DECLARE_GLOBAL_DATA_PTR;
20 /* #define DEBUG 0x28 */
22 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
23 #error "CONFIG_MII has to be defined!"
27 static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
28 static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
32 uint8 data[1500]; /* actual data */
33 int length; /* actual length */
34 int used; /* buffer in use or not */
35 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
38 int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 *retVal);
39 int fec5xxx_miiphy_write(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
41 static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis);
43 /********************************************************************/
45 static void mpc5xxx_fec_phydump (char *devname)
48 uint8 phyAddr = CONFIG_PHY_ADDR;
50 #if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
51 /* regs to print: 0...7, 16...19, 21, 23, 24 */
52 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
53 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
55 /* regs to print: 0...8, 16...20 */
56 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
57 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
61 for (i = 0; i < 32; i++) {
63 miiphy_read(devname, phyAddr, i, &phyStatus);
64 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
70 /********************************************************************/
71 static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
77 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
79 data = (char *)malloc(FEC_MAX_PKT_SIZE);
81 printf ("RBD INIT FAILED\n");
84 fec->rbdBase[ix].dataPointer = (uint32)data;
86 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
87 fec->rbdBase[ix].dataLength = 0;
92 * have the last RBD to close the ring
94 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
100 /********************************************************************/
101 static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
105 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
106 fec->tbdBase[ix].status = 0;
110 * Have the last TBD to close the ring
112 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
115 * Initialize some indices
118 fec->usedTbdIndex = 0;
119 fec->cleanTbdNum = FEC_TBD_NUM;
122 /********************************************************************/
123 static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
126 * Reset buffer descriptor as empty
128 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
129 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
131 pRbd->status = FEC_RBD_EMPTY;
133 pRbd->dataLength = 0;
136 * Now, we have an empty RxBD, restart the SmartDMA receive task
138 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
143 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
146 /********************************************************************/
147 static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
149 volatile FEC_TBD *pUsedTbd;
152 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
153 fec->cleanTbdNum, fec->usedTbdIndex);
157 * process all the consumed TBDs
159 while (fec->cleanTbdNum < FEC_TBD_NUM) {
160 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
161 if (pUsedTbd->status & FEC_TBD_READY) {
163 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
169 * clean this buffer descriptor
171 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
172 pUsedTbd->status = FEC_TBD_WRAP;
174 pUsedTbd->status = 0;
177 * update some indeces for a correct handling of the TBD ring
180 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
184 /********************************************************************/
185 static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
187 uint8 currByte; /* byte for which to compute the CRC */
188 int byte; /* loop - counter */
189 int bit; /* loop - counter */
190 uint32 crc = 0xffffffff; /* initial value */
193 * The algorithm used is the following:
194 * we loop on each of the six bytes of the provided address,
195 * and we compute the CRC by left-shifting the previous
196 * value by one position, so that each bit in the current
197 * byte of the address may contribute the calculation. If
198 * the latter and the MSB in the CRC are different, then
199 * the CRC value so computed is also ex-ored with the
200 * "polynomium generator". The current byte of the address
201 * is also shifted right by one bit at each iteration.
202 * This is because the CRC generatore in hardware is implemented
203 * as a shift-register with as many ex-ores as the radixes
204 * in the polynomium. This suggests that we represent the
205 * polynomiumm itself as a 32-bit constant.
207 for (byte = 0; byte < 6; byte++) {
208 currByte = mac[byte];
209 for (bit = 0; bit < 8; bit++) {
210 if ((currByte & 0x01) ^ (crc & 0x01)) {
212 crc = crc ^ 0xedb88320;
223 * Set individual hash table register
226 fec->eth->iaddr1 = (1 << (crc - 32));
227 fec->eth->iaddr2 = 0;
229 fec->eth->iaddr1 = 0;
230 fec->eth->iaddr2 = (1 << crc);
234 * Set physical address
236 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
237 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
240 /********************************************************************/
241 static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
243 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
244 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
247 printf ("mpc5xxx_fec_init... Begin\n");
250 mpc5xxx_fec_init_phy(dev, bis);
253 * Call board-specific PHY fixups (if any)
255 #ifdef CONFIG_RESET_PHY_R
260 * Initialize RxBD/TxBD rings
262 mpc5xxx_fec_rbd_init(fec);
263 mpc5xxx_fec_tbd_init(fec);
266 * Clear FEC-Lite interrupt event register(IEVENT)
268 fec->eth->ievent = 0xffffffff;
271 * Set interrupt mask register
273 fec->eth->imask = 0x00000000;
276 * Set FEC-Lite receive control register(R_CNTRL):
278 if (fec->xcv_type == SEVENWIRE) {
280 * Frame length=1518; 7-wire mode
282 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
285 * Frame length=1518; MII mode;
287 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
290 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
293 * Set Opcode/Pause Duration Register
295 fec->eth->op_pause = 0x00010020; /*FIXME 0xffff0020; */
298 * Set Rx FIFO alarm and granularity value
300 fec->eth->rfifo_cntrl = 0x0c000000
301 | (fec->eth->rfifo_cntrl & ~0x0f000000);
302 fec->eth->rfifo_alarm = 0x0000030c;
304 if (fec->eth->rfifo_status & 0x00700000 ) {
305 printf("mpc5xxx_fec_init() RFIFO error\n");
310 * Set Tx FIFO granularity value
312 fec->eth->tfifo_cntrl = 0x0c000000
313 | (fec->eth->tfifo_cntrl & ~0x0f000000);
315 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
316 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
320 * Set transmit fifo watermark register(X_WMRK), default = 64
322 fec->eth->tfifo_alarm = 0x00000080;
323 fec->eth->x_wmrk = 0x2;
326 * Set individual address filter for unicast address
327 * and set physical address registers.
329 mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
332 * Set multicast address filter
334 fec->eth->gaddr1 = 0x00000000;
335 fec->eth->gaddr2 = 0x00000000;
338 * Turn ON cheater FSM: ????
340 fec->eth->xmit_fsm = 0x03000000;
343 * Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't
344 * work w/ the current receive task.
346 sdma->PtdCntrl |= 0x00000001;
349 * Set priority of different initiators
351 sdma->IPR0 = 7; /* always */
352 sdma->IPR3 = 6; /* Eth RX */
353 sdma->IPR4 = 5; /* Eth Tx */
356 * Clear SmartDMA task interrupt pending bits
358 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
361 * Initialize SmartDMA parameters stored in SRAM
363 *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
364 *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
365 *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
366 *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
369 * Enable FEC-Lite controller
371 fec->eth->ecntrl |= 0x00000006;
374 if (fec->xcv_type != SEVENWIRE)
375 mpc5xxx_fec_phydump (dev->name);
379 * Enable SmartDMA receive task
381 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
384 printf("mpc5xxx_fec_init... Done \n");
390 /********************************************************************/
391 static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
393 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
394 const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
395 static int initialized = 0;
402 printf ("mpc5xxx_fec_init_phy... Begin\n");
406 * Initialize GPIO pins
408 if (fec->xcv_type == SEVENWIRE) {
409 /* 10MBit with 7-wire operation */
411 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
413 /* 100MBit with MD operation */
414 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
418 * Clear FEC-Lite interrupt event register(IEVENT)
420 fec->eth->ievent = 0xffffffff;
423 * Set interrupt mask register
425 fec->eth->imask = 0x00000000;
428 * In original Promess-provided code PHY initialization is disabled with the
429 * following comment: "Phy initialization is DISABLED for now. There was a
430 * problem with running 100 Mbps on PRO board". Thus we temporarily disable
431 * PHY initialization for the Motion-PRO board, until a proper fix is found.
434 if (fec->xcv_type != SEVENWIRE) {
436 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
437 * and do not drop the Preamble.
438 * No MII for 7-wire mode
440 fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
443 if (fec->xcv_type != SEVENWIRE) {
445 * Initialize PHY(LXT971A):
447 * Generally, on power up, the LXT971A reads its configuration
448 * pins to check for forced operation, If not cofigured for
449 * forced operation, it uses auto-negotiation/parallel detection
450 * to automatically determine line operating conditions.
451 * If the PHY device on the other side of the link supports
452 * auto-negotiation, the LXT971A auto-negotiates with it
453 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
454 * support auto-negotiation, the LXT971A automatically detects
455 * the presence of either link pulses(10Mbps PHY) or Idle
456 * symbols(100Mbps) and sets its operating conditions accordingly.
458 * When auto-negotiation is controlled by software, the following
459 * steps are recommended.
462 * The physical address is dependent on hardware configuration.
469 * Reset PHY, then delay 300ns
471 miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
474 if (fec->xcv_type == MII10) {
476 * Force 10Base-T, FDX operation
479 printf("Forcing 10 Mbps ethernet link... ");
481 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
483 miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
485 miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
488 do { /* wait for link status to go down */
490 if ((timeout--) == 0) {
492 printf("hmmm, should not have waited...");
496 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
500 } while ((phyStatus & 0x0004)); /* !link up */
503 do { /* wait for link status to come back up */
505 if ((timeout--) == 0) {
506 printf("failed. Link is down.\n");
509 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
513 } while (!(phyStatus & 0x0004)); /* !link up */
518 } else { /* MII100 */
520 * Set the auto-negotiation advertisement register bits
522 miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
525 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
527 miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
530 * Wait for AN completion
536 if ((timeout--) == 0) {
538 printf("PHY auto neg 0 failed...\n");
543 if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
545 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
549 } while (!(phyStatus & 0x0004));
552 printf("PHY auto neg complete! \n");
559 if (fec->xcv_type != SEVENWIRE)
560 mpc5xxx_fec_phydump (dev->name);
565 printf("mpc5xxx_fec_init_phy... Done \n");
571 /********************************************************************/
572 static void mpc5xxx_fec_halt(struct eth_device *dev)
574 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
575 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
576 int counter = 0xffff;
579 if (fec->xcv_type != SEVENWIRE)
580 mpc5xxx_fec_phydump (dev->name);
584 * mask FEC chip interrupts
589 * issue graceful stop command to the FEC transmitter if necessary
591 fec->eth->x_cntrl |= 0x00000001;
594 * wait for graceful stop to register
596 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
599 * Disable SmartDMA tasks
601 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
602 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
605 * Turn on COMM bus prefetch in the MPC5200 BestComm after we're
606 * done. It doesn't work w/ the current receive task.
608 sdma->PtdCntrl &= ~0x00000001;
611 * Disable the Ethernet Controller
613 fec->eth->ecntrl &= 0xfffffffd;
616 * Clear FIFO status registers
618 fec->eth->rfifo_status &= 0x00700000;
619 fec->eth->tfifo_status &= 0x00700000;
621 fec->eth->reset_cntrl = 0x01000000;
624 * Issue a reset command to the FEC chip
626 fec->eth->ecntrl |= 0x1;
629 * wait at least 16 clock cycles
633 /* don't leave the MII speed set to zero */
634 if (fec->xcv_type != SEVENWIRE) {
636 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
637 * and do not drop the Preamble.
638 * No MII for 7-wire mode
640 fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
644 printf("Ethernet task stopped\n");
649 /********************************************************************/
651 static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
653 uint16 phyAddr = CONFIG_PHY_ADDR;
656 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
657 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
659 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
660 printf("\nphyStatus: 0x%04x\n", phyStatus);
661 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
662 printf("ievent: 0x%08x\n", fec->eth->ievent);
663 printf("x_status: 0x%08x\n", fec->eth->x_status);
664 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
666 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
667 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
668 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
669 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
670 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
671 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
675 static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
677 uint16 phyAddr = CONFIG_PHY_ADDR;
680 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
681 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
683 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
684 printf("\nphyStatus: 0x%04x\n", phyStatus);
685 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
686 printf("ievent: 0x%08x\n", fec->eth->ievent);
687 printf("x_status: 0x%08x\n", fec->eth->x_status);
688 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
690 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
691 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
692 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
693 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
694 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
695 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
700 /********************************************************************/
702 static int mpc5xxx_fec_send(struct eth_device *dev, void *eth_data,
706 * This routine transmits one frame. This routine only accepts
707 * 6-byte Ethernet addresses.
709 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
710 volatile FEC_TBD *pTbd;
713 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
714 tfifo_print(dev->name, fec);
718 * Clear Tx BD ring at first
720 mpc5xxx_fec_tbd_scrub(fec);
723 * Check for valid length of data.
725 if ((data_length > 1500) || (data_length <= 0)) {
730 * Check the number of vacant TxBDs.
732 if (fec->cleanTbdNum < 1) {
734 printf("No available TxBDs ...\n");
740 * Get the first TxBD to send the mac header
742 pTbd = &fec->tbdBase[fec->tbdIndex];
743 pTbd->dataLength = data_length;
744 pTbd->dataPointer = (uint32)eth_data;
745 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
746 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
749 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
755 if (fec->xcv_type != SEVENWIRE) {
757 miiphy_read(dev->name, 0, 0x1, &phyStatus);
761 * Enable SmartDMA transmit task
765 tfifo_print(dev->name, fec);
767 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
769 tfifo_print(dev->name, fec);
775 fec->cleanTbdNum -= 1;
777 #if (DEBUG & 0x129) && (DEBUG & 0x80000000)
778 printf ("smartDMA ethernet Tx task enabled\n");
781 * wait until frame is sent .
783 while (pTbd->status & FEC_TBD_READY) {
786 printf ("TDB status = %04x\n", pTbd->status);
794 /********************************************************************/
795 static int mpc5xxx_fec_recv(struct eth_device *dev)
798 * This command pulls one frame from the card
800 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
801 volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
802 unsigned long ievent;
803 int frame_length, len = 0;
805 uchar buff[FEC_MAX_PKT_SIZE];
808 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
815 * Check if any critical events have happened
817 ievent = fec->eth->ievent;
818 fec->eth->ievent = ievent;
819 if (ievent & 0x20060000) {
820 /* BABT, Rx/Tx FIFO errors */
821 mpc5xxx_fec_halt(dev);
822 mpc5xxx_fec_init(dev, NULL);
825 if (ievent & 0x80000000) {
826 /* Heartbeat error */
827 fec->eth->x_cntrl |= 0x00000001;
829 if (ievent & 0x10000000) {
830 /* Graceful stop complete */
831 if (fec->eth->x_cntrl & 0x00000001) {
832 mpc5xxx_fec_halt(dev);
833 fec->eth->x_cntrl &= ~0x00000001;
834 mpc5xxx_fec_init(dev, NULL);
838 if (!(pRbd->status & FEC_RBD_EMPTY)) {
839 if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
840 ((pRbd->dataLength - 4) > 14)) {
843 * Get buffer address and size
845 frame = (NBUF *)pRbd->dataPointer;
846 frame_length = pRbd->dataLength - 4;
851 printf("recv data hdr:");
852 for (i = 0; i < 14; i++)
853 printf("%x ", *(frame->head + i));
858 * Fill the buffer and pass it to upper layers
860 memcpy(buff, frame->head, 14);
861 memcpy(buff + 14, frame->data, frame_length);
862 NetReceive(buff, frame_length);
866 * Reset buffer descriptor as empty
868 mpc5xxx_fec_rbd_clean(fec, pRbd);
870 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
875 /********************************************************************/
876 int mpc5xxx_fec_initialize(bd_t * bis)
878 mpc5xxx_fec_priv *fec;
879 struct eth_device *dev;
881 char env_enetaddr[6];
884 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
885 dev = (struct eth_device *)malloc(sizeof(*dev));
886 memset(dev, 0, sizeof *dev);
888 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
889 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
890 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
891 #if defined(CONFIG_MPC5xxx_FEC_MII100)
892 fec->xcv_type = MII100;
893 #elif defined(CONFIG_MPC5xxx_FEC_MII10)
894 fec->xcv_type = MII10;
895 #elif defined(CONFIG_MPC5xxx_FEC_SEVENWIRE)
896 fec->xcv_type = SEVENWIRE;
898 #error fec->xcv_type not initialized.
900 if (fec->xcv_type != SEVENWIRE) {
902 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
903 * and do not drop the Preamble.
904 * No MII for 7-wire mode
906 fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
909 dev->priv = (void *)fec;
910 dev->iobase = MPC5XXX_FEC;
911 dev->init = mpc5xxx_fec_init;
912 dev->halt = mpc5xxx_fec_halt;
913 dev->send = mpc5xxx_fec_send;
914 dev->recv = mpc5xxx_fec_recv;
916 sprintf(dev->name, "FEC");
919 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
920 miiphy_register (dev->name,
921 fec5xxx_miiphy_read, fec5xxx_miiphy_write);
925 * Try to set the mac address now. The fec mac address is
926 * a garbage after reset. When not using fec for booting
927 * the Linux fec driver will try to work with this garbage.
929 tmp = getenv("ethaddr");
931 for (i=0; i<6; i++) {
932 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
934 tmp = (*end) ? end+1 : end;
936 mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
942 /* MII-interface related functions */
943 /********************************************************************/
944 int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
946 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
947 uint32 reg; /* convenient holder for the PHY register */
948 uint32 phy; /* convenient holder for the PHY */
949 int timeout = 0xffff;
952 * reading from any PHY's register is done by properly
953 * programming the FEC's MII data register.
955 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
956 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
958 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
961 * wait for the related interrupt
963 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
967 printf ("Read MDIO failed...\n");
973 * clear mii interrupt bit
975 eth->ievent = 0x00800000;
978 * it's now safe to read the PHY's register
980 *retVal = (uint16) eth->mii_data;
985 /********************************************************************/
986 int fec5xxx_miiphy_write(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
988 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
989 uint32 reg; /* convenient holder for the PHY register */
990 uint32 phy; /* convenient holder for the PHY */
991 int timeout = 0xffff;
993 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
994 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
996 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
997 FEC_MII_DATA_TA | phy | reg | data);
1000 * wait for the MII interrupt
1002 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
1006 printf ("Write MDIO failed...\n");
1012 * clear MII interrupt bit
1014 eth->ievent = 0x00800000;