3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
7 * Ingo Assmus <ingo.assmus@keymile.com>
9 * based on - Driver for MV64360X ethernet ports
10 * Copyright (C) 2002 rabeeh@galileo.co.il
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
36 #include <asm/errno.h>
37 #include <asm/types.h>
38 #include <asm/system.h>
39 #include <asm/byteorder.h>
40 #include <asm/arch/cpu.h>
42 #if defined(CONFIG_KIRKWOOD)
43 #include <asm/arch/kirkwood.h>
44 #elif defined(CONFIG_ORION5X)
45 #include <asm/arch/orion5x.h>
50 DECLARE_GLOBAL_DATA_PTR;
52 #define MV_PHY_ADR_REQUEST 0xee
53 #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
56 * smi_reg_read - miiphy_read callback function.
58 * Returns 16bit phy register value, or 0xffff on error
60 static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
62 struct eth_device *dev = eth_get_dev_by_name(devname);
63 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
64 struct mvgbe_registers *regs = dmvgbe->regs;
68 /* Phyadr read request */
69 if (phy_adr == MV_PHY_ADR_REQUEST &&
70 reg_ofs == MV_PHY_ADR_REQUEST) {
72 *data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK);
75 /* check parameters */
76 if (phy_adr > PHYADR_MASK) {
77 printf("Err..(%s) Invalid PHY address %d\n",
78 __FUNCTION__, phy_adr);
81 if (reg_ofs > PHYREG_MASK) {
82 printf("Err..(%s) Invalid register offset %d\n",
83 __FUNCTION__, reg_ofs);
87 timeout = MVGBE_PHY_SMI_TIMEOUT;
88 /* wait till the SMI is not busy */
90 /* read smi register */
91 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
93 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
96 } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
98 /* fill the phy address and regiser offset and read opcode */
99 smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
100 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS)
101 | MVGBE_PHY_SMI_OPCODE_READ;
103 /* write the smi register */
104 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
106 /*wait till read value is ready */
107 timeout = MVGBE_PHY_SMI_TIMEOUT;
110 /* read smi register */
111 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
112 if (timeout-- == 0) {
113 printf("Err..(%s) SMI read ready timeout\n",
117 } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK));
119 /* Wait for the data to update in the SMI register */
120 for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++)
123 *data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK);
125 debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
132 * smi_reg_write - imiiphy_write callback function.
134 * Returns 0 if write succeed, -EINVAL on bad parameters
137 static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
139 struct eth_device *dev = eth_get_dev_by_name(devname);
140 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
141 struct mvgbe_registers *regs = dmvgbe->regs;
145 /* Phyadr write request*/
146 if (phy_adr == MV_PHY_ADR_REQUEST &&
147 reg_ofs == MV_PHY_ADR_REQUEST) {
148 MVGBE_REG_WR(regs->phyadr, data);
152 /* check parameters */
153 if (phy_adr > PHYADR_MASK) {
154 printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
157 if (reg_ofs > PHYREG_MASK) {
158 printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
162 /* wait till the SMI is not busy */
163 timeout = MVGBE_PHY_SMI_TIMEOUT;
165 /* read smi register */
166 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
167 if (timeout-- == 0) {
168 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
171 } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
173 /* fill the phy addr and reg offset and write opcode and data */
174 smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);
175 smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
176 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS);
177 smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ;
179 /* write the smi register */
180 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
185 /* Stop and checks all queues */
186 static void stop_queue(u32 * qreg)
190 reg_data = readl(qreg);
192 if (reg_data & 0xFF) {
193 /* Issue stop command for active channels only */
194 writel((reg_data << 8), qreg);
196 /* Wait for all queue activity to terminate. */
199 * Check port cause register that all queues
202 reg_data = readl(qreg);
204 while (reg_data & 0xFF);
209 * set_access_control - Config address decode parameters for Ethernet unit
211 * This function configures the address decode parameters for the Gigabit
212 * Ethernet Controller according the given parameters struct.
214 * @regs Register struct pointer.
215 * @param Address decode parameter struct.
217 static void set_access_control(struct mvgbe_registers *regs,
218 struct mvgbe_winparam *param)
222 /* Set access control register */
223 access_prot_reg = MVGBE_REG_RD(regs->epap);
224 /* clear window permission */
225 access_prot_reg &= (~(3 << (param->win * 2)));
226 access_prot_reg |= (param->access_ctrl << (param->win * 2));
227 MVGBE_REG_WR(regs->epap, access_prot_reg);
229 /* Set window Size reg (SR) */
230 MVGBE_REG_WR(regs->barsz[param->win].size,
231 (((param->size / 0x10000) - 1) << 16));
233 /* Set window Base address reg (BA) */
234 MVGBE_REG_WR(regs->barsz[param->win].bar,
235 (param->target | param->attrib | param->base_addr));
236 /* High address remap reg (HARR) */
238 MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);
240 /* Base address enable reg (BARER) */
241 if (param->enable == 1)
242 MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win));
244 MVGBE_REG_BITS_SET(regs->bare, (1 << param->win));
247 static void set_dram_access(struct mvgbe_registers *regs)
249 struct mvgbe_winparam win_param;
252 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
253 /* Set access parameters for DRAM bank i */
254 win_param.win = i; /* Use Ethernet window i */
255 /* Window target - DDR */
256 win_param.target = MVGBE_TARGET_DRAM;
257 /* Enable full access */
258 win_param.access_ctrl = EWIN_ACCESS_FULL;
259 win_param.high_addr = 0;
260 /* Get bank base and size */
261 win_param.base_addr = gd->bd->bi_dram[i].start;
262 win_param.size = gd->bd->bi_dram[i].size;
263 if (win_param.size == 0)
264 win_param.enable = 0;
266 win_param.enable = 1; /* Enable the access */
268 /* Enable DRAM bank */
271 win_param.attrib = EBAR_DRAM_CS0;
274 win_param.attrib = EBAR_DRAM_CS1;
277 win_param.attrib = EBAR_DRAM_CS2;
280 win_param.attrib = EBAR_DRAM_CS3;
283 /* invalid bank, disable access */
284 win_param.enable = 0;
285 win_param.attrib = 0;
288 /* Set the access control for address window(EPAPR) RD/WR */
289 set_access_control(regs, &win_param);
294 * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
296 * Go through all the DA filter tables (Unicast, Special Multicast & Other
297 * Multicast) and set each entry to 0.
299 static void port_init_mac_tables(struct mvgbe_registers *regs)
303 /* Clear DA filter unicast table (Ex_dFUT) */
304 for (table_index = 0; table_index < 4; ++table_index)
305 MVGBE_REG_WR(regs->dfut[table_index], 0);
307 for (table_index = 0; table_index < 64; ++table_index) {
308 /* Clear DA filter special multicast table (Ex_dFSMT) */
309 MVGBE_REG_WR(regs->dfsmt[table_index], 0);
310 /* Clear DA filter other multicast table (Ex_dFOMT) */
311 MVGBE_REG_WR(regs->dfomt[table_index], 0);
316 * port_uc_addr - This function Set the port unicast address table
318 * This function locates the proper entry in the Unicast table for the
319 * specified MAC nibble and sets its properties according to function
321 * This function add/removes MAC addresses from the port unicast address
324 * @uc_nibble Unicast MAC Address last nibble.
325 * @option 0 = Add, 1 = remove address.
327 * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
329 static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble,
336 /* Locate the Unicast table entry */
337 uc_nibble = (0xf & uc_nibble);
338 /* Register offset from unicast table base */
339 tbl_offset = (uc_nibble / 4);
340 /* Entry offset within the above register */
341 reg_offset = uc_nibble % 4;
344 case REJECT_MAC_ADDR:
346 * Clear accepts frame bit at specified unicast
349 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
350 unicast_reg &= (0xFF << (8 * reg_offset));
351 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
353 case ACCEPT_MAC_ADDR:
354 /* Set accepts frame bit at unicast DA filter table entry */
355 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
356 unicast_reg &= (0xFF << (8 * reg_offset));
357 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
358 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
367 * port_uc_addr_set - This function Set the port Unicast address.
369 static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr)
374 mac_l = (p_addr[4] << 8) | (p_addr[5]);
375 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
378 MVGBE_REG_WR(regs->macal, mac_l);
379 MVGBE_REG_WR(regs->macah, mac_h);
381 /* Accept frames of this address */
382 port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
386 * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
388 static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe)
390 struct mvgbe_rxdesc *p_rx_desc;
393 /* initialize the Rx descriptors ring */
394 p_rx_desc = dmvgbe->p_rxdesc;
395 for (i = 0; i < RINGSZ; i++) {
397 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
398 p_rx_desc->buf_size = PKTSIZE_ALIGN;
399 p_rx_desc->byte_cnt = 0;
400 p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN;
401 if (i == (RINGSZ - 1))
402 p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc;
404 p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *)
405 ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE);
406 p_rx_desc = p_rx_desc->nxtdesc_p;
409 dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
412 static int mvgbe_init(struct eth_device *dev)
414 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
415 struct mvgbe_registers *regs = dmvgbe->regs;
416 #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
417 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
421 mvgbe_init_rx_desc_ring(dmvgbe);
423 /* Clear the ethernet port interrupts */
424 MVGBE_REG_WR(regs->ic, 0);
425 MVGBE_REG_WR(regs->ice, 0);
426 /* Unmask RX buffer and TX end interrupt */
427 MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
428 /* Unmask phy and link status changes interrupts */
429 MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
431 set_dram_access(regs);
432 port_init_mac_tables(regs);
433 port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
435 /* Assign port configuration and command. */
436 MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
437 MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
438 MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
440 /* Assign port SDMA configuration */
441 MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
442 MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
443 MVGBE_REG_WR(regs->tqx[0].tqxtbc,
444 (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
445 /* Turn off the port/RXUQ bandwidth limitation */
446 MVGBE_REG_WR(regs->pmtu, 0);
448 /* Set maximum receive buffer to 9700 bytes */
449 MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
450 | (MVGBE_REG_RD(regs->psc0) & MRU_MASK));
452 /* Enable port initially */
453 MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);
456 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
457 * disable the leaky bucket mechanism .
459 MVGBE_REG_WR(regs->pmtu, 0);
461 /* Assignment of Rx CRDB of given RXUQ */
462 MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
463 /* ensure previous write is done before enabling Rx DMA */
465 /* Enable port Rx. */
466 MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
468 #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
469 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
470 /* Wait up to 5s for the link status */
471 for (i = 0; i < 5; i++) {
474 miiphy_read(dev->name, MV_PHY_ADR_REQUEST,
475 MV_PHY_ADR_REQUEST, &phyadr);
476 /* Return if we get link up */
477 if (miiphy_link(dev->name, phyadr))
482 printf("No link on %s\n", dev->name);
488 static int mvgbe_halt(struct eth_device *dev)
490 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
491 struct mvgbe_registers *regs = dmvgbe->regs;
493 /* Disable all gigE address decoder */
494 MVGBE_REG_WR(regs->bare, 0x3f);
496 stop_queue(®s->tqc);
497 stop_queue(®s->rqc);
500 MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN);
501 /* Set port is not reset */
502 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4);
503 #ifdef CONFIG_SYS_MII_MODE
504 /* Set MMI interface up */
505 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3);
507 /* Disable & mask ethernet port interrupts */
508 MVGBE_REG_WR(regs->ic, 0);
509 MVGBE_REG_WR(regs->ice, 0);
510 MVGBE_REG_WR(regs->pim, 0);
511 MVGBE_REG_WR(regs->peim, 0);
516 static int mvgbe_write_hwaddr(struct eth_device *dev)
518 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
519 struct mvgbe_registers *regs = dmvgbe->regs;
521 /* Programs net device MAC address after initialization */
522 port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
526 static int mvgbe_send(struct eth_device *dev, void *dataptr,
529 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
530 struct mvgbe_registers *regs = dmvgbe->regs;
531 struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
532 void *p = (void *)dataptr;
536 /* Copy buffer if it's misaligned */
537 if ((u32) dataptr & 0x07) {
538 if (datasize > PKTSIZE_ALIGN) {
539 printf("Non-aligned data too large (%d)\n",
544 memcpy(dmvgbe->p_aligned_txbuf, p, datasize);
545 p = dmvgbe->p_aligned_txbuf;
548 p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC;
549 p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC;
550 p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA;
551 p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT;
552 p_txdesc->buf_ptr = (u8 *) p;
553 p_txdesc->byte_cnt = datasize;
555 /* Set this tc desc as zeroth TXUQ */
556 txuq0_reg_addr = (u32)®s->tcqdp[TXUQ];
557 writel((u32) p_txdesc, txuq0_reg_addr);
559 /* ensure tx desc writes above are performed before we start Tx DMA */
562 /* Apply send command using zeroth TXUQ */
563 MVGBE_REG_WR(regs->tqc, (1 << TXUQ));
566 * wait for packet xmit completion
568 cmd_sts = readl(&p_txdesc->cmd_sts);
569 while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) {
570 /* return fail if error is detected */
571 if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) ==
572 (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) &&
573 cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) {
574 printf("Err..(%s) in xmit packet\n", __FUNCTION__);
577 cmd_sts = readl(&p_txdesc->cmd_sts);
582 static int mvgbe_recv(struct eth_device *dev)
584 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
585 struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
588 u32 rxdesc_curr_addr;
590 /* wait untill rx packet available or timeout */
592 if (timeout < MVGBE_PHY_SMI_TIMEOUT)
595 debug("%s time out...\n", __FUNCTION__);
598 } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA);
600 if (p_rxdesc_curr->byte_cnt != 0) {
601 debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
602 __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
603 (u32) p_rxdesc_curr->buf_ptr,
604 (u32) p_rxdesc_curr->cmd_sts);
608 * In case received a packet without first/last bits on
609 * OR the error summary bit is on,
610 * the packets needs to be dropeed.
612 cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
615 (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC))
616 != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) {
618 printf("Err..(%s) Dropping packet spread on"
619 " multiple descriptors\n", __FUNCTION__);
621 } else if (cmd_sts & MVGBE_ERROR_SUMMARY) {
623 printf("Err..(%s) Dropping packet with errors\n",
627 /* !!! call higher layer processing */
628 debug("%s: Sending Received packet to"
629 " upper layer (NetReceive)\n", __FUNCTION__);
631 /* let the upper layer handle the packet */
632 NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
633 (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
636 * free these descriptors and point next in the ring
638 p_rxdesc_curr->cmd_sts =
639 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
640 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
641 p_rxdesc_curr->byte_cnt = 0;
643 rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr;
644 writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr);
649 int mvgbe_initialize(bd_t *bis)
651 struct mvgbe_device *dmvgbe;
652 struct eth_device *dev;
654 u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
656 for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
657 /*skip if port is configured not to use */
658 if (used_ports[devnum] == 0)
661 dmvgbe = malloc(sizeof(struct mvgbe_device));
666 memset(dmvgbe, 0, sizeof(struct mvgbe_device));
669 (struct mvgbe_rxdesc *)memalign(PKTALIGN,
670 MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1);
672 if (!dmvgbe->p_rxdesc)
675 dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN,
676 RINGSZ*PKTSIZE_ALIGN + 1);
678 if (!dmvgbe->p_rxbuf)
681 dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
683 if (!dmvgbe->p_aligned_txbuf)
686 dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign(
687 PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
689 if (!dmvgbe->p_txdesc) {
690 free(dmvgbe->p_aligned_txbuf);
692 free(dmvgbe->p_rxbuf);
694 free(dmvgbe->p_rxdesc);
698 printf("Err.. %s Failed to allocate memory\n",
705 /* must be less than NAMESIZE (16) */
706 sprintf(dev->name, "egiga%d", devnum);
710 dmvgbe->regs = (void *)MVGBE0_BASE;
712 #if defined(MVGBE1_BASE)
714 dmvgbe->regs = (void *)MVGBE1_BASE;
717 default: /* this should never happen */
718 printf("Err..(%s) Invalid device number %d\n",
719 __FUNCTION__, devnum);
723 dev->init = (void *)mvgbe_init;
724 dev->halt = (void *)mvgbe_halt;
725 dev->send = (void *)mvgbe_send;
726 dev->recv = (void *)mvgbe_recv;
727 dev->write_hwaddr = (void *)mvgbe_write_hwaddr;
731 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
732 miiphy_register(dev->name, smi_reg_read, smi_reg_write);
733 /* Set phy address of the port */
734 miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
735 MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);