3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
7 * Ingo Assmus <ingo.assmus@keymile.com>
9 * based on - Driver for MV64360X ethernet ports
10 * Copyright (C) 2002 rabeeh@galileo.co.il
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
35 #include <asm/errno.h>
36 #include <asm/types.h>
37 #include <asm/byteorder.h>
38 #include <asm/arch/kirkwood.h>
41 DECLARE_GLOBAL_DATA_PTR;
43 #define KIRKWOOD_PHY_ADR_REQUEST 0xee
44 #define KWGBE_SMI_REG (((struct kwgbe_registers *)KW_EGIGA0_BASE)->smi)
47 * smi_reg_read - miiphy_read callback function.
49 * Returns 16bit phy register value, or 0xffff on error
51 static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
53 struct eth_device *dev = eth_get_dev_by_name(devname);
54 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
55 struct kwgbe_registers *regs = dkwgbe->regs;
59 /* Phyadr read request */
60 if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
61 reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
63 *data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK);
66 /* check parameters */
67 if (phy_adr > PHYADR_MASK) {
68 printf("Err..(%s) Invalid PHY address %d\n",
69 __FUNCTION__, phy_adr);
72 if (reg_ofs > PHYREG_MASK) {
73 printf("Err..(%s) Invalid register offset %d\n",
74 __FUNCTION__, reg_ofs);
78 timeout = KWGBE_PHY_SMI_TIMEOUT;
79 /* wait till the SMI is not busy */
81 /* read smi register */
82 smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
84 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
87 } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
89 /* fill the phy address and regiser offset and read opcode */
90 smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
91 | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS)
92 | KWGBE_PHY_SMI_OPCODE_READ;
94 /* write the smi register */
95 KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
97 /*wait till read value is ready */
98 timeout = KWGBE_PHY_SMI_TIMEOUT;
101 /* read smi register */
102 smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
103 if (timeout-- == 0) {
104 printf("Err..(%s) SMI read ready timeout\n",
108 } while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK));
110 /* Wait for the data to update in the SMI register */
111 for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ;
113 *data = (u16) (KWGBEREG_RD(KWGBE_SMI_REG) & KWGBE_PHY_SMI_DATA_MASK);
115 debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
122 * smi_reg_write - imiiphy_write callback function.
124 * Returns 0 if write succeed, -EINVAL on bad parameters
127 static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
129 struct eth_device *dev = eth_get_dev_by_name(devname);
130 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
131 struct kwgbe_registers *regs = dkwgbe->regs;
135 /* Phyadr write request*/
136 if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
137 reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
138 KWGBEREG_WR(regs->phyadr, data);
142 /* check parameters */
143 if (phy_adr > PHYADR_MASK) {
144 printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
147 if (reg_ofs > PHYREG_MASK) {
148 printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
152 /* wait till the SMI is not busy */
153 timeout = KWGBE_PHY_SMI_TIMEOUT;
155 /* read smi register */
156 smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
157 if (timeout-- == 0) {
158 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
161 } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
163 /* fill the phy addr and reg offset and write opcode and data */
164 smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS);
165 smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
166 | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS);
167 smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ;
169 /* write the smi register */
170 KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
175 /* Stop and checks all queues */
176 static void stop_queue(u32 * qreg)
180 reg_data = readl(qreg);
182 if (reg_data & 0xFF) {
183 /* Issue stop command for active channels only */
184 writel((reg_data << 8), qreg);
186 /* Wait for all queue activity to terminate. */
189 * Check port cause register that all queues
192 reg_data = readl(qreg);
194 while (reg_data & 0xFF);
199 * set_access_control - Config address decode parameters for Ethernet unit
201 * This function configures the address decode parameters for the Gigabit
202 * Ethernet Controller according the given parameters struct.
204 * @regs Register struct pointer.
205 * @param Address decode parameter struct.
207 static void set_access_control(struct kwgbe_registers *regs,
208 struct kwgbe_winparam *param)
212 /* Set access control register */
213 access_prot_reg = KWGBEREG_RD(regs->epap);
214 /* clear window permission */
215 access_prot_reg &= (~(3 << (param->win * 2)));
216 access_prot_reg |= (param->access_ctrl << (param->win * 2));
217 KWGBEREG_WR(regs->epap, access_prot_reg);
219 /* Set window Size reg (SR) */
220 KWGBEREG_WR(regs->barsz[param->win].size,
221 (((param->size / 0x10000) - 1) << 16));
223 /* Set window Base address reg (BA) */
224 KWGBEREG_WR(regs->barsz[param->win].bar,
225 (param->target | param->attrib | param->base_addr));
226 /* High address remap reg (HARR) */
228 KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr);
230 /* Base address enable reg (BARER) */
231 if (param->enable == 1)
232 KWGBEREG_BITS_RESET(regs->bare, (1 << param->win));
234 KWGBEREG_BITS_SET(regs->bare, (1 << param->win));
237 static void set_dram_access(struct kwgbe_registers *regs)
239 struct kwgbe_winparam win_param;
242 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
243 /* Set access parameters for DRAM bank i */
244 win_param.win = i; /* Use Ethernet window i */
245 /* Window target - DDR */
246 win_param.target = KWGBE_TARGET_DRAM;
247 /* Enable full access */
248 win_param.access_ctrl = EWIN_ACCESS_FULL;
249 win_param.high_addr = 0;
250 /* Get bank base and size */
251 win_param.base_addr = gd->bd->bi_dram[i].start;
252 win_param.size = gd->bd->bi_dram[i].size;
253 if (win_param.size == 0)
254 win_param.enable = 0;
256 win_param.enable = 1; /* Enable the access */
258 /* Enable DRAM bank */
261 win_param.attrib = EBAR_DRAM_CS0;
264 win_param.attrib = EBAR_DRAM_CS1;
267 win_param.attrib = EBAR_DRAM_CS2;
270 win_param.attrib = EBAR_DRAM_CS3;
273 /* invalid bank, disable access */
274 win_param.enable = 0;
275 win_param.attrib = 0;
278 /* Set the access control for address window(EPAPR) RD/WR */
279 set_access_control(regs, &win_param);
284 * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
286 * Go through all the DA filter tables (Unicast, Special Multicast & Other
287 * Multicast) and set each entry to 0.
289 static void port_init_mac_tables(struct kwgbe_registers *regs)
293 /* Clear DA filter unicast table (Ex_dFUT) */
294 for (table_index = 0; table_index < 4; ++table_index)
295 KWGBEREG_WR(regs->dfut[table_index], 0);
297 for (table_index = 0; table_index < 64; ++table_index) {
298 /* Clear DA filter special multicast table (Ex_dFSMT) */
299 KWGBEREG_WR(regs->dfsmt[table_index], 0);
300 /* Clear DA filter other multicast table (Ex_dFOMT) */
301 KWGBEREG_WR(regs->dfomt[table_index], 0);
306 * port_uc_addr - This function Set the port unicast address table
308 * This function locates the proper entry in the Unicast table for the
309 * specified MAC nibble and sets its properties according to function
311 * This function add/removes MAC addresses from the port unicast address
314 * @uc_nibble Unicast MAC Address last nibble.
315 * @option 0 = Add, 1 = remove address.
317 * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
319 static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
326 /* Locate the Unicast table entry */
327 uc_nibble = (0xf & uc_nibble);
328 /* Register offset from unicast table base */
329 tbl_offset = (uc_nibble / 4);
330 /* Entry offset within the above register */
331 reg_offset = uc_nibble % 4;
334 case REJECT_MAC_ADDR:
336 * Clear accepts frame bit at specified unicast
339 unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
340 unicast_reg &= (0xFF << (8 * reg_offset));
341 KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
343 case ACCEPT_MAC_ADDR:
344 /* Set accepts frame bit at unicast DA filter table entry */
345 unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
346 unicast_reg &= (0xFF << (8 * reg_offset));
347 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
348 KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
357 * port_uc_addr_set - This function Set the port Unicast address.
359 static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
364 mac_l = (p_addr[4] << 8) | (p_addr[5]);
365 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
368 KWGBEREG_WR(regs->macal, mac_l);
369 KWGBEREG_WR(regs->macah, mac_h);
371 /* Accept frames of this address */
372 port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
376 * kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
378 static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe)
380 struct kwgbe_rxdesc *p_rx_desc;
383 /* initialize the Rx descriptors ring */
384 p_rx_desc = dkwgbe->p_rxdesc;
385 for (i = 0; i < RINGSZ; i++) {
387 KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
388 p_rx_desc->buf_size = PKTSIZE_ALIGN;
389 p_rx_desc->byte_cnt = 0;
390 p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN;
391 if (i == (RINGSZ - 1))
392 p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc;
394 p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *)
395 ((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE);
396 p_rx_desc = p_rx_desc->nxtdesc_p;
399 dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc;
402 static int kwgbe_init(struct eth_device *dev)
404 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
405 struct kwgbe_registers *regs = dkwgbe->regs;
406 #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
407 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
411 kwgbe_init_rx_desc_ring(dkwgbe);
413 /* Clear the ethernet port interrupts */
414 KWGBEREG_WR(regs->ic, 0);
415 KWGBEREG_WR(regs->ice, 0);
416 /* Unmask RX buffer and TX end interrupt */
417 KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
418 /* Unmask phy and link status changes interrupts */
419 KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
421 set_dram_access(regs);
422 port_init_mac_tables(regs);
423 port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
425 /* Assign port configuration and command. */
426 KWGBEREG_WR(regs->pxc, PRT_CFG_VAL);
427 KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
428 KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
430 /* Assign port SDMA configuration */
431 KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
432 KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
433 KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
434 /* Turn off the port/RXUQ bandwidth limitation */
435 KWGBEREG_WR(regs->pmtu, 0);
437 /* Set maximum receive buffer to 9700 bytes */
438 KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE
439 | (KWGBEREG_RD(regs->psc0) & MRU_MASK));
441 /* Enable port initially */
442 KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN);
445 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
446 * disable the leaky bucket mechanism .
448 KWGBEREG_WR(regs->pmtu, 0);
450 /* Assignment of Rx CRDB of given RXUQ */
451 KWGBEREG_WR(regs->rxcdp[RXUQ], (u32) dkwgbe->p_rxdesc_curr);
452 /* ensure previous write is done before enabling Rx DMA */
454 /* Enable port Rx. */
455 KWGBEREG_WR(regs->rqc, (1 << RXUQ));
457 #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
458 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
459 /* Wait up to 5s for the link status */
460 for (i = 0; i < 5; i++) {
463 miiphy_read(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
464 KIRKWOOD_PHY_ADR_REQUEST, &phyadr);
465 /* Return if we get link up */
466 if (miiphy_link(dev->name, phyadr))
471 printf("No link on %s\n", dev->name);
477 static int kwgbe_halt(struct eth_device *dev)
479 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
480 struct kwgbe_registers *regs = dkwgbe->regs;
482 /* Disable all gigE address decoder */
483 KWGBEREG_WR(regs->bare, 0x3f);
485 stop_queue(®s->tqc);
486 stop_queue(®s->rqc);
489 KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN);
490 /* Set port is not reset */
491 KWGBEREG_BITS_RESET(regs->psc1, 1 << 4);
492 #ifdef CONFIG_SYS_MII_MODE
493 /* Set MMI interface up */
494 KWGBEREG_BITS_RESET(regs->psc1, 1 << 3);
496 /* Disable & mask ethernet port interrupts */
497 KWGBEREG_WR(regs->ic, 0);
498 KWGBEREG_WR(regs->ice, 0);
499 KWGBEREG_WR(regs->pim, 0);
500 KWGBEREG_WR(regs->peim, 0);
505 static int kwgbe_write_hwaddr(struct eth_device *dev)
507 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
508 struct kwgbe_registers *regs = dkwgbe->regs;
510 /* Programs net device MAC address after initialization */
511 port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
515 static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
518 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
519 struct kwgbe_registers *regs = dkwgbe->regs;
520 struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc;
521 void *p = (void *)dataptr;
524 /* Copy buffer if it's misaligned */
525 if ((u32) dataptr & 0x07) {
526 if (datasize > PKTSIZE_ALIGN) {
527 printf("Non-aligned data too large (%d)\n",
532 memcpy(dkwgbe->p_aligned_txbuf, p, datasize);
533 p = dkwgbe->p_aligned_txbuf;
536 p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC;
537 p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC;
538 p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA;
539 p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT;
540 p_txdesc->buf_ptr = (u8 *) p;
541 p_txdesc->byte_cnt = datasize;
543 /* Set this tc desc as zeroth TXUQ */
544 KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
546 /* ensure tx desc writes above are performed before we start Tx DMA */
549 /* Apply send command using zeroth TXUQ */
550 KWGBEREG_WR(regs->tqc, (1 << TXUQ));
553 * wait for packet xmit completion
555 cmd_sts = readl(&p_txdesc->cmd_sts);
556 while (cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) {
557 /* return fail if error is detected */
558 if ((cmd_sts & (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME)) ==
559 (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME) &&
560 cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) {
561 printf("Err..(%s) in xmit packet\n", __FUNCTION__);
564 cmd_sts = readl(&p_txdesc->cmd_sts);
569 static int kwgbe_recv(struct eth_device *dev)
571 struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
572 struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr;
576 /* wait untill rx packet available or timeout */
578 if (timeout < KWGBE_PHY_SMI_TIMEOUT)
581 debug("%s time out...\n", __FUNCTION__);
584 } while (readl(&p_rxdesc_curr->cmd_sts) & KWGBE_BUFFER_OWNED_BY_DMA);
586 if (p_rxdesc_curr->byte_cnt != 0) {
587 debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
588 __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
589 (u32) p_rxdesc_curr->buf_ptr,
590 (u32) p_rxdesc_curr->cmd_sts);
594 * In case received a packet without first/last bits on
595 * OR the error summary bit is on,
596 * the packets needs to be dropeed.
598 cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
601 (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC))
602 != (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) {
604 printf("Err..(%s) Dropping packet spread on"
605 " multiple descriptors\n", __FUNCTION__);
607 } else if (cmd_sts & KWGBE_ERROR_SUMMARY) {
609 printf("Err..(%s) Dropping packet with errors\n",
613 /* !!! call higher layer processing */
614 debug("%s: Sending Received packet to"
615 " upper layer (NetReceive)\n", __FUNCTION__);
617 /* let the upper layer handle the packet */
618 NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
619 (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
622 * free these descriptors and point next in the ring
624 p_rxdesc_curr->cmd_sts =
625 KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
626 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
627 p_rxdesc_curr->byte_cnt = 0;
629 writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dkwgbe->p_rxdesc_curr);
634 int kirkwood_egiga_initialize(bd_t * bis)
636 struct kwgbe_device *dkwgbe;
637 struct eth_device *dev;
640 u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS;
642 for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) {
643 /*skip if port is configured not to use */
644 if (used_ports[devnum] == 0)
647 if (!(dkwgbe = malloc(sizeof(struct kwgbe_device))))
650 memset(dkwgbe, 0, sizeof(struct kwgbe_device));
652 if (!(dkwgbe->p_rxdesc =
653 (struct kwgbe_rxdesc *)memalign(PKTALIGN,
654 KW_RXQ_DESC_ALIGNED_SIZE
658 if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ
659 * PKTSIZE_ALIGN + 1)))
662 if (!(dkwgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN)))
665 if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *)
666 memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) {
667 free(dkwgbe->p_aligned_txbuf);
669 free(dkwgbe->p_rxbuf);
671 free(dkwgbe->p_rxdesc);
675 printf("Err.. %s Failed to allocate memory\n",
682 /* must be less than NAMESIZE (16) */
683 sprintf(dev->name, "egiga%d", devnum);
685 /* Extract the MAC address from the environment */
688 dkwgbe->regs = (void *)KW_EGIGA0_BASE;
692 dkwgbe->regs = (void *)KW_EGIGA1_BASE;
695 default: /* this should never happen */
696 printf("Err..(%s) Invalid device number %d\n",
697 __FUNCTION__, devnum);
701 while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
702 /* Generate Private MAC addr if not set */
703 dev->enetaddr[0] = 0x02;
704 dev->enetaddr[1] = 0x50;
705 dev->enetaddr[2] = 0x43;
706 #if defined (CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION)
707 /* Generate fixed lower MAC half using devnum */
708 dev->enetaddr[3] = 0;
709 dev->enetaddr[4] = 0;
710 dev->enetaddr[5] = devnum;
712 /* Generate random lower MAC half */
713 dev->enetaddr[3] = get_random_hex();
714 dev->enetaddr[4] = get_random_hex();
715 dev->enetaddr[5] = get_random_hex();
717 eth_setenv_enetaddr(s, dev->enetaddr);
720 dev->init = (void *)kwgbe_init;
721 dev->halt = (void *)kwgbe_halt;
722 dev->send = (void *)kwgbe_send;
723 dev->recv = (void *)kwgbe_recv;
724 dev->write_hwaddr = (void *)kwgbe_write_hwaddr;
728 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
729 miiphy_register(dev->name, smi_reg_read, smi_reg_write);
730 /* Set phy address of the port */
731 miiphy_write(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
732 KIRKWOOD_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);