2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
9 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
18 #include <dm/device-internal.h>
25 #include <linux/errno.h>
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/soc.h>
31 #include <linux/compat.h>
32 #include <linux/mbus.h>
33 #include <asm-generic/gpio.h>
34 #include <fdt_support.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 /* Some linux -> U-Boot compatibility stuff */
39 #define netdev_err(dev, fmt, args...) \
41 #define netdev_warn(dev, fmt, args...) \
43 #define netdev_info(dev, fmt, args...) \
45 #define netdev_dbg(dev, fmt, args...) \
48 #define ETH_ALEN 6 /* Octets in one ethernet addr */
50 #define __verify_pcpu_ptr(ptr) \
52 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
56 #define VERIFY_PERCPU_PTR(__p) \
58 __verify_pcpu_ptr(__p); \
59 (typeof(*(__p)) __kernel __force *)(__p); \
62 #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
63 #define smp_processor_id() 0
64 #define num_present_cpus() 1
65 #define for_each_present_cpu(cpu) \
66 for ((cpu) = 0; (cpu) < 1; (cpu)++)
68 #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
70 #define CONFIG_NR_CPUS 1
71 #define ETH_HLEN ETHER_HDR_SIZE /* Total octets in header */
73 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
74 #define WRAP (2 + ETH_HLEN + 4 + 32)
76 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
78 #define MVPP2_SMI_TIMEOUT 10000
80 /* RX Fifo Registers */
81 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
82 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
83 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
84 #define MVPP2_RX_FIFO_INIT_REG 0x64
86 /* RX DMA Top Registers */
87 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
88 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
89 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
90 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
91 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
92 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
93 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
94 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
95 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
96 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
97 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
98 #define MVPP2_RXQ_POOL_LONG_OFFS 24
99 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
100 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
101 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
102 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
103 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
105 /* Parser Registers */
106 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
107 #define MVPP2_PRS_PORT_LU_MAX 0xf
108 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
109 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
110 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
111 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
112 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
113 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
114 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
115 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
116 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
117 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
118 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
119 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
120 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
121 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
122 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
124 /* Classifier Registers */
125 #define MVPP2_CLS_MODE_REG 0x1800
126 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
127 #define MVPP2_CLS_PORT_WAY_REG 0x1810
128 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
129 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
130 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
131 #define MVPP2_CLS_LKP_TBL_REG 0x1818
132 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
133 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
134 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
135 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
136 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
137 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
138 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
139 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
140 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
141 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
142 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
143 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
145 /* Descriptor Manager Top Registers */
146 #define MVPP2_RXQ_NUM_REG 0x2040
147 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
148 #define MVPP22_DESC_ADDR_OFFS 8
149 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
150 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
151 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
152 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
153 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
154 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
155 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
156 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
157 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
158 #define MVPP2_RXQ_THRESH_REG 0x204c
159 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
160 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
161 #define MVPP2_RXQ_INDEX_REG 0x2050
162 #define MVPP2_TXQ_NUM_REG 0x2080
163 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
164 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
165 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
166 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
167 #define MVPP2_TXQ_THRESH_REG 0x2094
168 #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
169 #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
170 #define MVPP2_TXQ_INDEX_REG 0x2098
171 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
172 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
173 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
174 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
175 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
176 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
177 #define MVPP2_TXQ_PENDING_REG 0x20a0
178 #define MVPP2_TXQ_PENDING_MASK 0x3fff
179 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
180 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
181 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
182 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
183 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
184 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
185 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
186 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
187 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
188 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
189 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
190 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
191 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
192 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
193 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
194 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
195 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
197 /* MBUS bridge registers */
198 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
199 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
200 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
201 #define MVPP2_BASE_ADDR_ENABLE 0x4060
203 /* AXI Bridge Registers */
204 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
205 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
206 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
207 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
208 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
209 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
210 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
211 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
212 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
213 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
214 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
215 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
217 /* Values for AXI Bridge registers */
218 #define MVPP22_AXI_ATTR_CACHE_OFFS 0
219 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
221 #define MVPP22_AXI_CODE_CACHE_OFFS 0
222 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4
224 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
225 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
226 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
228 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
229 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
231 /* Interrupt Cause and Mask registers */
232 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
233 #define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
235 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
236 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
237 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
238 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
240 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
241 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
243 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
244 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
245 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
246 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
248 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
249 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
250 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
251 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
252 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
253 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
254 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
255 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
256 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
257 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
258 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
259 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
260 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
261 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
262 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
263 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
264 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
265 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
267 /* Buffer Manager registers */
268 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
269 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
270 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
271 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
272 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
273 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
274 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
275 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
276 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
277 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
278 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
279 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
280 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
281 #define MVPP2_BM_START_MASK BIT(0)
282 #define MVPP2_BM_STOP_MASK BIT(1)
283 #define MVPP2_BM_STATE_MASK BIT(4)
284 #define MVPP2_BM_LOW_THRESH_OFFS 8
285 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
286 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
287 MVPP2_BM_LOW_THRESH_OFFS)
288 #define MVPP2_BM_HIGH_THRESH_OFFS 16
289 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
290 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
291 MVPP2_BM_HIGH_THRESH_OFFS)
292 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
293 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
294 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
295 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
296 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
297 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
298 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
299 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
300 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
301 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
302 #define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
303 #define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
304 #define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
305 #define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
306 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
307 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
308 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
309 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
310 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
311 #define MVPP21_BM_MC_RLS_REG 0x64c4
312 #define MVPP2_BM_MC_ID_MASK 0xfff
313 #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
314 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
315 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
316 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
317 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
318 #define MVPP22_BM_MC_RLS_REG 0x64d4
320 /* TX Scheduler registers */
321 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
322 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
323 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
324 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
325 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
326 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
327 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
328 #define MVPP2_TXP_MTU_MAX 0x7FFFF
329 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
330 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
331 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
332 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
333 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
334 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
335 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
336 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
337 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
338 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
339 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
340 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
341 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
342 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
344 /* TX general registers */
345 #define MVPP2_TX_SNOOP_REG 0x8800
346 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
347 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
350 #define MVPP2_SRC_ADDR_MIDDLE 0x24
351 #define MVPP2_SRC_ADDR_HIGH 0x28
352 #define MVPP2_PHY_AN_CFG0_REG 0x34
353 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
354 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
355 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
357 /* Per-port registers */
358 #define MVPP2_GMAC_CTRL_0_REG 0x0
359 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
360 #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
361 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
362 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
363 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
364 #define MVPP2_GMAC_CTRL_1_REG 0x4
365 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
366 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
367 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
368 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
369 #define MVPP2_GMAC_SA_LOW_OFFS 7
370 #define MVPP2_GMAC_CTRL_2_REG 0x8
371 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
372 #define MVPP2_GMAC_SGMII_MODE_MASK BIT(0)
373 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
374 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
375 #define MVPP2_GMAC_PORT_DIS_PADING_MASK BIT(5)
376 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
377 #define MVPP2_GMAC_CLK_125_BYPS_EN_MASK BIT(9)
378 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
379 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
380 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
381 #define MVPP2_GMAC_EN_PCS_AN BIT(2)
382 #define MVPP2_GMAC_AN_BYPASS_EN BIT(3)
383 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
384 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
385 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
386 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
387 #define MVPP2_GMAC_EN_FC_AN BIT(11)
388 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
389 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
390 #define MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG BIT(15)
391 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
392 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
393 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
394 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
395 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
396 #define MVPP2_GMAC_CTRL_4_REG 0x90
397 #define MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK BIT(0)
398 #define MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK BIT(5)
399 #define MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK BIT(6)
400 #define MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK BIT(7)
403 * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
404 * relative to port->base.
407 /* Port Mac Control0 */
408 #define MVPP22_XLG_CTRL0_REG 0x100
409 #define MVPP22_XLG_PORT_EN BIT(0)
410 #define MVPP22_XLG_MAC_RESETN BIT(1)
411 #define MVPP22_XLG_RX_FC_EN BIT(7)
412 #define MVPP22_XLG_MIBCNT_DIS BIT(13)
413 /* Port Mac Control1 */
414 #define MVPP22_XLG_CTRL1_REG 0x104
415 #define MVPP22_XLG_MAX_RX_SIZE_OFFS 0
416 #define MVPP22_XLG_MAX_RX_SIZE_MASK 0x1fff
417 /* Port Interrupt Mask */
418 #define MVPP22_XLG_INTERRUPT_MASK_REG 0x118
419 #define MVPP22_XLG_INTERRUPT_LINK_CHANGE BIT(1)
420 /* Port Mac Control3 */
421 #define MVPP22_XLG_CTRL3_REG 0x11c
422 #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
423 #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
424 #define MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC (1 << 13)
425 /* Port Mac Control4 */
426 #define MVPP22_XLG_CTRL4_REG 0x184
427 #define MVPP22_XLG_FORWARD_802_3X_FC_EN BIT(5)
428 #define MVPP22_XLG_FORWARD_PFC_EN BIT(6)
429 #define MVPP22_XLG_MODE_DMA_1G BIT(12)
430 #define MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK BIT(14)
434 /* Global Configuration 0 */
435 #define MVPP22_XPCS_GLOBAL_CFG_0_REG 0x0
436 #define MVPP22_XPCS_PCSRESET BIT(0)
437 #define MVPP22_XPCS_PCSMODE_OFFS 3
438 #define MVPP22_XPCS_PCSMODE_MASK (0x3 << \
439 MVPP22_XPCS_PCSMODE_OFFS)
440 #define MVPP22_XPCS_LANEACTIVE_OFFS 5
441 #define MVPP22_XPCS_LANEACTIVE_MASK (0x3 << \
442 MVPP22_XPCS_LANEACTIVE_OFFS)
446 #define PCS40G_COMMON_CONTROL 0x14
447 #define FORWARD_ERROR_CORRECTION_MASK BIT(10)
449 #define PCS_CLOCK_RESET 0x14c
450 #define TX_SD_CLK_RESET_MASK BIT(0)
451 #define RX_SD_CLK_RESET_MASK BIT(1)
452 #define MAC_CLK_RESET_MASK BIT(2)
453 #define CLK_DIVISION_RATIO_OFFS 4
454 #define CLK_DIVISION_RATIO_MASK (0x7 << CLK_DIVISION_RATIO_OFFS)
455 #define CLK_DIV_PHASE_SET_MASK BIT(11)
457 /* System Soft Reset 1 */
458 #define GOP_SOFT_RESET_1_REG 0x108
459 #define NETC_GOP_SOFT_RESET_OFFS 6
460 #define NETC_GOP_SOFT_RESET_MASK (0x1 << \
461 NETC_GOP_SOFT_RESET_OFFS)
463 /* Ports Control 0 */
464 #define NETCOMP_PORTS_CONTROL_0_REG 0x110
465 #define NETC_BUS_WIDTH_SELECT_OFFS 1
466 #define NETC_BUS_WIDTH_SELECT_MASK (0x1 << \
467 NETC_BUS_WIDTH_SELECT_OFFS)
468 #define NETC_GIG_RX_DATA_SAMPLE_OFFS 29
469 #define NETC_GIG_RX_DATA_SAMPLE_MASK (0x1 << \
470 NETC_GIG_RX_DATA_SAMPLE_OFFS)
471 #define NETC_CLK_DIV_PHASE_OFFS 31
472 #define NETC_CLK_DIV_PHASE_MASK (0x1 << NETC_CLK_DIV_PHASE_OFFS)
473 /* Ports Control 1 */
474 #define NETCOMP_PORTS_CONTROL_1_REG 0x114
475 #define NETC_PORTS_ACTIVE_OFFSET(p) (0 + p)
476 #define NETC_PORTS_ACTIVE_MASK(p) (0x1 << \
477 NETC_PORTS_ACTIVE_OFFSET(p))
478 #define NETC_PORT_GIG_RF_RESET_OFFS(p) (28 + p)
479 #define NETC_PORT_GIG_RF_RESET_MASK(p) (0x1 << \
480 NETC_PORT_GIG_RF_RESET_OFFS(p))
481 #define NETCOMP_CONTROL_0_REG 0x120
482 #define NETC_GBE_PORT0_SGMII_MODE_OFFS 0
483 #define NETC_GBE_PORT0_SGMII_MODE_MASK (0x1 << \
484 NETC_GBE_PORT0_SGMII_MODE_OFFS)
485 #define NETC_GBE_PORT1_SGMII_MODE_OFFS 1
486 #define NETC_GBE_PORT1_SGMII_MODE_MASK (0x1 << \
487 NETC_GBE_PORT1_SGMII_MODE_OFFS)
488 #define NETC_GBE_PORT1_MII_MODE_OFFS 2
489 #define NETC_GBE_PORT1_MII_MODE_MASK (0x1 << \
490 NETC_GBE_PORT1_MII_MODE_OFFS)
492 #define MVPP22_SMI_MISC_CFG_REG (MVPP22_SMI + 0x04)
493 #define MVPP22_SMI_POLLING_EN BIT(10)
495 #define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \
498 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
500 /* Descriptor ring Macros */
501 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
502 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
504 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
505 #define MVPP21_SMI 0x0054
506 /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
507 #define MVPP22_SMI 0x1200
508 #define MVPP2_PHY_REG_MASK 0x1f
509 /* SMI register fields */
510 #define MVPP2_SMI_DATA_OFFS 0 /* Data */
511 #define MVPP2_SMI_DATA_MASK (0xffff << MVPP2_SMI_DATA_OFFS)
512 #define MVPP2_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
513 #define MVPP2_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
514 #define MVPP2_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
515 #define MVPP2_SMI_OPCODE_READ (1 << MVPP2_SMI_OPCODE_OFFS)
516 #define MVPP2_SMI_READ_VALID (1 << 27) /* Read Valid */
517 #define MVPP2_SMI_BUSY (1 << 28) /* Busy */
519 #define MVPP2_PHY_ADDR_MASK 0x1f
520 #define MVPP2_PHY_REG_MASK 0x1f
522 /* Additional PPv2.2 offsets */
523 #define MVPP22_MPCS 0x007000
524 #define MVPP22_XPCS 0x007400
525 #define MVPP22_PORT_BASE 0x007e00
526 #define MVPP22_PORT_OFFSET 0x001000
527 #define MVPP22_RFU1 0x318000
529 /* Maximum number of ports */
530 #define MVPP22_GOP_MAC_NUM 4
532 /* Sets the field located at the specified in data */
533 #define MVPP2_RGMII_TX_FIFO_MIN_TH 0x41
534 #define MVPP2_SGMII_TX_FIFO_MIN_TH 0x5
535 #define MVPP2_SGMII2_5_TX_FIFO_MIN_TH 0xb
538 enum mv_netc_topology {
539 MV_NETC_GE_MAC2_SGMII = BIT(0),
540 MV_NETC_GE_MAC3_SGMII = BIT(1),
541 MV_NETC_GE_MAC3_RGMII = BIT(2),
546 MV_NETC_SECOND_PHASE,
549 enum mv_netc_sgmii_xmi_mode {
554 enum mv_netc_mii_mode {
564 /* Various constants */
567 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
568 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
569 #define MVPP2_RX_COAL_PKTS 32
570 #define MVPP2_RX_COAL_USEC 100
572 /* The two bytes Marvell header. Either contains a special value used
573 * by Marvell switches when a specific hardware mode is enabled (not
574 * supported by this driver) or is filled automatically by zeroes on
575 * the RX side. Those two bytes being at the front of the Ethernet
576 * header, they allow to have the IP header aligned on a 4 bytes
577 * boundary automatically: the hardware skips those two bytes on its
580 #define MVPP2_MH_SIZE 2
581 #define MVPP2_ETH_TYPE_LEN 2
582 #define MVPP2_PPPOE_HDR_SIZE 8
583 #define MVPP2_VLAN_TAG_LEN 4
585 /* Lbtd 802.3 type */
586 #define MVPP2_IP_LBDT_TYPE 0xfffa
588 #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
589 #define MVPP2_TX_CSUM_MAX_SIZE 9800
591 /* Timeout constants */
592 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
593 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
595 #define MVPP2_TX_MTU_MAX 0x7ffff
597 /* Maximum number of T-CONTs of PON port */
598 #define MVPP2_MAX_TCONT 16
600 /* Maximum number of supported ports */
601 #define MVPP2_MAX_PORTS 4
603 /* Maximum number of TXQs used by single port */
604 #define MVPP2_MAX_TXQ 8
606 /* Default number of TXQs in use */
607 #define MVPP2_DEFAULT_TXQ 1
609 /* Dfault number of RXQs in use */
610 #define MVPP2_DEFAULT_RXQ 1
611 #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
613 /* Max number of Rx descriptors */
614 #define MVPP2_MAX_RXD 16
616 /* Max number of Tx descriptors */
617 #define MVPP2_MAX_TXD 16
619 /* Amount of Tx descriptors that can be reserved at once by CPU */
620 #define MVPP2_CPU_DESC_CHUNK 64
622 /* Max number of Tx descriptors in each aggregated queue */
623 #define MVPP2_AGGR_TXQ_SIZE 256
625 /* Descriptor aligned size */
626 #define MVPP2_DESC_ALIGNED_SIZE 32
628 /* Descriptor alignment mask */
629 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
631 /* RX FIFO constants */
632 #define MVPP21_RX_FIFO_PORT_DATA_SIZE 0x2000
633 #define MVPP21_RX_FIFO_PORT_ATTR_SIZE 0x80
634 #define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE 0x8000
635 #define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE 0x2000
636 #define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE 0x1000
637 #define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE 0x200
638 #define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE 0x80
639 #define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE 0x40
640 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
642 /* TX general registers */
643 #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2))
644 #define MVPP22_TX_FIFO_SIZE_MASK 0xf
646 /* TX FIFO constants */
647 #define MVPP2_TX_FIFO_DATA_SIZE_10KB 0xa
648 #define MVPP2_TX_FIFO_DATA_SIZE_3KB 0x3
650 /* RX buffer constants */
651 #define MVPP2_SKB_SHINFO_SIZE \
654 #define MVPP2_RX_PKT_SIZE(mtu) \
655 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
656 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
658 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
659 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
660 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
661 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
663 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
665 /* IPv6 max L3 address size */
666 #define MVPP2_MAX_L3_ADDR_SIZE 16
669 #define MVPP2_F_LOOPBACK BIT(0)
671 /* Marvell tag types */
672 enum mvpp2_tag_type {
673 MVPP2_TAG_TYPE_NONE = 0,
674 MVPP2_TAG_TYPE_MH = 1,
675 MVPP2_TAG_TYPE_DSA = 2,
676 MVPP2_TAG_TYPE_EDSA = 3,
677 MVPP2_TAG_TYPE_VLAN = 4,
678 MVPP2_TAG_TYPE_LAST = 5
681 /* Parser constants */
682 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
683 #define MVPP2_PRS_TCAM_WORDS 6
684 #define MVPP2_PRS_SRAM_WORDS 4
685 #define MVPP2_PRS_FLOW_ID_SIZE 64
686 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
687 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
688 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
689 #define MVPP2_PRS_IPV4_HEAD 0x40
690 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
691 #define MVPP2_PRS_IPV4_MC 0xe0
692 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
693 #define MVPP2_PRS_IPV4_BC_MASK 0xff
694 #define MVPP2_PRS_IPV4_IHL 0x5
695 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
696 #define MVPP2_PRS_IPV6_MC 0xff
697 #define MVPP2_PRS_IPV6_MC_MASK 0xff
698 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
699 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
700 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
701 #define MVPP2_PRS_DBL_VLANS_MAX 100
704 * - lookup ID - 4 bits
706 * - additional information - 1 byte
707 * - header data - 8 bytes
708 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
710 #define MVPP2_PRS_AI_BITS 8
711 #define MVPP2_PRS_PORT_MASK 0xff
712 #define MVPP2_PRS_LU_MASK 0xf
713 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
714 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
715 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
716 (((offs) * 2) - ((offs) % 2) + 2)
717 #define MVPP2_PRS_TCAM_AI_BYTE 16
718 #define MVPP2_PRS_TCAM_PORT_BYTE 17
719 #define MVPP2_PRS_TCAM_LU_BYTE 20
720 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
721 #define MVPP2_PRS_TCAM_INV_WORD 5
722 /* Tcam entries ID */
723 #define MVPP2_PE_DROP_ALL 0
724 #define MVPP2_PE_FIRST_FREE_TID 1
725 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
726 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
727 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
728 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
729 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
730 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
731 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
732 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
733 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
734 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
735 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
736 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
737 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
738 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
739 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
740 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
741 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
742 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
743 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
744 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
745 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
746 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
747 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
748 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
749 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
752 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
754 #define MVPP2_PRS_SRAM_RI_OFFS 0
755 #define MVPP2_PRS_SRAM_RI_WORD 0
756 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
757 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
758 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
759 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
760 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
761 #define MVPP2_PRS_SRAM_UDF_OFFS 73
762 #define MVPP2_PRS_SRAM_UDF_BITS 8
763 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
764 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
765 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
766 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
767 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
768 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
769 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
770 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
771 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
772 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
773 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
774 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
775 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
776 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
777 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
778 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
779 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
780 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
781 #define MVPP2_PRS_SRAM_AI_OFFS 90
782 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
783 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
784 #define MVPP2_PRS_SRAM_AI_MASK 0xff
785 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
786 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
787 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
788 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
790 /* Sram result info bits assignment */
791 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
792 #define MVPP2_PRS_RI_DSA_MASK 0x2
793 #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
794 #define MVPP2_PRS_RI_VLAN_NONE 0x0
795 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
796 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
797 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
798 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
799 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
800 #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
801 #define MVPP2_PRS_RI_L2_UCAST 0x0
802 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
803 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
804 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
805 #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
806 #define MVPP2_PRS_RI_L3_UN 0x0
807 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
808 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
809 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
810 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
811 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
812 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
813 #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
814 #define MVPP2_PRS_RI_L3_UCAST 0x0
815 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
816 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
817 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
818 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
819 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
820 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
821 #define MVPP2_PRS_RI_L4_TCP BIT(22)
822 #define MVPP2_PRS_RI_L4_UDP BIT(23)
823 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
824 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
825 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
826 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
828 /* Sram additional info bits assignment */
829 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
830 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
831 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
832 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
833 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
834 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
835 #define MVPP2_PRS_SINGLE_VLAN_AI 0
836 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
839 #define MVPP2_PRS_TAGGED true
840 #define MVPP2_PRS_UNTAGGED false
841 #define MVPP2_PRS_EDSA true
842 #define MVPP2_PRS_DSA false
844 /* MAC entries, shadow udf */
846 MVPP2_PRS_UDF_MAC_DEF,
847 MVPP2_PRS_UDF_MAC_RANGE,
848 MVPP2_PRS_UDF_L2_DEF,
849 MVPP2_PRS_UDF_L2_DEF_COPY,
850 MVPP2_PRS_UDF_L2_USER,
854 enum mvpp2_prs_lookup {
868 enum mvpp2_prs_l3_cast {
869 MVPP2_PRS_L3_UNI_CAST,
870 MVPP2_PRS_L3_MULTI_CAST,
871 MVPP2_PRS_L3_BROAD_CAST
874 /* Classifier constants */
875 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
876 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
877 #define MVPP2_CLS_LKP_TBL_SIZE 64
880 #define MVPP2_BM_POOLS_NUM 1
881 #define MVPP2_BM_LONG_BUF_NUM 16
882 #define MVPP2_BM_SHORT_BUF_NUM 16
883 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
884 #define MVPP2_BM_POOL_PTR_ALIGN 128
885 #define MVPP2_BM_SWF_LONG_POOL(port) 0
887 /* BM cookie (32 bits) definition */
888 #define MVPP2_BM_COOKIE_POOL_OFFS 8
889 #define MVPP2_BM_COOKIE_CPU_OFFS 24
891 /* BM short pool packet size
892 * These value assure that for SWF the total number
893 * of bytes allocated for each buffer will be 512
895 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
905 /* Shared Packet Processor resources */
907 /* Shared registers' base addresses */
909 void __iomem *lms_base;
910 void __iomem *iface_base;
911 void __iomem *mdio_base;
913 void __iomem *mpcs_base;
914 void __iomem *xpcs_base;
915 void __iomem *rfu1_base;
919 /* List of pointers to port structures */
920 struct mvpp2_port **port_list;
922 /* Aggregated TXQs */
923 struct mvpp2_tx_queue *aggr_txqs;
926 struct mvpp2_bm_pool *bm_pools;
928 /* PRS shadow table */
929 struct mvpp2_prs_shadow *prs_shadow;
930 /* PRS auxiliary table for double vlan entries control */
931 bool *prs_double_vlans;
937 enum { MVPP21, MVPP22 } hw_version;
939 /* Maximum number of RXQs per port */
940 unsigned int max_port_rxqs;
947 struct mvpp2_pcpu_stats {
957 /* Index of the port from the "group of ports" complex point
966 /* Per-port registers' base address */
969 struct mvpp2_rx_queue **rxqs;
970 struct mvpp2_tx_queue **txqs;
974 u32 pending_cause_rx;
976 /* Per-CPU port control */
977 struct mvpp2_port_pcpu __percpu *pcpu;
984 struct mvpp2_pcpu_stats __percpu *stats;
986 struct phy_device *phy_dev;
987 phy_interface_t phy_interface;
990 #ifdef CONFIG_DM_GPIO
991 struct gpio_desc phy_reset_gpio;
992 struct gpio_desc phy_tx_disable_gpio;
999 unsigned int phy_speed; /* SGMII 1Gbps vs 2.5Gbps */
1001 struct mvpp2_bm_pool *pool_long;
1002 struct mvpp2_bm_pool *pool_short;
1004 /* Index of first port's physical RXQ */
1007 u8 dev_addr[ETH_ALEN];
1010 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
1011 * layout of the transmit and reception DMA descriptors, and their
1012 * layout is therefore defined by the hardware design
1015 #define MVPP2_TXD_L3_OFF_SHIFT 0
1016 #define MVPP2_TXD_IP_HLEN_SHIFT 8
1017 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
1018 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
1019 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
1020 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
1021 #define MVPP2_TXD_L4_UDP BIT(24)
1022 #define MVPP2_TXD_L3_IP6 BIT(26)
1023 #define MVPP2_TXD_L_DESC BIT(28)
1024 #define MVPP2_TXD_F_DESC BIT(29)
1026 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
1027 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
1028 #define MVPP2_RXD_ERR_CRC 0x0
1029 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
1030 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
1031 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
1032 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
1033 #define MVPP2_RXD_HWF_SYNC BIT(21)
1034 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
1035 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
1036 #define MVPP2_RXD_L4_TCP BIT(25)
1037 #define MVPP2_RXD_L4_UDP BIT(26)
1038 #define MVPP2_RXD_L3_IP4 BIT(28)
1039 #define MVPP2_RXD_L3_IP6 BIT(30)
1040 #define MVPP2_RXD_BUF_HDR BIT(31)
1042 /* HW TX descriptor for PPv2.1 */
1043 struct mvpp21_tx_desc {
1044 u32 command; /* Options used by HW for packet transmitting.*/
1045 u8 packet_offset; /* the offset from the buffer beginning */
1046 u8 phys_txq; /* destination queue ID */
1047 u16 data_size; /* data size of transmitted packet in bytes */
1048 u32 buf_dma_addr; /* physical addr of transmitted buffer */
1049 u32 buf_cookie; /* cookie for access to TX buffer in tx path */
1050 u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
1051 u32 reserved2; /* reserved (for future use) */
1054 /* HW RX descriptor for PPv2.1 */
1055 struct mvpp21_rx_desc {
1056 u32 status; /* info about received packet */
1057 u16 reserved1; /* parser_info (for future use, PnC) */
1058 u16 data_size; /* size of received packet in bytes */
1059 u32 buf_dma_addr; /* physical address of the buffer */
1060 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
1061 u16 reserved2; /* gem_port_id (for future use, PON) */
1062 u16 reserved3; /* csum_l4 (for future use, PnC) */
1063 u8 reserved4; /* bm_qset (for future use, BM) */
1065 u16 reserved6; /* classify_info (for future use, PnC) */
1066 u32 reserved7; /* flow_id (for future use, PnC) */
1070 /* HW TX descriptor for PPv2.2 */
1071 struct mvpp22_tx_desc {
1077 u64 buf_dma_addr_ptp;
1078 u64 buf_cookie_misc;
1081 /* HW RX descriptor for PPv2.2 */
1082 struct mvpp22_rx_desc {
1088 u64 buf_dma_addr_key_hash;
1089 u64 buf_cookie_misc;
1092 /* Opaque type used by the driver to manipulate the HW TX and RX
1095 struct mvpp2_tx_desc {
1097 struct mvpp21_tx_desc pp21;
1098 struct mvpp22_tx_desc pp22;
1102 struct mvpp2_rx_desc {
1104 struct mvpp21_rx_desc pp21;
1105 struct mvpp22_rx_desc pp22;
1109 /* Per-CPU Tx queue control */
1110 struct mvpp2_txq_pcpu {
1113 /* Number of Tx DMA descriptors in the descriptor ring */
1116 /* Number of currently used Tx DMA descriptor in the
1121 /* Number of Tx DMA descriptors reserved for each CPU */
1124 /* Index of last TX DMA descriptor that was inserted */
1127 /* Index of the TX DMA descriptor to be cleaned up */
1131 struct mvpp2_tx_queue {
1132 /* Physical number of this Tx queue */
1135 /* Logical number of this Tx queue */
1138 /* Number of Tx DMA descriptors in the descriptor ring */
1141 /* Number of currently used Tx DMA descriptor in the descriptor ring */
1144 /* Per-CPU control of physical Tx queues */
1145 struct mvpp2_txq_pcpu __percpu *pcpu;
1149 /* Virtual address of thex Tx DMA descriptors array */
1150 struct mvpp2_tx_desc *descs;
1152 /* DMA address of the Tx DMA descriptors array */
1153 dma_addr_t descs_dma;
1155 /* Index of the last Tx DMA descriptor */
1158 /* Index of the next Tx DMA descriptor to process */
1159 int next_desc_to_proc;
1162 struct mvpp2_rx_queue {
1163 /* RX queue number, in the range 0-31 for physical RXQs */
1166 /* Num of rx descriptors in the rx descriptor ring */
1172 /* Virtual address of the RX DMA descriptors array */
1173 struct mvpp2_rx_desc *descs;
1175 /* DMA address of the RX DMA descriptors array */
1176 dma_addr_t descs_dma;
1178 /* Index of the last RX DMA descriptor */
1181 /* Index of the next RX DMA descriptor to process */
1182 int next_desc_to_proc;
1184 /* ID of port to which physical RXQ is mapped */
1187 /* Port's logic RXQ number to which physical RXQ is mapped */
1191 union mvpp2_prs_tcam_entry {
1192 u32 word[MVPP2_PRS_TCAM_WORDS];
1193 u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
1196 union mvpp2_prs_sram_entry {
1197 u32 word[MVPP2_PRS_SRAM_WORDS];
1198 u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
1201 struct mvpp2_prs_entry {
1203 union mvpp2_prs_tcam_entry tcam;
1204 union mvpp2_prs_sram_entry sram;
1207 struct mvpp2_prs_shadow {
1214 /* User defined offset */
1222 struct mvpp2_cls_flow_entry {
1224 u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
1227 struct mvpp2_cls_lookup_entry {
1233 struct mvpp2_bm_pool {
1234 /* Pool number in the range 0-7 */
1236 enum mvpp2_bm_type type;
1238 /* Buffer Pointers Pool External (BPPE) size */
1240 /* Number of buffers for this pool */
1242 /* Pool buffer size */
1247 /* BPPE virtual base address */
1248 unsigned long *virt_addr;
1249 /* BPPE DMA base address */
1250 dma_addr_t dma_addr;
1252 /* Ports using BM pool */
1256 /* Static declaractions */
1258 /* Number of RXQs used by single port */
1259 static int rxq_number = MVPP2_DEFAULT_RXQ;
1260 /* Number of TXQs used by single port */
1261 static int txq_number = MVPP2_DEFAULT_TXQ;
1265 #define MVPP2_DRIVER_NAME "mvpp2"
1266 #define MVPP2_DRIVER_VERSION "1.0"
1269 * U-Boot internal data, mostly uncached buffers for descriptors and data
1271 struct buffer_location {
1272 struct mvpp2_tx_desc *aggr_tx_descs;
1273 struct mvpp2_tx_desc *tx_descs;
1274 struct mvpp2_rx_desc *rx_descs;
1275 unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
1276 unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
1281 * All 4 interfaces use the same global buffer, since only one interface
1282 * can be enabled at once
1284 static struct buffer_location buffer_loc;
1287 * Page table entries are set to 1MB, or multiples of 1MB
1288 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
1290 #define BD_SPACE (1 << 20)
1292 /* Utility/helper methods */
1294 static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
1296 writel(data, priv->base + offset);
1299 static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
1301 return readl(priv->base + offset);
1304 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
1305 struct mvpp2_tx_desc *tx_desc,
1306 dma_addr_t dma_addr)
1308 if (port->priv->hw_version == MVPP21) {
1309 tx_desc->pp21.buf_dma_addr = dma_addr;
1311 u64 val = (u64)dma_addr;
1313 tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
1314 tx_desc->pp22.buf_dma_addr_ptp |= val;
1318 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
1319 struct mvpp2_tx_desc *tx_desc,
1322 if (port->priv->hw_version == MVPP21)
1323 tx_desc->pp21.data_size = size;
1325 tx_desc->pp22.data_size = size;
1328 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
1329 struct mvpp2_tx_desc *tx_desc,
1332 if (port->priv->hw_version == MVPP21)
1333 tx_desc->pp21.phys_txq = txq;
1335 tx_desc->pp22.phys_txq = txq;
1338 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
1339 struct mvpp2_tx_desc *tx_desc,
1340 unsigned int command)
1342 if (port->priv->hw_version == MVPP21)
1343 tx_desc->pp21.command = command;
1345 tx_desc->pp22.command = command;
1348 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
1349 struct mvpp2_tx_desc *tx_desc,
1350 unsigned int offset)
1352 if (port->priv->hw_version == MVPP21)
1353 tx_desc->pp21.packet_offset = offset;
1355 tx_desc->pp22.packet_offset = offset;
1358 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
1359 struct mvpp2_rx_desc *rx_desc)
1361 if (port->priv->hw_version == MVPP21)
1362 return rx_desc->pp21.buf_dma_addr;
1364 return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
1367 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
1368 struct mvpp2_rx_desc *rx_desc)
1370 if (port->priv->hw_version == MVPP21)
1371 return rx_desc->pp21.buf_cookie;
1373 return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
1376 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
1377 struct mvpp2_rx_desc *rx_desc)
1379 if (port->priv->hw_version == MVPP21)
1380 return rx_desc->pp21.data_size;
1382 return rx_desc->pp22.data_size;
1385 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
1386 struct mvpp2_rx_desc *rx_desc)
1388 if (port->priv->hw_version == MVPP21)
1389 return rx_desc->pp21.status;
1391 return rx_desc->pp22.status;
1394 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
1396 txq_pcpu->txq_get_index++;
1397 if (txq_pcpu->txq_get_index == txq_pcpu->size)
1398 txq_pcpu->txq_get_index = 0;
1401 /* Get number of physical egress port */
1402 static inline int mvpp2_egress_port(struct mvpp2_port *port)
1404 return MVPP2_MAX_TCONT + port->id;
1407 /* Get number of physical TXQ */
1408 static inline int mvpp2_txq_phys(int port, int txq)
1410 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
1413 /* Parser configuration routines */
1415 /* Update parser tcam and sram hw entries */
1416 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1420 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1423 /* Clear entry invalidation bit */
1424 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1426 /* Write tcam index - indirect access */
1427 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1428 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1429 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1431 /* Write sram index - indirect access */
1432 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1433 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1434 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1439 /* Read tcam entry from hw */
1440 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1444 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1447 /* Write tcam index - indirect access */
1448 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1450 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
1451 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
1452 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
1453 return MVPP2_PRS_TCAM_ENTRY_INVALID;
1455 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1456 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
1458 /* Write sram index - indirect access */
1459 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1460 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1461 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
1466 /* Invalidate tcam hw entry */
1467 static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
1469 /* Write index - indirect access */
1470 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1471 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
1472 MVPP2_PRS_TCAM_INV_MASK);
1475 /* Enable shadow table entry and set its lookup ID */
1476 static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
1478 priv->prs_shadow[index].valid = true;
1479 priv->prs_shadow[index].lu = lu;
1482 /* Update ri fields in shadow table entry */
1483 static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
1484 unsigned int ri, unsigned int ri_mask)
1486 priv->prs_shadow[index].ri_mask = ri_mask;
1487 priv->prs_shadow[index].ri = ri;
1490 /* Update lookup field in tcam sw entry */
1491 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
1493 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
1495 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
1496 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
1499 /* Update mask for single port in tcam sw entry */
1500 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
1501 unsigned int port, bool add)
1503 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1506 pe->tcam.byte[enable_off] &= ~(1 << port);
1508 pe->tcam.byte[enable_off] |= 1 << port;
1511 /* Update port map in tcam sw entry */
1512 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
1515 unsigned char port_mask = MVPP2_PRS_PORT_MASK;
1516 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1518 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
1519 pe->tcam.byte[enable_off] &= ~port_mask;
1520 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
1523 /* Obtain port map from tcam sw entry */
1524 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
1526 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1528 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
1531 /* Set byte of data and its enable bits in tcam sw entry */
1532 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
1533 unsigned int offs, unsigned char byte,
1534 unsigned char enable)
1536 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
1537 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
1540 /* Get byte of data and its enable bits from tcam sw entry */
1541 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
1542 unsigned int offs, unsigned char *byte,
1543 unsigned char *enable)
1545 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
1546 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
1549 /* Set ethertype in tcam sw entry */
1550 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
1551 unsigned short ethertype)
1553 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
1554 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
1557 /* Set bits in sram sw entry */
1558 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
1561 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
1564 /* Clear bits in sram sw entry */
1565 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
1568 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
1571 /* Update ri bits in sram sw entry */
1572 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
1573 unsigned int bits, unsigned int mask)
1577 for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
1578 int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
1580 if (!(mask & BIT(i)))
1584 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
1586 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
1588 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
1592 /* Update ai bits in sram sw entry */
1593 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
1594 unsigned int bits, unsigned int mask)
1597 int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
1599 for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
1601 if (!(mask & BIT(i)))
1605 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
1607 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
1609 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
1613 /* Read ai bits from sram sw entry */
1614 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
1617 int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
1618 int ai_en_off = ai_off + 1;
1619 int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
1621 bits = (pe->sram.byte[ai_off] >> ai_shift) |
1622 (pe->sram.byte[ai_en_off] << (8 - ai_shift));
1627 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1630 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
1633 int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
1635 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
1636 MVPP2_PRS_SRAM_NEXT_LU_MASK);
1637 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
1640 /* In the sram sw entry set sign and value of the next lookup offset
1641 * and the offset value generated to the classifier
1643 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
1648 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1651 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1655 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
1656 (unsigned char)shift;
1658 /* Reset and set operation */
1659 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
1660 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
1661 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
1663 /* Set base offset as current */
1664 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1667 /* In the sram sw entry set sign and value of the user defined offset
1668 * generated to the classifier
1670 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
1671 unsigned int type, int offset,
1676 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1677 offset = 0 - offset;
1679 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1683 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
1684 MVPP2_PRS_SRAM_UDF_MASK);
1685 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
1686 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1687 MVPP2_PRS_SRAM_UDF_BITS)] &=
1688 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1689 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1690 MVPP2_PRS_SRAM_UDF_BITS)] |=
1691 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1693 /* Set offset type */
1694 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
1695 MVPP2_PRS_SRAM_UDF_TYPE_MASK);
1696 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
1698 /* Set offset operation */
1699 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
1700 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
1701 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
1703 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1704 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
1705 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
1706 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1708 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1709 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
1710 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1712 /* Set base offset as current */
1713 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1716 /* Find parser flow entry */
1717 static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
1719 struct mvpp2_prs_entry *pe;
1722 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1725 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
1727 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1728 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
1731 if (!priv->prs_shadow[tid].valid ||
1732 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
1736 mvpp2_prs_hw_read(priv, pe);
1737 bits = mvpp2_prs_sram_ai_get(pe);
1739 /* Sram store classification lookup ID in AI bits [5:0] */
1740 if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
1748 /* Return first free tcam index, seeking from start to end */
1749 static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
1757 if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
1758 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
1760 for (tid = start; tid <= end; tid++) {
1761 if (!priv->prs_shadow[tid].valid)
1768 /* Enable/disable dropping all mac da's */
1769 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
1771 struct mvpp2_prs_entry pe;
1773 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
1774 /* Entry exist - update port only */
1775 pe.index = MVPP2_PE_DROP_ALL;
1776 mvpp2_prs_hw_read(priv, &pe);
1778 /* Entry doesn't exist - create new */
1779 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1780 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1781 pe.index = MVPP2_PE_DROP_ALL;
1783 /* Non-promiscuous mode for all ports - DROP unknown packets */
1784 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1785 MVPP2_PRS_RI_DROP_MASK);
1787 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1788 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1790 /* Update shadow table */
1791 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1793 /* Mask all ports */
1794 mvpp2_prs_tcam_port_map_set(&pe, 0);
1797 /* Update port mask */
1798 mvpp2_prs_tcam_port_set(&pe, port, add);
1800 mvpp2_prs_hw_write(priv, &pe);
1803 /* Set port to promiscuous mode */
1804 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
1806 struct mvpp2_prs_entry pe;
1808 /* Promiscuous mode - Accept unknown packets */
1810 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
1811 /* Entry exist - update port only */
1812 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1813 mvpp2_prs_hw_read(priv, &pe);
1815 /* Entry doesn't exist - create new */
1816 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1817 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1818 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1820 /* Continue - set next lookup */
1821 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1823 /* Set result info bits */
1824 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
1825 MVPP2_PRS_RI_L2_CAST_MASK);
1827 /* Shift to ethertype */
1828 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1829 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1831 /* Mask all ports */
1832 mvpp2_prs_tcam_port_map_set(&pe, 0);
1834 /* Update shadow table */
1835 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1838 /* Update port mask */
1839 mvpp2_prs_tcam_port_set(&pe, port, add);
1841 mvpp2_prs_hw_write(priv, &pe);
1844 /* Accept multicast */
1845 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
1848 struct mvpp2_prs_entry pe;
1849 unsigned char da_mc;
1851 /* Ethernet multicast address first byte is
1852 * 0x01 for IPv4 and 0x33 for IPv6
1854 da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
1856 if (priv->prs_shadow[index].valid) {
1857 /* Entry exist - update port only */
1859 mvpp2_prs_hw_read(priv, &pe);
1861 /* Entry doesn't exist - create new */
1862 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1863 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1866 /* Continue - set next lookup */
1867 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1869 /* Set result info bits */
1870 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
1871 MVPP2_PRS_RI_L2_CAST_MASK);
1873 /* Update tcam entry data first byte */
1874 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
1876 /* Shift to ethertype */
1877 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1878 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1880 /* Mask all ports */
1881 mvpp2_prs_tcam_port_map_set(&pe, 0);
1883 /* Update shadow table */
1884 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1887 /* Update port mask */
1888 mvpp2_prs_tcam_port_set(&pe, port, add);
1890 mvpp2_prs_hw_write(priv, &pe);
1893 /* Parser per-port initialization */
1894 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
1895 int lu_max, int offset)
1900 val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
1901 val &= ~MVPP2_PRS_PORT_LU_MASK(port);
1902 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
1903 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
1905 /* Set maximum number of loops for packet received from port */
1906 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
1907 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
1908 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
1909 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
1911 /* Set initial offset for packet header extraction for the first
1914 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
1915 val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
1916 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
1917 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
1920 /* Default flow entries initialization for all ports */
1921 static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
1923 struct mvpp2_prs_entry pe;
1926 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
1927 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1928 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1929 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
1931 /* Mask all ports */
1932 mvpp2_prs_tcam_port_map_set(&pe, 0);
1935 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
1936 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
1938 /* Update shadow table and hw entry */
1939 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
1940 mvpp2_prs_hw_write(priv, &pe);
1944 /* Set default entry for Marvell Header field */
1945 static void mvpp2_prs_mh_init(struct mvpp2 *priv)
1947 struct mvpp2_prs_entry pe;
1949 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1951 pe.index = MVPP2_PE_MH_DEFAULT;
1952 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1953 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1954 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1955 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
1957 /* Unmask all ports */
1958 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1960 /* Update shadow table and hw entry */
1961 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1962 mvpp2_prs_hw_write(priv, &pe);
1965 /* Set default entires (place holder) for promiscuous, non-promiscuous and
1966 * multicast MAC addresses
1968 static void mvpp2_prs_mac_init(struct mvpp2 *priv)
1970 struct mvpp2_prs_entry pe;
1972 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1974 /* Non-promiscuous mode for all ports - DROP unknown packets */
1975 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
1976 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1978 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1979 MVPP2_PRS_RI_DROP_MASK);
1980 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1981 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1983 /* Unmask all ports */
1984 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1986 /* Update shadow table and hw entry */
1987 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1988 mvpp2_prs_hw_write(priv, &pe);
1990 /* place holders only - no ports */
1991 mvpp2_prs_mac_drop_all_set(priv, 0, false);
1992 mvpp2_prs_mac_promisc_set(priv, 0, false);
1993 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
1994 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
1997 /* Match basic ethertypes */
1998 static int mvpp2_prs_etype_init(struct mvpp2 *priv)
2000 struct mvpp2_prs_entry pe;
2003 /* Ethertype: PPPoE */
2004 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2005 MVPP2_PE_LAST_FREE_TID);
2009 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2010 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2013 mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
2015 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
2016 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2017 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
2018 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
2019 MVPP2_PRS_RI_PPPOE_MASK);
2021 /* Update shadow table and hw entry */
2022 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2023 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2024 priv->prs_shadow[pe.index].finish = false;
2025 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
2026 MVPP2_PRS_RI_PPPOE_MASK);
2027 mvpp2_prs_hw_write(priv, &pe);
2029 /* Ethertype: ARP */
2030 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2031 MVPP2_PE_LAST_FREE_TID);
2035 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2036 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2039 mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
2041 /* Generate flow in the next iteration*/
2042 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2043 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2044 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
2045 MVPP2_PRS_RI_L3_PROTO_MASK);
2047 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2049 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2051 /* Update shadow table and hw entry */
2052 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2053 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2054 priv->prs_shadow[pe.index].finish = true;
2055 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
2056 MVPP2_PRS_RI_L3_PROTO_MASK);
2057 mvpp2_prs_hw_write(priv, &pe);
2059 /* Ethertype: LBTD */
2060 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2061 MVPP2_PE_LAST_FREE_TID);
2065 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2066 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2069 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
2071 /* Generate flow in the next iteration*/
2072 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2073 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2074 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2075 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2076 MVPP2_PRS_RI_CPU_CODE_MASK |
2077 MVPP2_PRS_RI_UDF3_MASK);
2079 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2081 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2083 /* Update shadow table and hw entry */
2084 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2085 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2086 priv->prs_shadow[pe.index].finish = true;
2087 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
2088 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
2089 MVPP2_PRS_RI_CPU_CODE_MASK |
2090 MVPP2_PRS_RI_UDF3_MASK);
2091 mvpp2_prs_hw_write(priv, &pe);
2093 /* Ethertype: IPv4 without options */
2094 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2095 MVPP2_PE_LAST_FREE_TID);
2099 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2100 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2103 mvpp2_prs_match_etype(&pe, 0, PROT_IP);
2104 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2105 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
2106 MVPP2_PRS_IPV4_HEAD_MASK |
2107 MVPP2_PRS_IPV4_IHL_MASK);
2109 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
2110 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
2111 MVPP2_PRS_RI_L3_PROTO_MASK);
2112 /* Skip eth_type + 4 bytes of IP header */
2113 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
2114 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2116 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2118 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2120 /* Update shadow table and hw entry */
2121 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2122 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2123 priv->prs_shadow[pe.index].finish = false;
2124 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
2125 MVPP2_PRS_RI_L3_PROTO_MASK);
2126 mvpp2_prs_hw_write(priv, &pe);
2128 /* Ethertype: IPv4 with options */
2129 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2130 MVPP2_PE_LAST_FREE_TID);
2136 /* Clear tcam data before updating */
2137 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
2138 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
2140 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
2141 MVPP2_PRS_IPV4_HEAD,
2142 MVPP2_PRS_IPV4_HEAD_MASK);
2144 /* Clear ri before updating */
2145 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
2146 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
2147 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
2148 MVPP2_PRS_RI_L3_PROTO_MASK);
2150 /* Update shadow table and hw entry */
2151 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2152 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2153 priv->prs_shadow[pe.index].finish = false;
2154 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
2155 MVPP2_PRS_RI_L3_PROTO_MASK);
2156 mvpp2_prs_hw_write(priv, &pe);
2158 /* Ethertype: IPv6 without options */
2159 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2160 MVPP2_PE_LAST_FREE_TID);
2164 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2165 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2168 mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
2170 /* Skip DIP of IPV6 header */
2171 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
2172 MVPP2_MAX_L3_ADDR_SIZE,
2173 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2174 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
2175 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
2176 MVPP2_PRS_RI_L3_PROTO_MASK);
2178 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2180 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2182 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2183 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2184 priv->prs_shadow[pe.index].finish = false;
2185 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
2186 MVPP2_PRS_RI_L3_PROTO_MASK);
2187 mvpp2_prs_hw_write(priv, &pe);
2189 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
2190 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2191 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2192 pe.index = MVPP2_PE_ETH_TYPE_UN;
2194 /* Unmask all ports */
2195 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2197 /* Generate flow in the next iteration*/
2198 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2199 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2200 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
2201 MVPP2_PRS_RI_L3_PROTO_MASK);
2202 /* Set L3 offset even it's unknown L3 */
2203 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2205 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2207 /* Update shadow table and hw entry */
2208 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2209 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2210 priv->prs_shadow[pe.index].finish = true;
2211 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
2212 MVPP2_PRS_RI_L3_PROTO_MASK);
2213 mvpp2_prs_hw_write(priv, &pe);
2218 /* Parser default initialization */
2219 static int mvpp2_prs_default_init(struct udevice *dev,
2224 /* Enable tcam table */
2225 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
2227 /* Clear all tcam and sram entries */
2228 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
2229 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
2230 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
2231 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
2233 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
2234 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
2235 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
2238 /* Invalidate all tcam entries */
2239 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
2240 mvpp2_prs_hw_inv(priv, index);
2242 priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
2243 sizeof(struct mvpp2_prs_shadow),
2245 if (!priv->prs_shadow)
2248 /* Always start from lookup = 0 */
2249 for (index = 0; index < MVPP2_MAX_PORTS; index++)
2250 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
2251 MVPP2_PRS_PORT_LU_MAX, 0);
2253 mvpp2_prs_def_flow_init(priv);
2255 mvpp2_prs_mh_init(priv);
2257 mvpp2_prs_mac_init(priv);
2259 err = mvpp2_prs_etype_init(priv);
2266 /* Compare MAC DA with tcam entry data */
2267 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
2268 const u8 *da, unsigned char *mask)
2270 unsigned char tcam_byte, tcam_mask;
2273 for (index = 0; index < ETH_ALEN; index++) {
2274 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
2275 if (tcam_mask != mask[index])
2278 if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
2285 /* Find tcam entry with matched pair <MAC DA, port> */
2286 static struct mvpp2_prs_entry *
2287 mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
2288 unsigned char *mask, int udf_type)
2290 struct mvpp2_prs_entry *pe;
2293 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2296 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2298 /* Go through the all entires with MVPP2_PRS_LU_MAC */
2299 for (tid = MVPP2_PE_FIRST_FREE_TID;
2300 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
2301 unsigned int entry_pmap;
2303 if (!priv->prs_shadow[tid].valid ||
2304 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
2305 (priv->prs_shadow[tid].udf != udf_type))
2309 mvpp2_prs_hw_read(priv, pe);
2310 entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
2312 if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
2321 /* Update parser's mac da entry */
2322 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
2323 const u8 *da, bool add)
2325 struct mvpp2_prs_entry *pe;
2326 unsigned int pmap, len, ri;
2327 unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2330 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
2331 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
2332 MVPP2_PRS_UDF_MAC_DEF);
2339 /* Create new TCAM entry */
2340 /* Find first range mac entry*/
2341 for (tid = MVPP2_PE_FIRST_FREE_TID;
2342 tid <= MVPP2_PE_LAST_FREE_TID; tid++)
2343 if (priv->prs_shadow[tid].valid &&
2344 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
2345 (priv->prs_shadow[tid].udf ==
2346 MVPP2_PRS_UDF_MAC_RANGE))
2349 /* Go through the all entries from first to last */
2350 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2355 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2358 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2361 /* Mask all ports */
2362 mvpp2_prs_tcam_port_map_set(pe, 0);
2365 /* Update port mask */
2366 mvpp2_prs_tcam_port_set(pe, port, add);
2368 /* Invalidate the entry if no ports are left enabled */
2369 pmap = mvpp2_prs_tcam_port_map_get(pe);
2375 mvpp2_prs_hw_inv(priv, pe->index);
2376 priv->prs_shadow[pe->index].valid = false;
2381 /* Continue - set next lookup */
2382 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
2384 /* Set match on DA */
2387 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
2389 /* Set result info bits */
2390 ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
2392 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2393 MVPP2_PRS_RI_MAC_ME_MASK);
2394 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2395 MVPP2_PRS_RI_MAC_ME_MASK);
2397 /* Shift to ethertype */
2398 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
2399 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2401 /* Update shadow table and hw entry */
2402 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
2403 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
2404 mvpp2_prs_hw_write(priv, pe);
2411 static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
2415 /* Remove old parser entry */
2416 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
2421 /* Add new parser entry */
2422 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
2426 /* Set addr in the device */
2427 memcpy(port->dev_addr, da, ETH_ALEN);
2432 /* Set prs flow for the port */
2433 static int mvpp2_prs_def_flow(struct mvpp2_port *port)
2435 struct mvpp2_prs_entry *pe;
2438 pe = mvpp2_prs_flow_find(port->priv, port->id);
2440 /* Such entry not exist */
2442 /* Go through the all entires from last to first */
2443 tid = mvpp2_prs_tcam_first_free(port->priv,
2444 MVPP2_PE_LAST_FREE_TID,
2445 MVPP2_PE_FIRST_FREE_TID);
2449 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2453 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
2457 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
2458 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2460 /* Update shadow table */
2461 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
2464 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
2465 mvpp2_prs_hw_write(port->priv, pe);
2471 /* Classifier configuration routines */
2473 /* Update classification flow table registers */
2474 static void mvpp2_cls_flow_write(struct mvpp2 *priv,
2475 struct mvpp2_cls_flow_entry *fe)
2477 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
2478 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
2479 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
2480 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
2483 /* Update classification lookup table register */
2484 static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
2485 struct mvpp2_cls_lookup_entry *le)
2489 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
2490 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
2491 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
2494 /* Classifier default initialization */
2495 static void mvpp2_cls_init(struct mvpp2 *priv)
2497 struct mvpp2_cls_lookup_entry le;
2498 struct mvpp2_cls_flow_entry fe;
2501 /* Enable classifier */
2502 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
2504 /* Clear classifier flow table */
2505 memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
2506 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
2508 mvpp2_cls_flow_write(priv, &fe);
2511 /* Clear classifier lookup table */
2513 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
2516 mvpp2_cls_lookup_write(priv, &le);
2519 mvpp2_cls_lookup_write(priv, &le);
2523 static void mvpp2_cls_port_config(struct mvpp2_port *port)
2525 struct mvpp2_cls_lookup_entry le;
2528 /* Set way for the port */
2529 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
2530 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
2531 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
2533 /* Pick the entry to be accessed in lookup ID decoding table
2534 * according to the way and lkpid.
2536 le.lkpid = port->id;
2540 /* Set initial CPU queue for receiving packets */
2541 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
2542 le.data |= port->first_rxq;
2544 /* Disable classification engines */
2545 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
2547 /* Update lookup ID table entry */
2548 mvpp2_cls_lookup_write(port->priv, &le);
2551 /* Set CPU queue number for oversize packets */
2552 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
2556 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
2557 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
2559 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
2560 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
2562 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
2563 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
2564 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
2567 /* Buffer Manager configuration routines */
2570 static int mvpp2_bm_pool_create(struct udevice *dev,
2572 struct mvpp2_bm_pool *bm_pool, int size)
2576 /* Number of buffer pointers must be a multiple of 16, as per
2577 * hardware constraints
2579 if (!IS_ALIGNED(size, 16))
2582 bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
2583 bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
2584 if (!bm_pool->virt_addr)
2587 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
2588 MVPP2_BM_POOL_PTR_ALIGN)) {
2589 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
2590 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
2594 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
2595 lower_32_bits(bm_pool->dma_addr));
2596 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
2598 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2599 val |= MVPP2_BM_START_MASK;
2600 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2602 bm_pool->type = MVPP2_BM_FREE;
2603 bm_pool->size = size;
2604 bm_pool->pkt_size = 0;
2605 bm_pool->buf_num = 0;
2610 /* Set pool buffer size */
2611 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
2612 struct mvpp2_bm_pool *bm_pool,
2617 bm_pool->buf_size = buf_size;
2619 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
2620 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
2623 /* Free all buffers from the pool */
2624 static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
2625 struct mvpp2_bm_pool *bm_pool)
2629 for (i = 0; i < bm_pool->buf_num; i++) {
2630 /* Allocate buffer back from the buffer manager */
2631 mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
2634 bm_pool->buf_num = 0;
2638 static int mvpp2_bm_pool_destroy(struct udevice *dev,
2640 struct mvpp2_bm_pool *bm_pool)
2644 mvpp2_bm_bufs_free(dev, priv, bm_pool);
2645 if (bm_pool->buf_num) {
2646 dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
2650 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2651 val |= MVPP2_BM_STOP_MASK;
2652 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2657 static int mvpp2_bm_pools_init(struct udevice *dev,
2661 struct mvpp2_bm_pool *bm_pool;
2663 /* Create all pools with maximum size */
2664 size = MVPP2_BM_POOL_SIZE_MAX;
2665 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2666 bm_pool = &priv->bm_pools[i];
2668 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
2670 goto err_unroll_pools;
2671 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
2676 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
2677 for (i = i - 1; i >= 0; i--)
2678 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
2682 static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
2686 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2687 /* Mask BM all interrupts */
2688 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
2689 /* Clear BM cause register */
2690 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
2693 /* Allocate and initialize BM pools */
2694 priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
2695 sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
2696 if (!priv->bm_pools)
2699 err = mvpp2_bm_pools_init(dev, priv);
2705 /* Attach long pool to rxq */
2706 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
2707 int lrxq, int long_pool)
2712 /* Get queue physical ID */
2713 prxq = port->rxqs[lrxq]->id;
2715 if (port->priv->hw_version == MVPP21)
2716 mask = MVPP21_RXQ_POOL_LONG_MASK;
2718 mask = MVPP22_RXQ_POOL_LONG_MASK;
2720 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2722 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
2723 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2726 /* Set pool number in a BM cookie */
2727 static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
2731 bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
2732 bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
2737 /* Get pool number from a BM cookie */
2738 static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
2740 return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
2743 /* Release buffer to BM */
2744 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
2745 dma_addr_t buf_dma_addr,
2746 unsigned long buf_phys_addr)
2748 if (port->priv->hw_version == MVPP22) {
2751 if (sizeof(dma_addr_t) == 8)
2752 val |= upper_32_bits(buf_dma_addr) &
2753 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
2755 if (sizeof(phys_addr_t) == 8)
2756 val |= (upper_32_bits(buf_phys_addr)
2757 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
2758 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
2760 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
2763 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
2764 * returned in the "cookie" field of the RX
2765 * descriptor. Instead of storing the virtual address, we
2766 * store the physical address
2768 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
2769 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
2772 /* Refill BM pool */
2773 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
2774 dma_addr_t dma_addr,
2775 phys_addr_t phys_addr)
2777 int pool = mvpp2_bm_cookie_pool_get(bm);
2779 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2782 /* Allocate buffers for the pool */
2783 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
2784 struct mvpp2_bm_pool *bm_pool, int buf_num)
2789 (buf_num + bm_pool->buf_num > bm_pool->size)) {
2790 netdev_err(port->dev,
2791 "cannot allocate %d buffers for pool %d\n",
2792 buf_num, bm_pool->id);
2796 for (i = 0; i < buf_num; i++) {
2797 mvpp2_bm_pool_put(port, bm_pool->id,
2798 (dma_addr_t)buffer_loc.rx_buffer[i],
2799 (unsigned long)buffer_loc.rx_buffer[i]);
2803 /* Update BM driver with number of buffers added to pool */
2804 bm_pool->buf_num += i;
2809 /* Notify the driver that BM pool is being used as specific type and return the
2810 * pool pointer on success
2812 static struct mvpp2_bm_pool *
2813 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
2816 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
2819 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
2820 netdev_err(port->dev, "mixing pool types is forbidden\n");
2824 if (new_pool->type == MVPP2_BM_FREE)
2825 new_pool->type = type;
2827 /* Allocate buffers in case BM pool is used as long pool, but packet
2828 * size doesn't match MTU or BM pool hasn't being used yet
2830 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
2831 (new_pool->pkt_size == 0)) {
2834 /* Set default buffer number or free all the buffers in case
2835 * the pool is not empty
2837 pkts_num = new_pool->buf_num;
2839 pkts_num = type == MVPP2_BM_SWF_LONG ?
2840 MVPP2_BM_LONG_BUF_NUM :
2841 MVPP2_BM_SHORT_BUF_NUM;
2843 mvpp2_bm_bufs_free(NULL,
2844 port->priv, new_pool);
2846 new_pool->pkt_size = pkt_size;
2848 /* Allocate buffers for this pool */
2849 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
2850 if (num != pkts_num) {
2851 dev_err(dev, "pool %d: %d of %d allocated\n",
2852 new_pool->id, num, pkts_num);
2857 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
2858 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
2863 /* Initialize pools for swf */
2864 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
2868 if (!port->pool_long) {
2870 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
2873 if (!port->pool_long)
2876 port->pool_long->port_map |= (1 << port->id);
2878 for (rxq = 0; rxq < rxq_number; rxq++)
2879 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
2885 /* Port configuration routines */
2887 static void mvpp2_port_mii_set(struct mvpp2_port *port)
2891 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2893 switch (port->phy_interface) {
2894 case PHY_INTERFACE_MODE_SGMII:
2895 val |= MVPP2_GMAC_INBAND_AN_MASK;
2897 case PHY_INTERFACE_MODE_RGMII:
2898 case PHY_INTERFACE_MODE_RGMII_ID:
2899 val |= MVPP2_GMAC_PORT_RGMII_MASK;
2901 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
2904 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2907 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
2911 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2912 val |= MVPP2_GMAC_FC_ADV_EN;
2913 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2916 static void mvpp2_port_enable(struct mvpp2_port *port)
2920 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2921 val |= MVPP2_GMAC_PORT_EN_MASK;
2922 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
2923 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2926 static void mvpp2_port_disable(struct mvpp2_port *port)
2930 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2931 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
2932 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2935 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
2936 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
2940 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
2941 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
2942 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2945 /* Configure loopback port */
2946 static void mvpp2_port_loopback_set(struct mvpp2_port *port)
2950 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
2952 if (port->speed == 1000)
2953 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
2955 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
2957 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
2958 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
2960 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
2962 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2965 static void mvpp2_port_reset(struct mvpp2_port *port)
2969 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2970 ~MVPP2_GMAC_PORT_RESET_MASK;
2971 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2973 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2974 MVPP2_GMAC_PORT_RESET_MASK)
2978 /* Change maximum receive size of the port */
2979 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2983 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2984 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2985 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2986 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2987 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2990 /* PPv2.2 GoP/GMAC config */
2992 /* Set the MAC to reset or exit from reset */
2993 static int gop_gmac_reset(struct mvpp2_port *port, int reset)
2997 /* read - modify - write */
2998 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3000 val |= MVPP2_GMAC_PORT_RESET_MASK;
3002 val &= ~MVPP2_GMAC_PORT_RESET_MASK;
3003 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3011 * Configure port to working with Gig PCS or don't.
3013 static int gop_gpcs_mode_cfg(struct mvpp2_port *port, int en)
3017 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3019 val |= MVPP2_GMAC_PCS_ENABLE_MASK;
3021 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
3022 /* enable / disable PCS on this port */
3023 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3028 static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en)
3032 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3034 val |= MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
3036 val &= ~MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
3037 /* enable / disable PCS on this port */
3038 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3043 static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
3048 * Configure minimal level of the Tx FIFO before the lower part
3049 * starts to read a packet
3051 thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
3052 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3053 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3054 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3055 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3057 /* Disable bypass of sync module */
3058 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3059 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3060 /* configure DP clock select according to mode */
3061 val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3062 /* configure QSGMII bypass according to mode */
3063 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3064 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3066 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3068 * Configure GIG MAC to 1000Base-X mode connected to a fiber
3071 val |= MVPP2_GMAC_PORT_TYPE_MASK;
3072 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3074 /* configure AN 0x9268 */
3075 val = MVPP2_GMAC_EN_PCS_AN |
3076 MVPP2_GMAC_AN_BYPASS_EN |
3077 MVPP2_GMAC_CONFIG_MII_SPEED |
3078 MVPP2_GMAC_CONFIG_GMII_SPEED |
3079 MVPP2_GMAC_FC_ADV_EN |
3080 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
3081 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3082 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3085 static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
3090 * Configure minimal level of the Tx FIFO before the lower part
3091 * starts to read a packet
3093 thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
3094 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3095 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3096 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3097 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3099 /* Disable bypass of sync module */
3100 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3101 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3102 /* configure DP clock select according to mode */
3103 val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3104 /* configure QSGMII bypass according to mode */
3105 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3106 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3108 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3109 /* configure GIG MAC to SGMII mode */
3110 val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
3111 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3114 val = MVPP2_GMAC_EN_PCS_AN |
3115 MVPP2_GMAC_AN_BYPASS_EN |
3116 MVPP2_GMAC_AN_SPEED_EN |
3117 MVPP2_GMAC_EN_FC_AN |
3118 MVPP2_GMAC_AN_DUPLEX_EN |
3119 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3120 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3123 static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
3128 * Configure minimal level of the Tx FIFO before the lower part
3129 * starts to read a packet
3131 thresh = MVPP2_RGMII_TX_FIFO_MIN_TH;
3132 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3133 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3134 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
3135 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3137 /* Disable bypass of sync module */
3138 val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
3139 val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
3140 /* configure DP clock select according to mode */
3141 val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
3142 val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
3143 val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK;
3144 writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
3146 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3147 /* configure GIG MAC to SGMII mode */
3148 val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
3149 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3151 /* configure AN 0xb8e8 */
3152 val = MVPP2_GMAC_AN_BYPASS_EN |
3153 MVPP2_GMAC_AN_SPEED_EN |
3154 MVPP2_GMAC_EN_FC_AN |
3155 MVPP2_GMAC_AN_DUPLEX_EN |
3156 MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
3157 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3160 /* Set the internal mux's to the required MAC in the GOP */
3161 static int gop_gmac_mode_cfg(struct mvpp2_port *port)
3165 /* Set TX FIFO thresholds */
3166 switch (port->phy_interface) {
3167 case PHY_INTERFACE_MODE_SGMII:
3168 if (port->phy_speed == 2500)
3169 gop_gmac_sgmii2_5_cfg(port);
3171 gop_gmac_sgmii_cfg(port);
3174 case PHY_INTERFACE_MODE_RGMII:
3175 case PHY_INTERFACE_MODE_RGMII_ID:
3176 gop_gmac_rgmii_cfg(port);
3183 /* Jumbo frame support - 0x1400*2= 0x2800 bytes */
3184 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
3185 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
3186 val |= 0x1400 << MVPP2_GMAC_MAX_RX_SIZE_OFFS;
3187 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
3189 /* PeriodicXonEn disable */
3190 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
3191 val &= ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
3192 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
3197 static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port)
3201 /* relevant only for MAC0 (XLG0 and GMAC0) */
3202 if (port->gop_id > 0)
3205 /* configure 1Gig MAC mode */
3206 val = readl(port->base + MVPP22_XLG_CTRL3_REG);
3207 val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3208 val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
3209 writel(val, port->base + MVPP22_XLG_CTRL3_REG);
3212 static int gop_gpcs_reset(struct mvpp2_port *port, int reset)
3216 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
3218 val &= ~MVPP2_GMAC_SGMII_MODE_MASK;
3220 val |= MVPP2_GMAC_SGMII_MODE_MASK;
3221 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
3226 /* Set the internal mux's to the required PCS in the PI */
3227 static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
3232 switch (num_of_lanes) {
3246 /* configure XG MAC mode */
3247 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3248 val &= ~MVPP22_XPCS_PCSMODE_MASK;
3249 val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
3250 val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
3251 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3256 static int gop_mpcs_mode(struct mvpp2_port *port)
3260 /* configure PCS40G COMMON CONTROL */
3261 val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
3262 val &= ~FORWARD_ERROR_CORRECTION_MASK;
3263 writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
3265 /* configure PCS CLOCK RESET */
3266 val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
3267 val &= ~CLK_DIVISION_RATIO_MASK;
3268 val |= 1 << CLK_DIVISION_RATIO_OFFS;
3269 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
3271 val &= ~CLK_DIV_PHASE_SET_MASK;
3272 val |= MAC_CLK_RESET_MASK;
3273 val |= RX_SD_CLK_RESET_MASK;
3274 val |= TX_SD_CLK_RESET_MASK;
3275 writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
3280 /* Set the internal mux's to the required MAC in the GOP */
3281 static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
3285 /* configure 10G MAC mode */
3286 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3287 val |= MVPP22_XLG_RX_FC_EN;
3288 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3290 val = readl(port->base + MVPP22_XLG_CTRL3_REG);
3291 val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3292 val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
3293 writel(val, port->base + MVPP22_XLG_CTRL3_REG);
3295 /* read - modify - write */
3296 val = readl(port->base + MVPP22_XLG_CTRL4_REG);
3297 val &= ~MVPP22_XLG_MODE_DMA_1G;
3298 val |= MVPP22_XLG_FORWARD_PFC_EN;
3299 val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
3300 val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
3301 writel(val, port->base + MVPP22_XLG_CTRL4_REG);
3303 /* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
3304 val = readl(port->base + MVPP22_XLG_CTRL1_REG);
3305 val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
3306 val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
3307 writel(val, port->base + MVPP22_XLG_CTRL1_REG);
3309 /* unmask link change interrupt */
3310 val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
3311 val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
3312 val |= 1; /* unmask summary bit */
3313 writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
3318 /* Set PCS to reset or exit from reset */
3319 static int gop_xpcs_reset(struct mvpp2_port *port, int reset)
3323 /* read - modify - write */
3324 val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3326 val &= ~MVPP22_XPCS_PCSRESET;
3328 val |= MVPP22_XPCS_PCSRESET;
3329 writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
3334 /* Set the MAC to reset or exit from reset */
3335 static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
3339 /* read - modify - write */
3340 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3342 val &= ~MVPP22_XLG_MAC_RESETN;
3344 val |= MVPP22_XLG_MAC_RESETN;
3345 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3353 * Init physical port. Configures the port mode and all it's elements
3355 * Does not verify that the selected mode/port number is valid at the
3358 static int gop_port_init(struct mvpp2_port *port)
3360 int mac_num = port->gop_id;
3361 int num_of_act_lanes;
3363 if (mac_num >= MVPP22_GOP_MAC_NUM) {
3364 netdev_err(NULL, "%s: illegal port number %d", __func__,
3369 switch (port->phy_interface) {
3370 case PHY_INTERFACE_MODE_RGMII:
3371 case PHY_INTERFACE_MODE_RGMII_ID:
3372 gop_gmac_reset(port, 1);
3375 gop_gpcs_mode_cfg(port, 0);
3376 gop_bypass_clk_cfg(port, 1);
3379 gop_gmac_mode_cfg(port);
3381 gop_gpcs_reset(port, 0);
3384 gop_gmac_reset(port, 0);
3387 case PHY_INTERFACE_MODE_SGMII:
3389 gop_gpcs_mode_cfg(port, 1);
3392 gop_gmac_mode_cfg(port);
3393 /* select proper Mac mode */
3394 gop_xlg_2_gig_mac_cfg(port);
3397 gop_gpcs_reset(port, 0);
3399 gop_gmac_reset(port, 0);
3402 case PHY_INTERFACE_MODE_SFI:
3403 num_of_act_lanes = 2;
3406 gop_xpcs_mode(port, num_of_act_lanes);
3407 gop_mpcs_mode(port);
3409 gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
3412 gop_xpcs_reset(port, 0);
3415 gop_xlg_mac_reset(port, 0);
3419 netdev_err(NULL, "%s: Requested port mode (%d) not supported\n",
3420 __func__, port->phy_interface);
3427 static void gop_xlg_mac_port_enable(struct mvpp2_port *port, int enable)
3431 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
3433 /* Enable port and MIB counters update */
3434 val |= MVPP22_XLG_PORT_EN;
3435 val &= ~MVPP22_XLG_MIBCNT_DIS;
3438 val &= ~MVPP22_XLG_PORT_EN;
3440 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
3443 static void gop_port_enable(struct mvpp2_port *port, int enable)
3445 switch (port->phy_interface) {
3446 case PHY_INTERFACE_MODE_RGMII:
3447 case PHY_INTERFACE_MODE_RGMII_ID:
3448 case PHY_INTERFACE_MODE_SGMII:
3450 mvpp2_port_enable(port);
3452 mvpp2_port_disable(port);
3455 case PHY_INTERFACE_MODE_SFI:
3456 gop_xlg_mac_port_enable(port, enable);
3460 netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__,
3461 port->phy_interface);
3466 /* RFU1 functions */
3467 static inline u32 gop_rfu1_read(struct mvpp2 *priv, u32 offset)
3469 return readl(priv->rfu1_base + offset);
3472 static inline void gop_rfu1_write(struct mvpp2 *priv, u32 offset, u32 data)
3474 writel(data, priv->rfu1_base + offset);
3477 static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
3482 if (phy_type == PHY_INTERFACE_MODE_SGMII)
3483 val |= MV_NETC_GE_MAC2_SGMII;
3487 if (phy_type == PHY_INTERFACE_MODE_SGMII)
3488 val |= MV_NETC_GE_MAC3_SGMII;
3489 else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
3490 phy_type == PHY_INTERFACE_MODE_RGMII_ID)
3491 val |= MV_NETC_GE_MAC3_RGMII;
3497 static void gop_netc_active_port(struct mvpp2 *priv, int gop_id, u32 val)
3501 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
3502 reg &= ~(NETC_PORTS_ACTIVE_MASK(gop_id));
3504 val <<= NETC_PORTS_ACTIVE_OFFSET(gop_id);
3505 val &= NETC_PORTS_ACTIVE_MASK(gop_id);
3509 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
3512 static void gop_netc_mii_mode(struct mvpp2 *priv, int gop_id, u32 val)
3516 reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
3517 reg &= ~NETC_GBE_PORT1_MII_MODE_MASK;
3519 val <<= NETC_GBE_PORT1_MII_MODE_OFFS;
3520 val &= NETC_GBE_PORT1_MII_MODE_MASK;
3524 gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
3527 static void gop_netc_gop_reset(struct mvpp2 *priv, u32 val)
3531 reg = gop_rfu1_read(priv, GOP_SOFT_RESET_1_REG);
3532 reg &= ~NETC_GOP_SOFT_RESET_MASK;
3534 val <<= NETC_GOP_SOFT_RESET_OFFS;
3535 val &= NETC_GOP_SOFT_RESET_MASK;
3539 gop_rfu1_write(priv, GOP_SOFT_RESET_1_REG, reg);
3542 static void gop_netc_gop_clock_logic_set(struct mvpp2 *priv, u32 val)
3546 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3547 reg &= ~NETC_CLK_DIV_PHASE_MASK;
3549 val <<= NETC_CLK_DIV_PHASE_OFFS;
3550 val &= NETC_CLK_DIV_PHASE_MASK;
3554 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3557 static void gop_netc_port_rf_reset(struct mvpp2 *priv, int gop_id, u32 val)
3561 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
3562 reg &= ~(NETC_PORT_GIG_RF_RESET_MASK(gop_id));
3564 val <<= NETC_PORT_GIG_RF_RESET_OFFS(gop_id);
3565 val &= NETC_PORT_GIG_RF_RESET_MASK(gop_id);
3569 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
3572 static void gop_netc_gbe_sgmii_mode_select(struct mvpp2 *priv, int gop_id,
3575 u32 reg, mask, offset;
3578 mask = NETC_GBE_PORT0_SGMII_MODE_MASK;
3579 offset = NETC_GBE_PORT0_SGMII_MODE_OFFS;
3581 mask = NETC_GBE_PORT1_SGMII_MODE_MASK;
3582 offset = NETC_GBE_PORT1_SGMII_MODE_OFFS;
3584 reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
3592 gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
3595 static void gop_netc_bus_width_select(struct mvpp2 *priv, u32 val)
3599 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3600 reg &= ~NETC_BUS_WIDTH_SELECT_MASK;
3602 val <<= NETC_BUS_WIDTH_SELECT_OFFS;
3603 val &= NETC_BUS_WIDTH_SELECT_MASK;
3607 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3610 static void gop_netc_sample_stages_timing(struct mvpp2 *priv, u32 val)
3614 reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
3615 reg &= ~NETC_GIG_RX_DATA_SAMPLE_MASK;
3617 val <<= NETC_GIG_RX_DATA_SAMPLE_OFFS;
3618 val &= NETC_GIG_RX_DATA_SAMPLE_MASK;
3622 gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
3625 static void gop_netc_mac_to_xgmii(struct mvpp2 *priv, int gop_id,
3626 enum mv_netc_phase phase)
3629 case MV_NETC_FIRST_PHASE:
3630 /* Set Bus Width to HB mode = 1 */
3631 gop_netc_bus_width_select(priv, 1);
3632 /* Select RGMII mode */
3633 gop_netc_gbe_sgmii_mode_select(priv, gop_id, MV_NETC_GBE_XMII);
3636 case MV_NETC_SECOND_PHASE:
3637 /* De-assert the relevant port HB reset */
3638 gop_netc_port_rf_reset(priv, gop_id, 1);
3643 static void gop_netc_mac_to_sgmii(struct mvpp2 *priv, int gop_id,
3644 enum mv_netc_phase phase)
3647 case MV_NETC_FIRST_PHASE:
3648 /* Set Bus Width to HB mode = 1 */
3649 gop_netc_bus_width_select(priv, 1);
3650 /* Select SGMII mode */
3652 gop_netc_gbe_sgmii_mode_select(priv, gop_id,
3656 /* Configure the sample stages */
3657 gop_netc_sample_stages_timing(priv, 0);
3658 /* Configure the ComPhy Selector */
3659 /* gop_netc_com_phy_selector_config(netComplex); */
3662 case MV_NETC_SECOND_PHASE:
3663 /* De-assert the relevant port HB reset */
3664 gop_netc_port_rf_reset(priv, gop_id, 1);
3669 static int gop_netc_init(struct mvpp2 *priv, enum mv_netc_phase phase)
3671 u32 c = priv->netc_config;
3673 if (c & MV_NETC_GE_MAC2_SGMII)
3674 gop_netc_mac_to_sgmii(priv, 2, phase);
3676 gop_netc_mac_to_xgmii(priv, 2, phase);
3678 if (c & MV_NETC_GE_MAC3_SGMII) {
3679 gop_netc_mac_to_sgmii(priv, 3, phase);
3681 gop_netc_mac_to_xgmii(priv, 3, phase);
3682 if (c & MV_NETC_GE_MAC3_RGMII)
3683 gop_netc_mii_mode(priv, 3, MV_NETC_GBE_RGMII);
3685 gop_netc_mii_mode(priv, 3, MV_NETC_GBE_MII);
3688 /* Activate gop ports 0, 2, 3 */
3689 gop_netc_active_port(priv, 0, 1);
3690 gop_netc_active_port(priv, 2, 1);
3691 gop_netc_active_port(priv, 3, 1);
3693 if (phase == MV_NETC_SECOND_PHASE) {
3694 /* Enable the GOP internal clock logic */
3695 gop_netc_gop_clock_logic_set(priv, 1);
3696 /* De-assert GOP unit reset */
3697 gop_netc_gop_reset(priv, 1);
3703 /* Set defaults to the MVPP2 port */
3704 static void mvpp2_defaults_set(struct mvpp2_port *port)
3706 int tx_port_num, val, queue, ptxq, lrxq;
3708 if (port->priv->hw_version == MVPP21) {
3709 /* Configure port to loopback if needed */
3710 if (port->flags & MVPP2_F_LOOPBACK)
3711 mvpp2_port_loopback_set(port);
3713 /* Update TX FIFO MIN Threshold */
3714 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3715 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
3716 /* Min. TX threshold must be less than minimal packet length */
3717 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
3718 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
3721 /* Disable Legacy WRR, Disable EJP, Release from reset */
3722 tx_port_num = mvpp2_egress_port(port);
3723 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
3725 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
3727 /* Close bandwidth for all queues */
3728 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
3729 ptxq = mvpp2_txq_phys(port->id, queue);
3730 mvpp2_write(port->priv,
3731 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
3734 /* Set refill period to 1 usec, refill tokens
3735 * and bucket size to maximum
3737 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
3738 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
3739 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
3740 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
3741 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
3742 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
3743 val = MVPP2_TXP_TOKEN_SIZE_MAX;
3744 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3746 /* Set MaximumLowLatencyPacketSize value to 256 */
3747 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
3748 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
3749 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
3751 /* Enable Rx cache snoop */
3752 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3753 queue = port->rxqs[lrxq]->id;
3754 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3755 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
3756 MVPP2_SNOOP_BUF_HDR_MASK;
3757 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3761 /* Enable/disable receiving packets */
3762 static void mvpp2_ingress_enable(struct mvpp2_port *port)
3767 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3768 queue = port->rxqs[lrxq]->id;
3769 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3770 val &= ~MVPP2_RXQ_DISABLE_MASK;
3771 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3775 static void mvpp2_ingress_disable(struct mvpp2_port *port)
3780 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
3781 queue = port->rxqs[lrxq]->id;
3782 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
3783 val |= MVPP2_RXQ_DISABLE_MASK;
3784 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
3788 /* Enable transmit via physical egress queue
3789 * - HW starts take descriptors from DRAM
3791 static void mvpp2_egress_enable(struct mvpp2_port *port)
3795 int tx_port_num = mvpp2_egress_port(port);
3797 /* Enable all initialized TXs. */
3799 for (queue = 0; queue < txq_number; queue++) {
3800 struct mvpp2_tx_queue *txq = port->txqs[queue];
3802 if (txq->descs != NULL)
3803 qmap |= (1 << queue);
3806 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3807 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
3810 /* Disable transmit via physical egress queue
3811 * - HW doesn't take descriptors from DRAM
3813 static void mvpp2_egress_disable(struct mvpp2_port *port)
3817 int tx_port_num = mvpp2_egress_port(port);
3819 /* Issue stop command for active channels only */
3820 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3821 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
3822 MVPP2_TXP_SCHED_ENQ_MASK;
3824 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
3825 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
3827 /* Wait for all Tx activity to terminate. */
3830 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
3831 netdev_warn(port->dev,
3832 "Tx stop timed out, status=0x%08x\n",
3839 /* Check port TX Command register that all
3840 * Tx queues are stopped
3842 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
3843 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
3846 /* Rx descriptors helper methods */
3848 /* Get number of Rx descriptors occupied by received packets */
3850 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
3852 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
3854 return val & MVPP2_RXQ_OCCUPIED_MASK;
3857 /* Update Rx queue status with the number of occupied and available
3858 * Rx descriptor slots.
3861 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
3862 int used_count, int free_count)
3864 /* Decrement the number of used descriptors and increment count
3865 * increment the number of free descriptors.
3867 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
3869 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
3872 /* Get pointer to next RX descriptor to be processed by SW */
3873 static inline struct mvpp2_rx_desc *
3874 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
3876 int rx_desc = rxq->next_desc_to_proc;
3878 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
3879 prefetch(rxq->descs + rxq->next_desc_to_proc);
3880 return rxq->descs + rx_desc;
3883 /* Set rx queue offset */
3884 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
3885 int prxq, int offset)
3889 /* Convert offset from bytes to units of 32 bytes */
3890 offset = offset >> 5;
3892 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
3893 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
3896 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
3897 MVPP2_RXQ_PACKET_OFFSET_MASK);
3899 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
3902 /* Obtain BM cookie information from descriptor */
3903 static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
3904 struct mvpp2_rx_desc *rx_desc)
3906 int cpu = smp_processor_id();
3909 pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
3910 MVPP2_RXD_BM_POOL_ID_MASK) >>
3911 MVPP2_RXD_BM_POOL_ID_OFFS;
3913 return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
3914 ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
3917 /* Tx descriptors helper methods */
3919 /* Get number of Tx descriptors waiting to be transmitted by HW */
3920 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
3921 struct mvpp2_tx_queue *txq)
3925 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3926 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3928 return val & MVPP2_TXQ_PENDING_MASK;
3931 /* Get pointer to next Tx descriptor to be processed (send) by HW */
3932 static struct mvpp2_tx_desc *
3933 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
3935 int tx_desc = txq->next_desc_to_proc;
3937 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
3938 return txq->descs + tx_desc;
3941 /* Update HW with number of aggregated Tx descriptors to be sent */
3942 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
3944 /* aggregated access - relevant TXQ number is written in TX desc */
3945 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
3948 /* Get number of sent descriptors and decrement counter.
3949 * The number of sent descriptors is returned.
3952 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
3953 struct mvpp2_tx_queue *txq)
3957 /* Reading status reg resets transmitted descriptor counter */
3958 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
3960 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
3961 MVPP2_TRANSMITTED_COUNT_OFFSET;
3964 static void mvpp2_txq_sent_counter_clear(void *arg)
3966 struct mvpp2_port *port = arg;
3969 for (queue = 0; queue < txq_number; queue++) {
3970 int id = port->txqs[queue]->id;
3972 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
3976 /* Set max sizes for Tx queues */
3977 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
3980 int txq, tx_port_num;
3982 mtu = port->pkt_size * 8;
3983 if (mtu > MVPP2_TXP_MTU_MAX)
3984 mtu = MVPP2_TXP_MTU_MAX;
3986 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
3989 /* Indirect access to registers */
3990 tx_port_num = mvpp2_egress_port(port);
3991 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3994 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
3995 val &= ~MVPP2_TXP_MTU_MAX;
3997 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
3999 /* TXP token size and all TXQs token size must be larger that MTU */
4000 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
4001 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
4004 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
4006 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
4009 for (txq = 0; txq < txq_number; txq++) {
4010 val = mvpp2_read(port->priv,
4011 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
4012 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
4016 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
4018 mvpp2_write(port->priv,
4019 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
4025 /* Free Tx queue skbuffs */
4026 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
4027 struct mvpp2_tx_queue *txq,
4028 struct mvpp2_txq_pcpu *txq_pcpu, int num)
4032 for (i = 0; i < num; i++)
4033 mvpp2_txq_inc_get(txq_pcpu);
4036 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
4039 int queue = fls(cause) - 1;
4041 return port->rxqs[queue];
4044 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
4047 int queue = fls(cause) - 1;
4049 return port->txqs[queue];
4052 /* Rx/Tx queue initialization/cleanup methods */
4054 /* Allocate and initialize descriptors for aggr TXQ */
4055 static int mvpp2_aggr_txq_init(struct udevice *dev,
4056 struct mvpp2_tx_queue *aggr_txq,
4057 int desc_num, int cpu,
4062 /* Allocate memory for TX descriptors */
4063 aggr_txq->descs = buffer_loc.aggr_tx_descs;
4064 aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
4065 if (!aggr_txq->descs)
4068 /* Make sure descriptor address is cache line size aligned */
4069 BUG_ON(aggr_txq->descs !=
4070 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4072 aggr_txq->last_desc = aggr_txq->size - 1;
4074 /* Aggr TXQ no reset WA */
4075 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
4076 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
4078 /* Set Tx descriptors queue starting address indirect
4081 if (priv->hw_version == MVPP21)
4082 txq_dma = aggr_txq->descs_dma;
4084 txq_dma = aggr_txq->descs_dma >>
4085 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
4087 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
4088 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
4093 /* Create a specified Rx queue */
4094 static int mvpp2_rxq_init(struct mvpp2_port *port,
4095 struct mvpp2_rx_queue *rxq)
4100 rxq->size = port->rx_ring_size;
4102 /* Allocate memory for RX descriptors */
4103 rxq->descs = buffer_loc.rx_descs;
4104 rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
4108 BUG_ON(rxq->descs !=
4109 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4111 rxq->last_desc = rxq->size - 1;
4113 /* Zero occupied and non-occupied counters - direct access */
4114 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4116 /* Set Rx descriptors queue starting address - indirect access */
4117 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4118 if (port->priv->hw_version == MVPP21)
4119 rxq_dma = rxq->descs_dma;
4121 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
4122 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
4123 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
4124 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
4127 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
4129 /* Add number of descriptors ready for receiving packets */
4130 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
4135 /* Push packets received by the RXQ to BM pool */
4136 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
4137 struct mvpp2_rx_queue *rxq)
4141 rx_received = mvpp2_rxq_received(port, rxq->id);
4145 for (i = 0; i < rx_received; i++) {
4146 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
4147 u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
4149 mvpp2_pool_refill(port, bm,
4150 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
4151 mvpp2_rxdesc_cookie_get(port, rx_desc));
4153 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
4156 /* Cleanup Rx queue */
4157 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
4158 struct mvpp2_rx_queue *rxq)
4160 mvpp2_rxq_drop_pkts(port, rxq);
4164 rxq->next_desc_to_proc = 0;
4167 /* Clear Rx descriptors queue starting address and size;
4168 * free descriptor number
4170 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4171 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4172 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
4173 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
4176 /* Create and initialize a Tx queue */
4177 static int mvpp2_txq_init(struct mvpp2_port *port,
4178 struct mvpp2_tx_queue *txq)
4181 int cpu, desc, desc_per_txq, tx_port_num;
4182 struct mvpp2_txq_pcpu *txq_pcpu;
4184 txq->size = port->tx_ring_size;
4186 /* Allocate memory for Tx descriptors */
4187 txq->descs = buffer_loc.tx_descs;
4188 txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
4192 /* Make sure descriptor address is cache line size aligned */
4193 BUG_ON(txq->descs !=
4194 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4196 txq->last_desc = txq->size - 1;
4198 /* Set Tx descriptors queue starting address - indirect access */
4199 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4200 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
4201 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
4202 MVPP2_TXQ_DESC_SIZE_MASK);
4203 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
4204 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
4205 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
4206 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
4207 val &= ~MVPP2_TXQ_PENDING_MASK;
4208 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
4210 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
4211 * for each existing TXQ.
4212 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
4213 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
4216 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
4217 (txq->log_id * desc_per_txq);
4219 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
4220 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
4221 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
4223 /* WRR / EJP configuration - indirect access */
4224 tx_port_num = mvpp2_egress_port(port);
4225 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
4227 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
4228 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
4229 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
4230 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
4231 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
4233 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
4234 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
4237 for_each_present_cpu(cpu) {
4238 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4239 txq_pcpu->size = txq->size;
4245 /* Free allocated TXQ resources */
4246 static void mvpp2_txq_deinit(struct mvpp2_port *port,
4247 struct mvpp2_tx_queue *txq)
4251 txq->next_desc_to_proc = 0;
4254 /* Set minimum bandwidth for disabled TXQs */
4255 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
4257 /* Set Tx descriptors queue starting address and size */
4258 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4259 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
4260 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
4263 /* Cleanup Tx ports */
4264 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
4266 struct mvpp2_txq_pcpu *txq_pcpu;
4267 int delay, pending, cpu;
4270 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4271 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
4272 val |= MVPP2_TXQ_DRAIN_EN_MASK;
4273 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4275 /* The napi queue has been stopped so wait for all packets
4276 * to be transmitted.
4280 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
4281 netdev_warn(port->dev,
4282 "port %d: cleaning queue %d timed out\n",
4283 port->id, txq->log_id);
4289 pending = mvpp2_txq_pend_desc_num_get(port, txq);
4292 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
4293 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4295 for_each_present_cpu(cpu) {
4296 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4298 /* Release all packets */
4299 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
4302 txq_pcpu->count = 0;
4303 txq_pcpu->txq_put_index = 0;
4304 txq_pcpu->txq_get_index = 0;
4308 /* Cleanup all Tx queues */
4309 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
4311 struct mvpp2_tx_queue *txq;
4315 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
4317 /* Reset Tx ports and delete Tx queues */
4318 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
4319 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4321 for (queue = 0; queue < txq_number; queue++) {
4322 txq = port->txqs[queue];
4323 mvpp2_txq_clean(port, txq);
4324 mvpp2_txq_deinit(port, txq);
4327 mvpp2_txq_sent_counter_clear(port);
4329 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
4330 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
4333 /* Cleanup all Rx queues */
4334 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
4338 for (queue = 0; queue < rxq_number; queue++)
4339 mvpp2_rxq_deinit(port, port->rxqs[queue]);
4342 /* Init all Rx queues for port */
4343 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
4347 for (queue = 0; queue < rxq_number; queue++) {
4348 err = mvpp2_rxq_init(port, port->rxqs[queue]);
4355 mvpp2_cleanup_rxqs(port);
4359 /* Init all tx queues for port */
4360 static int mvpp2_setup_txqs(struct mvpp2_port *port)
4362 struct mvpp2_tx_queue *txq;
4365 for (queue = 0; queue < txq_number; queue++) {
4366 txq = port->txqs[queue];
4367 err = mvpp2_txq_init(port, txq);
4372 mvpp2_txq_sent_counter_clear(port);
4376 mvpp2_cleanup_txqs(port);
4381 static void mvpp2_link_event(struct mvpp2_port *port)
4383 struct phy_device *phydev = port->phy_dev;
4384 int status_change = 0;
4388 if ((port->speed != phydev->speed) ||
4389 (port->duplex != phydev->duplex)) {
4392 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4393 val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
4394 MVPP2_GMAC_CONFIG_GMII_SPEED |
4395 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
4396 MVPP2_GMAC_AN_SPEED_EN |
4397 MVPP2_GMAC_AN_DUPLEX_EN);
4400 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4402 if (phydev->speed == SPEED_1000)
4403 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
4404 else if (phydev->speed == SPEED_100)
4405 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
4407 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4409 port->duplex = phydev->duplex;
4410 port->speed = phydev->speed;
4414 if (phydev->link != port->link) {
4415 if (!phydev->link) {
4420 port->link = phydev->link;
4424 if (status_change) {
4426 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4427 val |= (MVPP2_GMAC_FORCE_LINK_PASS |
4428 MVPP2_GMAC_FORCE_LINK_DOWN);
4429 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4430 mvpp2_egress_enable(port);
4431 mvpp2_ingress_enable(port);
4433 mvpp2_ingress_disable(port);
4434 mvpp2_egress_disable(port);
4439 /* Main RX/TX processing routines */
4441 /* Display more error info */
4442 static void mvpp2_rx_error(struct mvpp2_port *port,
4443 struct mvpp2_rx_desc *rx_desc)
4445 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
4446 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
4448 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
4449 case MVPP2_RXD_ERR_CRC:
4450 netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
4453 case MVPP2_RXD_ERR_OVERRUN:
4454 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
4457 case MVPP2_RXD_ERR_RESOURCE:
4458 netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
4464 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
4465 static int mvpp2_rx_refill(struct mvpp2_port *port,
4466 struct mvpp2_bm_pool *bm_pool,
4467 u32 bm, dma_addr_t dma_addr)
4469 mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
4473 /* Set hw internals when starting port */
4474 static void mvpp2_start_dev(struct mvpp2_port *port)
4476 switch (port->phy_interface) {
4477 case PHY_INTERFACE_MODE_RGMII:
4478 case PHY_INTERFACE_MODE_RGMII_ID:
4479 case PHY_INTERFACE_MODE_SGMII:
4480 mvpp2_gmac_max_rx_size_set(port);
4485 mvpp2_txp_max_tx_size_set(port);
4487 if (port->priv->hw_version == MVPP21)
4488 mvpp2_port_enable(port);
4490 gop_port_enable(port, 1);
4493 /* Set hw internals when stopping port */
4494 static void mvpp2_stop_dev(struct mvpp2_port *port)
4496 /* Stop new packets from arriving to RXQs */
4497 mvpp2_ingress_disable(port);
4499 mvpp2_egress_disable(port);
4501 if (port->priv->hw_version == MVPP21)
4502 mvpp2_port_disable(port);
4504 gop_port_enable(port, 0);
4507 static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
4509 struct phy_device *phy_dev;
4511 if (!port->init || port->link == 0) {
4512 phy_dev = phy_connect(port->priv->bus, port->phyaddr, dev,
4513 port->phy_interface);
4514 port->phy_dev = phy_dev;
4516 netdev_err(port->dev, "cannot connect to phy\n");
4519 phy_dev->supported &= PHY_GBIT_FEATURES;
4520 phy_dev->advertising = phy_dev->supported;
4522 port->phy_dev = phy_dev;
4527 phy_config(phy_dev);
4528 phy_startup(phy_dev);
4529 if (!phy_dev->link) {
4530 printf("%s: No link\n", phy_dev->dev->name);
4536 mvpp2_egress_enable(port);
4537 mvpp2_ingress_enable(port);
4543 static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
4545 unsigned char mac_bcast[ETH_ALEN] = {
4546 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4549 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
4551 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
4554 err = mvpp2_prs_mac_da_accept(port->priv, port->id,
4555 port->dev_addr, true);
4557 netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
4560 err = mvpp2_prs_def_flow(port);
4562 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
4566 /* Allocate the Rx/Tx queues */
4567 err = mvpp2_setup_rxqs(port);
4569 netdev_err(port->dev, "cannot allocate Rx queues\n");
4573 err = mvpp2_setup_txqs(port);
4575 netdev_err(port->dev, "cannot allocate Tx queues\n");
4579 if (port->phy_node) {
4580 err = mvpp2_phy_connect(dev, port);
4584 mvpp2_link_event(port);
4586 mvpp2_egress_enable(port);
4587 mvpp2_ingress_enable(port);
4590 mvpp2_start_dev(port);
4595 /* No Device ops here in U-Boot */
4597 /* Driver initialization */
4599 static void mvpp2_port_power_up(struct mvpp2_port *port)
4601 struct mvpp2 *priv = port->priv;
4603 /* On PPv2.2 the GoP / interface configuration has already been done */
4604 if (priv->hw_version == MVPP21)
4605 mvpp2_port_mii_set(port);
4606 mvpp2_port_periodic_xon_disable(port);
4607 if (priv->hw_version == MVPP21)
4608 mvpp2_port_fc_adv_enable(port);
4609 mvpp2_port_reset(port);
4612 /* Initialize port HW */
4613 static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
4615 struct mvpp2 *priv = port->priv;
4616 struct mvpp2_txq_pcpu *txq_pcpu;
4617 int queue, cpu, err;
4619 if (port->first_rxq + rxq_number >
4620 MVPP2_MAX_PORTS * priv->max_port_rxqs)
4624 mvpp2_egress_disable(port);
4625 if (priv->hw_version == MVPP21)
4626 mvpp2_port_disable(port);
4628 gop_port_enable(port, 0);
4630 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
4635 /* Associate physical Tx queues to this port and initialize.
4636 * The mapping is predefined.
4638 for (queue = 0; queue < txq_number; queue++) {
4639 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
4640 struct mvpp2_tx_queue *txq;
4642 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
4646 txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
4651 txq->id = queue_phy_id;
4652 txq->log_id = queue;
4653 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
4654 for_each_present_cpu(cpu) {
4655 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4656 txq_pcpu->cpu = cpu;
4659 port->txqs[queue] = txq;
4662 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
4667 /* Allocate and initialize Rx queue for this port */
4668 for (queue = 0; queue < rxq_number; queue++) {
4669 struct mvpp2_rx_queue *rxq;
4671 /* Map physical Rx queue to port's logical Rx queue */
4672 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
4675 /* Map this Rx queue to a physical queue */
4676 rxq->id = port->first_rxq + queue;
4677 rxq->port = port->id;
4678 rxq->logic_rxq = queue;
4680 port->rxqs[queue] = rxq;
4683 /* Configure Rx queue group interrupt for this port */
4684 if (priv->hw_version == MVPP21) {
4685 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
4690 val = (port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
4691 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
4693 val = (CONFIG_MV_ETH_RXQ <<
4694 MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
4695 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
4698 /* Create Rx descriptor rings */
4699 for (queue = 0; queue < rxq_number; queue++) {
4700 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4702 rxq->size = port->rx_ring_size;
4703 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
4704 rxq->time_coal = MVPP2_RX_COAL_USEC;
4707 mvpp2_ingress_disable(port);
4709 /* Port default configuration */
4710 mvpp2_defaults_set(port);
4712 /* Port's classifier configuration */
4713 mvpp2_cls_oversize_rxq_set(port);
4714 mvpp2_cls_port_config(port);
4716 /* Provide an initial Rx packet size */
4717 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
4719 /* Initialize pools for swf */
4720 err = mvpp2_swf_bm_pool_init(port);
4727 static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
4729 int port_node = dev_of_offset(dev);
4730 const char *phy_mode_str;
4731 int phy_node, mdio_off, cp_node;
4737 phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
4740 phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
4742 dev_err(&pdev->dev, "could not find phy address\n");
4745 mdio_off = fdt_parent_offset(gd->fdt_blob, phy_node);
4747 /* TODO: This WA for mdio issue. U-boot 2017 don't have
4748 * mdio driver and on MACHIATOBin board ports from CP1
4749 * connected to mdio on CP0.
4750 * WA is to get mdio address from phy handler parent
4751 * base address. WA should be removed after
4752 * mdio driver implementation.
4754 mdio_addr = fdtdec_get_uint(gd->fdt_blob,
4755 mdio_off, "reg", 0);
4757 cp_node = fdt_parent_offset(gd->fdt_blob, mdio_off);
4758 mdio_addr |= fdt_get_base_address((void *)gd->fdt_blob,
4761 port->priv->mdio_base = (void *)mdio_addr;
4763 if (port->priv->mdio_base < 0) {
4764 dev_err(&pdev->dev, "could not find mdio base address\n");
4771 phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
4773 phy_mode = phy_get_interface_by_name(phy_mode_str);
4774 if (phy_mode == -1) {
4775 dev_err(&pdev->dev, "incorrect phy mode\n");
4779 id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
4781 dev_err(&pdev->dev, "missing port-id value\n");
4785 #ifdef CONFIG_DM_GPIO
4786 gpio_request_by_name(dev, "phy-reset-gpios", 0,
4787 &port->phy_reset_gpio, GPIOD_IS_OUT);
4788 gpio_request_by_name(dev, "marvell,sfp-tx-disable-gpio", 0,
4789 &port->phy_tx_disable_gpio, GPIOD_IS_OUT);
4794 * Not sure if this DT property "phy-speed" will get accepted, so
4795 * this might change later
4797 /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */
4798 port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
4802 if (port->priv->hw_version == MVPP21)
4803 port->first_rxq = port->id * rxq_number;
4805 port->first_rxq = port->id * port->priv->max_port_rxqs;
4806 port->phy_node = phy_node;
4807 port->phy_interface = phy_mode;
4808 port->phyaddr = phyaddr;
4813 #ifdef CONFIG_DM_GPIO
4814 /* Port GPIO initialization */
4815 static void mvpp2_gpio_init(struct mvpp2_port *port)
4817 if (dm_gpio_is_valid(&port->phy_reset_gpio)) {
4818 dm_gpio_set_value(&port->phy_reset_gpio, 0);
4820 dm_gpio_set_value(&port->phy_reset_gpio, 1);
4823 if (dm_gpio_is_valid(&port->phy_tx_disable_gpio))
4824 dm_gpio_set_value(&port->phy_tx_disable_gpio, 0);
4828 /* Ports initialization */
4829 static int mvpp2_port_probe(struct udevice *dev,
4830 struct mvpp2_port *port,
4836 port->tx_ring_size = MVPP2_MAX_TXD;
4837 port->rx_ring_size = MVPP2_MAX_RXD;
4839 err = mvpp2_port_init(dev, port);
4841 dev_err(&pdev->dev, "failed to init port %d\n", port->id);
4844 mvpp2_port_power_up(port);
4846 #ifdef CONFIG_DM_GPIO
4847 mvpp2_gpio_init(port);
4850 priv->port_list[port->id] = port;
4854 /* Initialize decoding windows */
4855 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
4861 for (i = 0; i < 6; i++) {
4862 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
4863 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
4866 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
4871 for (i = 0; i < dram->num_cs; i++) {
4872 const struct mbus_dram_window *cs = dram->cs + i;
4874 mvpp2_write(priv, MVPP2_WIN_BASE(i),
4875 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
4876 dram->mbus_dram_target_id);
4878 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
4879 (cs->size - 1) & 0xffff0000);
4881 win_enable |= (1 << i);
4884 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
4887 /* Initialize Rx FIFO's */
4888 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
4892 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4893 if (priv->hw_version == MVPP22) {
4896 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4897 MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE);
4899 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4900 MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE);
4901 } else if (port == 1) {
4903 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4904 MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE);
4906 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4907 MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE);
4910 MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4911 MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE);
4913 MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4914 MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE);
4917 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4918 MVPP21_RX_FIFO_PORT_DATA_SIZE);
4919 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4920 MVPP21_RX_FIFO_PORT_ATTR_SIZE);
4924 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
4925 MVPP2_RX_FIFO_PORT_MIN_PKT);
4926 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
4929 /* Initialize Tx FIFO's */
4930 static void mvpp2_tx_fifo_init(struct mvpp2 *priv)
4934 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4935 /* Port 0 supports 10KB TX FIFO */
4937 val = MVPP2_TX_FIFO_DATA_SIZE_10KB &
4938 MVPP22_TX_FIFO_SIZE_MASK;
4940 val = MVPP2_TX_FIFO_DATA_SIZE_3KB &
4941 MVPP22_TX_FIFO_SIZE_MASK;
4943 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val);
4947 static void mvpp2_axi_init(struct mvpp2 *priv)
4949 u32 val, rdval, wrval;
4951 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
4953 /* AXI Bridge Configuration */
4955 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
4956 << MVPP22_AXI_ATTR_CACHE_OFFS;
4957 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4958 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4960 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
4961 << MVPP22_AXI_ATTR_CACHE_OFFS;
4962 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4963 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4966 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
4967 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
4970 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
4971 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
4972 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
4973 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
4976 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
4977 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
4979 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
4980 << MVPP22_AXI_CODE_CACHE_OFFS;
4981 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
4982 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4983 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
4984 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
4986 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
4987 << MVPP22_AXI_CODE_CACHE_OFFS;
4988 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4989 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4991 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
4993 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
4994 << MVPP22_AXI_CODE_CACHE_OFFS;
4995 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4996 << MVPP22_AXI_CODE_DOMAIN_OFFS;
4998 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
5001 /* Initialize network controller common part HW */
5002 static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
5004 const struct mbus_dram_target_info *dram_target_info;
5008 /* Checks for hardware constraints (U-Boot uses only one rxq) */
5009 if ((rxq_number > priv->max_port_rxqs) ||
5010 (txq_number > MVPP2_MAX_TXQ)) {
5011 dev_err(&pdev->dev, "invalid queue size parameter\n");
5015 /* MBUS windows configuration */
5016 dram_target_info = mvebu_mbus_dram_info();
5017 if (dram_target_info)
5018 mvpp2_conf_mbus_windows(dram_target_info, priv);
5020 if (priv->hw_version == MVPP22)
5021 mvpp2_axi_init(priv);
5023 if (priv->hw_version == MVPP21) {
5024 /* Disable HW PHY polling */
5025 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5026 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
5027 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5029 /* Enable HW PHY polling */
5030 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5031 val |= MVPP22_SMI_POLLING_EN;
5032 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5035 /* Allocate and initialize aggregated TXQs */
5036 priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
5037 sizeof(struct mvpp2_tx_queue),
5039 if (!priv->aggr_txqs)
5042 for_each_present_cpu(i) {
5043 priv->aggr_txqs[i].id = i;
5044 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
5045 err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
5046 MVPP2_AGGR_TXQ_SIZE, i, priv);
5052 mvpp2_rx_fifo_init(priv);
5055 if (priv->hw_version == MVPP22)
5056 mvpp2_tx_fifo_init(priv);
5058 /* Reset Rx queue group interrupt configuration */
5059 for (i = 0; i < MVPP2_MAX_PORTS; i++) {
5060 if (priv->hw_version == MVPP21) {
5061 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(i),
5067 val = (i << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
5068 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
5070 val = (CONFIG_MV_ETH_RXQ <<
5071 MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
5073 MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
5077 if (priv->hw_version == MVPP21)
5078 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
5079 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
5081 /* Allow cache snoop when transmiting packets */
5082 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
5084 /* Buffer Manager initialization */
5085 err = mvpp2_bm_init(dev, priv);
5089 /* Parser default initialization */
5090 err = mvpp2_prs_default_init(dev, priv);
5094 /* Classifier default initialization */
5095 mvpp2_cls_init(priv);
5100 /* SMI / MDIO functions */
5102 static int smi_wait_ready(struct mvpp2 *priv)
5104 u32 timeout = MVPP2_SMI_TIMEOUT;
5107 /* wait till the SMI is not busy */
5109 /* read smi register */
5110 smi_reg = readl(priv->mdio_base);
5111 if (timeout-- == 0) {
5112 printf("Error: SMI busy timeout\n");
5115 } while (smi_reg & MVPP2_SMI_BUSY);
5121 * mpp2_mdio_read - miiphy_read callback function.
5123 * Returns 16bit phy register value, or 0xffff on error
5125 static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
5127 struct mvpp2 *priv = bus->priv;
5131 /* check parameters */
5132 if (addr > MVPP2_PHY_ADDR_MASK) {
5133 printf("Error: Invalid PHY address %d\n", addr);
5137 if (reg > MVPP2_PHY_REG_MASK) {
5138 printf("Err: Invalid register offset %d\n", reg);
5142 /* wait till the SMI is not busy */
5143 if (smi_wait_ready(priv) < 0)
5146 /* fill the phy address and regiser offset and read opcode */
5147 smi_reg = (addr << MVPP2_SMI_DEV_ADDR_OFFS)
5148 | (reg << MVPP2_SMI_REG_ADDR_OFFS)
5149 | MVPP2_SMI_OPCODE_READ;
5151 /* write the smi register */
5152 writel(smi_reg, priv->mdio_base);
5154 /* wait till read value is ready */
5155 timeout = MVPP2_SMI_TIMEOUT;
5158 /* read smi register */
5159 smi_reg = readl(priv->mdio_base);
5160 if (timeout-- == 0) {
5161 printf("Err: SMI read ready timeout\n");
5164 } while (!(smi_reg & MVPP2_SMI_READ_VALID));
5166 /* Wait for the data to update in the SMI register */
5167 for (timeout = 0; timeout < MVPP2_SMI_TIMEOUT; timeout++)
5170 return readl(priv->mdio_base) & MVPP2_SMI_DATA_MASK;
5174 * mpp2_mdio_write - miiphy_write callback function.
5176 * Returns 0 if write succeed, -EINVAL on bad parameters
5179 static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
5182 struct mvpp2 *priv = bus->priv;
5185 /* check parameters */
5186 if (addr > MVPP2_PHY_ADDR_MASK) {
5187 printf("Error: Invalid PHY address %d\n", addr);
5191 if (reg > MVPP2_PHY_REG_MASK) {
5192 printf("Err: Invalid register offset %d\n", reg);
5196 /* wait till the SMI is not busy */
5197 if (smi_wait_ready(priv) < 0)
5200 /* fill the phy addr and reg offset and write opcode and data */
5201 smi_reg = value << MVPP2_SMI_DATA_OFFS;
5202 smi_reg |= (addr << MVPP2_SMI_DEV_ADDR_OFFS)
5203 | (reg << MVPP2_SMI_REG_ADDR_OFFS);
5204 smi_reg &= ~MVPP2_SMI_OPCODE_READ;
5206 /* write the smi register */
5207 writel(smi_reg, priv->mdio_base);
5212 static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
5214 struct mvpp2_port *port = dev_get_priv(dev);
5215 struct mvpp2_rx_desc *rx_desc;
5216 struct mvpp2_bm_pool *bm_pool;
5217 dma_addr_t dma_addr;
5219 int pool, rx_bytes, err;
5221 struct mvpp2_rx_queue *rxq;
5222 u32 cause_rx_tx, cause_rx, cause_misc;
5225 cause_rx_tx = mvpp2_read(port->priv,
5226 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
5227 cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
5228 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
5229 if (!cause_rx_tx && !cause_misc)
5232 cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
5234 /* Process RX packets */
5235 cause_rx |= port->pending_cause_rx;
5236 rxq = mvpp2_get_rx_queue(port, cause_rx);
5238 /* Get number of received packets and clamp the to-do */
5239 rx_received = mvpp2_rxq_received(port, rxq->id);
5241 /* Return if no packets are received */
5245 rx_desc = mvpp2_rxq_next_desc_get(rxq);
5246 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
5247 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
5248 rx_bytes -= MVPP2_MH_SIZE;
5249 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
5251 bm = mvpp2_bm_cookie_build(port, rx_desc);
5252 pool = mvpp2_bm_cookie_pool_get(bm);
5253 bm_pool = &port->priv->bm_pools[pool];
5255 /* In case of an error, release the requested buffer pointer
5256 * to the Buffer Manager. This request process is controlled
5257 * by the hardware, and the information about the buffer is
5258 * comprised by the RX descriptor.
5260 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
5261 mvpp2_rx_error(port, rx_desc);
5262 /* Return the buffer to the pool */
5263 mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
5267 err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
5269 netdev_err(port->dev, "failed to refill BM pools\n");
5273 /* Update Rx queue management counters */
5275 mvpp2_rxq_status_update(port, rxq->id, 1, 1);
5277 /* give packet to stack - skip on first n bytes */
5278 data = (u8 *)dma_addr + 2 + 32;
5284 * No cache invalidation needed here, since the rx_buffer's are
5285 * located in a uncached memory region
5293 static void mvpp2_txq_drain(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
5298 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
5299 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
5301 val |= MVPP2_TXQ_DRAIN_EN_MASK;
5303 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
5304 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
5307 static int mvpp2_send(struct udevice *dev, void *packet, int length)
5309 struct mvpp2_port *port = dev_get_priv(dev);
5310 struct mvpp2_tx_queue *txq, *aggr_txq;
5311 struct mvpp2_tx_desc *tx_desc;
5315 txq = port->txqs[0];
5316 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
5318 /* Get a descriptor for the first part of the packet */
5319 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
5320 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
5321 mvpp2_txdesc_size_set(port, tx_desc, length);
5322 mvpp2_txdesc_offset_set(port, tx_desc,
5323 (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
5324 mvpp2_txdesc_dma_addr_set(port, tx_desc,
5325 (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
5326 /* First and Last descriptor */
5327 mvpp2_txdesc_cmd_set(port, tx_desc,
5328 MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
5329 | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
5332 flush_dcache_range((unsigned long)packet,
5333 (unsigned long)packet + ALIGN(length, PKTALIGN));
5335 /* Enable transmit */
5337 mvpp2_aggr_txq_pend_desc_add(port, 1);
5339 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
5343 if (timeout++ > 10000) {
5344 printf("timeout: packet not sent from aggregated to phys TXQ\n");
5347 tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
5350 /* Enable TXQ drain */
5351 mvpp2_txq_drain(port, txq, 1);
5355 if (timeout++ > 10000) {
5356 printf("timeout: packet not sent\n");
5359 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
5362 /* Disable TXQ drain */
5363 mvpp2_txq_drain(port, txq, 0);
5368 static int mvpp2_start(struct udevice *dev)
5370 struct eth_pdata *pdata = dev_get_platdata(dev);
5371 struct mvpp2_port *port = dev_get_priv(dev);
5373 /* Load current MAC address */
5374 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
5376 /* Reconfigure parser accept the original MAC address */
5377 mvpp2_prs_update_mac_da(port, port->dev_addr);
5379 switch (port->phy_interface) {
5380 case PHY_INTERFACE_MODE_RGMII:
5381 case PHY_INTERFACE_MODE_RGMII_ID:
5382 case PHY_INTERFACE_MODE_SGMII:
5383 mvpp2_port_power_up(port);
5388 mvpp2_open(dev, port);
5393 static void mvpp2_stop(struct udevice *dev)
5395 struct mvpp2_port *port = dev_get_priv(dev);
5397 mvpp2_stop_dev(port);
5398 mvpp2_cleanup_rxqs(port);
5399 mvpp2_cleanup_txqs(port);
5402 static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
5404 writel(port->phyaddr, port->priv->iface_base +
5405 MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
5410 static int mvpp2_base_probe(struct udevice *dev)
5412 struct mvpp2 *priv = dev_get_priv(dev);
5413 struct mii_dev *bus;
5418 /* Save hw-version */
5419 priv->hw_version = dev_get_driver_data(dev);
5422 * U-Boot special buffer handling:
5424 * Allocate buffer area for descs and rx_buffers. This is only
5425 * done once for all interfaces. As only one interface can
5426 * be active. Make this area DMA-safe by disabling the D-cache
5429 /* Align buffer area for descs and rx_buffers to 1MiB */
5430 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
5431 mmu_set_region_dcache_behaviour((unsigned long)bd_space,
5432 BD_SPACE, DCACHE_OFF);
5434 buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
5435 size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
5437 buffer_loc.tx_descs =
5438 (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
5439 size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
5441 buffer_loc.rx_descs =
5442 (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
5443 size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
5445 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
5446 buffer_loc.bm_pool[i] =
5447 (unsigned long *)((unsigned long)bd_space + size);
5448 if (priv->hw_version == MVPP21)
5449 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
5451 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
5454 for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
5455 buffer_loc.rx_buffer[i] =
5456 (unsigned long *)((unsigned long)bd_space + size);
5457 size += RX_BUFFER_SIZE;
5460 /* Clear the complete area so that all descriptors are cleared */
5461 memset(bd_space, 0, size);
5463 /* Save base addresses for later use */
5464 priv->base = (void *)devfdt_get_addr_index(dev, 0);
5465 if (IS_ERR(priv->base))
5466 return PTR_ERR(priv->base);
5468 if (priv->hw_version == MVPP21) {
5469 priv->lms_base = (void *)devfdt_get_addr_index(dev, 1);
5470 if (IS_ERR(priv->lms_base))
5471 return PTR_ERR(priv->lms_base);
5473 priv->mdio_base = priv->lms_base + MVPP21_SMI;
5475 priv->iface_base = (void *)devfdt_get_addr_index(dev, 1);
5476 if (IS_ERR(priv->iface_base))
5477 return PTR_ERR(priv->iface_base);
5479 priv->mdio_base = priv->iface_base + MVPP22_SMI;
5481 /* Store common base addresses for all ports */
5482 priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
5483 priv->xpcs_base = priv->iface_base + MVPP22_XPCS;
5484 priv->rfu1_base = priv->iface_base + MVPP22_RFU1;
5487 if (priv->hw_version == MVPP21)
5488 priv->max_port_rxqs = 8;
5490 priv->max_port_rxqs = 32;
5492 /* Finally create and register the MDIO bus driver */
5495 printf("Failed to allocate MDIO bus\n");
5499 bus->read = mpp2_mdio_read;
5500 bus->write = mpp2_mdio_write;
5501 snprintf(bus->name, sizeof(bus->name), dev->name);
5502 bus->priv = (void *)priv;
5505 return mdio_register(bus);
5508 static int mvpp2_probe(struct udevice *dev)
5510 struct mvpp2_port *port = dev_get_priv(dev);
5511 struct mvpp2 *priv = dev_get_priv(dev->parent);
5514 /* Only call the probe function for the parent once */
5515 if (!priv->probe_done) {
5516 err = mvpp2_base_probe(dev->parent);
5517 priv->probe_done = 1;
5520 port->priv = dev_get_priv(dev->parent);
5522 err = phy_info_parse(dev, port);
5527 * We need the port specific io base addresses at this stage, since
5528 * gop_port_init() accesses these registers
5530 if (priv->hw_version == MVPP21) {
5531 int priv_common_regs_num = 2;
5533 port->base = (void __iomem *)devfdt_get_addr_index(
5534 dev->parent, priv_common_regs_num + port->id);
5535 if (IS_ERR(port->base))
5536 return PTR_ERR(port->base);
5538 port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
5540 if (port->id == -1) {
5541 dev_err(&pdev->dev, "missing gop-port-id value\n");
5545 port->base = priv->iface_base + MVPP22_PORT_BASE +
5546 port->gop_id * MVPP22_PORT_OFFSET;
5548 /* Set phy address of the port */
5550 mvpp22_smi_phy_addr_cfg(port);
5553 gop_port_init(port);
5556 /* Initialize network controller */
5557 err = mvpp2_init(dev, priv);
5559 dev_err(&pdev->dev, "failed to initialize controller\n");
5563 err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
5567 if (priv->hw_version == MVPP22) {
5568 priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id,
5569 port->phy_interface);
5571 /* Netcomplex configurations for all ports */
5572 gop_netc_init(priv, MV_NETC_FIRST_PHASE);
5573 gop_netc_init(priv, MV_NETC_SECOND_PHASE);
5580 * Empty BM pool and stop its activity before the OS is started
5582 static int mvpp2_remove(struct udevice *dev)
5584 struct mvpp2_port *port = dev_get_priv(dev);
5585 struct mvpp2 *priv = port->priv;
5588 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
5589 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
5594 static const struct eth_ops mvpp2_ops = {
5595 .start = mvpp2_start,
5601 static struct driver mvpp2_driver = {
5604 .probe = mvpp2_probe,
5605 .remove = mvpp2_remove,
5607 .priv_auto_alloc_size = sizeof(struct mvpp2_port),
5608 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
5609 .flags = DM_FLAG_ACTIVE_DMA,
5613 * Use a MISC device to bind the n instances (child nodes) of the
5614 * network base controller in UCLASS_ETH.
5616 static int mvpp2_base_bind(struct udevice *parent)
5618 const void *blob = gd->fdt_blob;
5619 int node = dev_of_offset(parent);
5620 struct uclass_driver *drv;
5621 struct udevice *dev;
5622 struct eth_pdata *plat;
5628 /* Lookup eth driver */
5629 drv = lists_uclass_lookup(UCLASS_ETH);
5631 puts("Cannot find eth driver\n");
5635 base_id_add = base_id;
5637 fdt_for_each_subnode(subnode, blob, node) {
5638 /* Increment base_id for all subnodes, also the disabled ones */
5641 /* Skip disabled ports */
5642 if (!fdtdec_get_is_enabled(blob, subnode))
5645 plat = calloc(1, sizeof(*plat));
5649 id = fdtdec_get_int(blob, subnode, "port-id", -1);
5652 name = calloc(1, 16);
5653 sprintf(name, "mvpp2-%d", id);
5655 /* Create child device UCLASS_ETH and bind it */
5656 device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
5657 dev_set_of_offset(dev, subnode);
5663 static const struct udevice_id mvpp2_ids[] = {
5665 .compatible = "marvell,armada-375-pp2",
5669 .compatible = "marvell,armada-7k-pp22",
5675 U_BOOT_DRIVER(mvpp2_base) = {
5676 .name = "mvpp2_base",
5678 .of_match = mvpp2_ids,
5679 .bind = mvpp2_base_bind,
5680 .priv_auto_alloc_size = sizeof(struct mvpp2),