2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
9 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
18 #include <dm/device-internal.h>
25 #include <linux/errno.h>
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/soc.h>
31 #include <linux/compat.h>
32 #include <linux/mbus.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 /* Some linux -> U-Boot compatibility stuff */
37 #define netdev_err(dev, fmt, args...) \
39 #define netdev_warn(dev, fmt, args...) \
41 #define netdev_info(dev, fmt, args...) \
43 #define netdev_dbg(dev, fmt, args...) \
46 #define ETH_ALEN 6 /* Octets in one ethernet addr */
48 #define __verify_pcpu_ptr(ptr) \
50 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
54 #define VERIFY_PERCPU_PTR(__p) \
56 __verify_pcpu_ptr(__p); \
57 (typeof(*(__p)) __kernel __force *)(__p); \
60 #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
61 #define smp_processor_id() 0
62 #define num_present_cpus() 1
63 #define for_each_present_cpu(cpu) \
64 for ((cpu) = 0; (cpu) < 1; (cpu)++)
66 #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
68 #define CONFIG_NR_CPUS 1
69 #define ETH_HLEN ETHER_HDR_SIZE /* Total octets in header */
71 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
72 #define WRAP (2 + ETH_HLEN + 4 + 32)
74 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
76 #define MVPP2_SMI_TIMEOUT 10000
78 /* RX Fifo Registers */
79 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
80 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
81 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
82 #define MVPP2_RX_FIFO_INIT_REG 0x64
84 /* RX DMA Top Registers */
85 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
86 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
87 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
88 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
89 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
90 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
91 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
92 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
93 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
94 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
95 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
96 #define MVPP2_RXQ_POOL_LONG_OFFS 24
97 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
98 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
99 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
100 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
101 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
103 /* Parser Registers */
104 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
105 #define MVPP2_PRS_PORT_LU_MAX 0xf
106 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
107 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
108 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
109 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
110 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
111 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
112 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
113 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
114 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
115 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
116 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
117 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
118 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
119 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
120 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
122 /* Classifier Registers */
123 #define MVPP2_CLS_MODE_REG 0x1800
124 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
125 #define MVPP2_CLS_PORT_WAY_REG 0x1810
126 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
127 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
128 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
129 #define MVPP2_CLS_LKP_TBL_REG 0x1818
130 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
131 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
132 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
133 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
134 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
135 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
136 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
137 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
138 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
139 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
140 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
141 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
143 /* Descriptor Manager Top Registers */
144 #define MVPP2_RXQ_NUM_REG 0x2040
145 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
146 #define MVPP22_DESC_ADDR_OFFS 8
147 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
148 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
149 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
150 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
151 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
152 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
153 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
154 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
155 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
156 #define MVPP2_RXQ_THRESH_REG 0x204c
157 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
158 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
159 #define MVPP2_RXQ_INDEX_REG 0x2050
160 #define MVPP2_TXQ_NUM_REG 0x2080
161 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
162 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
163 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
164 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
165 #define MVPP2_TXQ_THRESH_REG 0x2094
166 #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
167 #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
168 #define MVPP2_TXQ_INDEX_REG 0x2098
169 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
170 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
171 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
172 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
173 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
174 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
175 #define MVPP2_TXQ_PENDING_REG 0x20a0
176 #define MVPP2_TXQ_PENDING_MASK 0x3fff
177 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
178 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
179 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
180 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
181 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
182 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
183 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
184 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
185 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
186 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
187 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
188 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
189 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
190 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
191 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
192 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
193 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
195 /* MBUS bridge registers */
196 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
197 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
198 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
199 #define MVPP2_BASE_ADDR_ENABLE 0x4060
201 /* AXI Bridge Registers */
202 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
203 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
204 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
205 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
206 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
207 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
208 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
209 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
210 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
211 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
212 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
213 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
215 /* Values for AXI Bridge registers */
216 #define MVPP22_AXI_ATTR_CACHE_OFFS 0
217 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
219 #define MVPP22_AXI_CODE_CACHE_OFFS 0
220 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4
222 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
223 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
224 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
226 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
227 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
229 /* Interrupt Cause and Mask registers */
230 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
231 #define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
233 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
234 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
235 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
236 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
238 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
239 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
241 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
242 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
243 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
244 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
246 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
247 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
248 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
249 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
250 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
251 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
252 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
253 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
254 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
255 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
256 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
257 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
258 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
259 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
260 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
261 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
262 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
263 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
265 /* Buffer Manager registers */
266 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
267 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
268 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
269 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
270 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
271 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
272 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
273 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
274 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
275 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
276 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
277 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
278 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
279 #define MVPP2_BM_START_MASK BIT(0)
280 #define MVPP2_BM_STOP_MASK BIT(1)
281 #define MVPP2_BM_STATE_MASK BIT(4)
282 #define MVPP2_BM_LOW_THRESH_OFFS 8
283 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
284 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
285 MVPP2_BM_LOW_THRESH_OFFS)
286 #define MVPP2_BM_HIGH_THRESH_OFFS 16
287 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
288 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
289 MVPP2_BM_HIGH_THRESH_OFFS)
290 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
291 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
292 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
293 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
294 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
295 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
296 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
297 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
298 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
299 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
300 #define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
301 #define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
302 #define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
303 #define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
304 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
305 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
306 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
307 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
308 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
309 #define MVPP21_BM_MC_RLS_REG 0x64c4
310 #define MVPP2_BM_MC_ID_MASK 0xfff
311 #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
312 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
313 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
314 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
315 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
316 #define MVPP22_BM_MC_RLS_REG 0x64d4
318 /* TX Scheduler registers */
319 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
320 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
321 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
322 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
323 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
324 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
325 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
326 #define MVPP2_TXP_MTU_MAX 0x7FFFF
327 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
328 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
329 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
330 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
331 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
332 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
333 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
334 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
335 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
336 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
337 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
338 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
339 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
340 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
342 /* TX general registers */
343 #define MVPP2_TX_SNOOP_REG 0x8800
344 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
345 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
348 #define MVPP2_SRC_ADDR_MIDDLE 0x24
349 #define MVPP2_SRC_ADDR_HIGH 0x28
350 #define MVPP2_PHY_AN_CFG0_REG 0x34
351 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
352 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
353 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
355 /* Per-port registers */
356 #define MVPP2_GMAC_CTRL_0_REG 0x0
357 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
358 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
359 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
360 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
361 #define MVPP2_GMAC_CTRL_1_REG 0x4
362 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
363 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
364 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
365 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
366 #define MVPP2_GMAC_SA_LOW_OFFS 7
367 #define MVPP2_GMAC_CTRL_2_REG 0x8
368 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
369 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
370 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
371 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
372 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
373 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
374 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
375 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
376 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
377 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
378 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
379 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
380 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
381 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
382 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
383 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
384 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
385 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
387 #define MVPP22_SMI_MISC_CFG_REG 0x1204
388 #define MVPP22_SMI_POLLING_EN BIT(10)
390 #define MVPP22_PORT_BASE 0x30e00
391 #define MVPP22_PORT_OFFSET 0x1000
393 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
395 /* Descriptor ring Macros */
396 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
397 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
399 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
400 #define MVPP2_SMI 0x0054
401 #define MVPP2_PHY_REG_MASK 0x1f
402 /* SMI register fields */
403 #define MVPP2_SMI_DATA_OFFS 0 /* Data */
404 #define MVPP2_SMI_DATA_MASK (0xffff << MVPP2_SMI_DATA_OFFS)
405 #define MVPP2_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
406 #define MVPP2_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
407 #define MVPP2_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
408 #define MVPP2_SMI_OPCODE_READ (1 << MVPP2_SMI_OPCODE_OFFS)
409 #define MVPP2_SMI_READ_VALID (1 << 27) /* Read Valid */
410 #define MVPP2_SMI_BUSY (1 << 28) /* Busy */
412 #define MVPP2_PHY_ADDR_MASK 0x1f
413 #define MVPP2_PHY_REG_MASK 0x1f
415 /* Various constants */
418 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
419 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
420 #define MVPP2_RX_COAL_PKTS 32
421 #define MVPP2_RX_COAL_USEC 100
423 /* The two bytes Marvell header. Either contains a special value used
424 * by Marvell switches when a specific hardware mode is enabled (not
425 * supported by this driver) or is filled automatically by zeroes on
426 * the RX side. Those two bytes being at the front of the Ethernet
427 * header, they allow to have the IP header aligned on a 4 bytes
428 * boundary automatically: the hardware skips those two bytes on its
431 #define MVPP2_MH_SIZE 2
432 #define MVPP2_ETH_TYPE_LEN 2
433 #define MVPP2_PPPOE_HDR_SIZE 8
434 #define MVPP2_VLAN_TAG_LEN 4
436 /* Lbtd 802.3 type */
437 #define MVPP2_IP_LBDT_TYPE 0xfffa
439 #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
440 #define MVPP2_TX_CSUM_MAX_SIZE 9800
442 /* Timeout constants */
443 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
444 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
446 #define MVPP2_TX_MTU_MAX 0x7ffff
448 /* Maximum number of T-CONTs of PON port */
449 #define MVPP2_MAX_TCONT 16
451 /* Maximum number of supported ports */
452 #define MVPP2_MAX_PORTS 4
454 /* Maximum number of TXQs used by single port */
455 #define MVPP2_MAX_TXQ 8
457 /* Default number of TXQs in use */
458 #define MVPP2_DEFAULT_TXQ 1
460 /* Dfault number of RXQs in use */
461 #define MVPP2_DEFAULT_RXQ 1
462 #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
464 /* Max number of Rx descriptors */
465 #define MVPP2_MAX_RXD 16
467 /* Max number of Tx descriptors */
468 #define MVPP2_MAX_TXD 16
470 /* Amount of Tx descriptors that can be reserved at once by CPU */
471 #define MVPP2_CPU_DESC_CHUNK 64
473 /* Max number of Tx descriptors in each aggregated queue */
474 #define MVPP2_AGGR_TXQ_SIZE 256
476 /* Descriptor aligned size */
477 #define MVPP2_DESC_ALIGNED_SIZE 32
479 /* Descriptor alignment mask */
480 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
482 /* RX FIFO constants */
483 #define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000
484 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80
485 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
487 /* RX buffer constants */
488 #define MVPP2_SKB_SHINFO_SIZE \
491 #define MVPP2_RX_PKT_SIZE(mtu) \
492 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
493 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
495 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
496 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
497 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
498 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
500 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
502 /* IPv6 max L3 address size */
503 #define MVPP2_MAX_L3_ADDR_SIZE 16
506 #define MVPP2_F_LOOPBACK BIT(0)
508 /* Marvell tag types */
509 enum mvpp2_tag_type {
510 MVPP2_TAG_TYPE_NONE = 0,
511 MVPP2_TAG_TYPE_MH = 1,
512 MVPP2_TAG_TYPE_DSA = 2,
513 MVPP2_TAG_TYPE_EDSA = 3,
514 MVPP2_TAG_TYPE_VLAN = 4,
515 MVPP2_TAG_TYPE_LAST = 5
518 /* Parser constants */
519 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
520 #define MVPP2_PRS_TCAM_WORDS 6
521 #define MVPP2_PRS_SRAM_WORDS 4
522 #define MVPP2_PRS_FLOW_ID_SIZE 64
523 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
524 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
525 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
526 #define MVPP2_PRS_IPV4_HEAD 0x40
527 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
528 #define MVPP2_PRS_IPV4_MC 0xe0
529 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
530 #define MVPP2_PRS_IPV4_BC_MASK 0xff
531 #define MVPP2_PRS_IPV4_IHL 0x5
532 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
533 #define MVPP2_PRS_IPV6_MC 0xff
534 #define MVPP2_PRS_IPV6_MC_MASK 0xff
535 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
536 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
537 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
538 #define MVPP2_PRS_DBL_VLANS_MAX 100
541 * - lookup ID - 4 bits
543 * - additional information - 1 byte
544 * - header data - 8 bytes
545 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
547 #define MVPP2_PRS_AI_BITS 8
548 #define MVPP2_PRS_PORT_MASK 0xff
549 #define MVPP2_PRS_LU_MASK 0xf
550 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
551 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
552 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
553 (((offs) * 2) - ((offs) % 2) + 2)
554 #define MVPP2_PRS_TCAM_AI_BYTE 16
555 #define MVPP2_PRS_TCAM_PORT_BYTE 17
556 #define MVPP2_PRS_TCAM_LU_BYTE 20
557 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
558 #define MVPP2_PRS_TCAM_INV_WORD 5
559 /* Tcam entries ID */
560 #define MVPP2_PE_DROP_ALL 0
561 #define MVPP2_PE_FIRST_FREE_TID 1
562 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
563 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
564 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
565 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
566 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
567 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
568 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
569 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
570 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
571 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
572 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
573 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
574 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
575 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
576 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
577 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
578 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
579 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
580 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
581 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
582 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
583 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
584 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
585 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
586 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
589 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
591 #define MVPP2_PRS_SRAM_RI_OFFS 0
592 #define MVPP2_PRS_SRAM_RI_WORD 0
593 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
594 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
595 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
596 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
597 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
598 #define MVPP2_PRS_SRAM_UDF_OFFS 73
599 #define MVPP2_PRS_SRAM_UDF_BITS 8
600 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
601 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
602 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
603 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
604 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
605 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
606 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
607 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
608 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
609 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
610 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
611 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
612 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
613 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
614 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
615 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
616 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
617 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
618 #define MVPP2_PRS_SRAM_AI_OFFS 90
619 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
620 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
621 #define MVPP2_PRS_SRAM_AI_MASK 0xff
622 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
623 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
624 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
625 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
627 /* Sram result info bits assignment */
628 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
629 #define MVPP2_PRS_RI_DSA_MASK 0x2
630 #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
631 #define MVPP2_PRS_RI_VLAN_NONE 0x0
632 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
633 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
634 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
635 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
636 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
637 #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
638 #define MVPP2_PRS_RI_L2_UCAST 0x0
639 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
640 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
641 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
642 #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
643 #define MVPP2_PRS_RI_L3_UN 0x0
644 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
645 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
646 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
647 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
648 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
649 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
650 #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
651 #define MVPP2_PRS_RI_L3_UCAST 0x0
652 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
653 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
654 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
655 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
656 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
657 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
658 #define MVPP2_PRS_RI_L4_TCP BIT(22)
659 #define MVPP2_PRS_RI_L4_UDP BIT(23)
660 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
661 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
662 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
663 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
665 /* Sram additional info bits assignment */
666 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
667 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
668 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
669 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
670 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
671 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
672 #define MVPP2_PRS_SINGLE_VLAN_AI 0
673 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
676 #define MVPP2_PRS_TAGGED true
677 #define MVPP2_PRS_UNTAGGED false
678 #define MVPP2_PRS_EDSA true
679 #define MVPP2_PRS_DSA false
681 /* MAC entries, shadow udf */
683 MVPP2_PRS_UDF_MAC_DEF,
684 MVPP2_PRS_UDF_MAC_RANGE,
685 MVPP2_PRS_UDF_L2_DEF,
686 MVPP2_PRS_UDF_L2_DEF_COPY,
687 MVPP2_PRS_UDF_L2_USER,
691 enum mvpp2_prs_lookup {
705 enum mvpp2_prs_l3_cast {
706 MVPP2_PRS_L3_UNI_CAST,
707 MVPP2_PRS_L3_MULTI_CAST,
708 MVPP2_PRS_L3_BROAD_CAST
711 /* Classifier constants */
712 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
713 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
714 #define MVPP2_CLS_LKP_TBL_SIZE 64
717 #define MVPP2_BM_POOLS_NUM 1
718 #define MVPP2_BM_LONG_BUF_NUM 16
719 #define MVPP2_BM_SHORT_BUF_NUM 16
720 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
721 #define MVPP2_BM_POOL_PTR_ALIGN 128
722 #define MVPP2_BM_SWF_LONG_POOL(port) 0
724 /* BM cookie (32 bits) definition */
725 #define MVPP2_BM_COOKIE_POOL_OFFS 8
726 #define MVPP2_BM_COOKIE_CPU_OFFS 24
728 /* BM short pool packet size
729 * These value assure that for SWF the total number
730 * of bytes allocated for each buffer will be 512
732 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
742 /* Shared Packet Processor resources */
744 /* Shared registers' base addresses */
746 void __iomem *lms_base;
747 void __iomem *iface_base;
749 /* List of pointers to port structures */
750 struct mvpp2_port **port_list;
752 /* Aggregated TXQs */
753 struct mvpp2_tx_queue *aggr_txqs;
756 struct mvpp2_bm_pool *bm_pools;
758 /* PRS shadow table */
759 struct mvpp2_prs_shadow *prs_shadow;
760 /* PRS auxiliary table for double vlan entries control */
761 bool *prs_double_vlans;
767 enum { MVPP21, MVPP22 } hw_version;
769 /* Maximum number of RXQs per port */
770 unsigned int max_port_rxqs;
775 struct mvpp2_pcpu_stats {
785 /* Index of the port from the "group of ports" complex point
794 /* Per-port registers' base address */
797 struct mvpp2_rx_queue **rxqs;
798 struct mvpp2_tx_queue **txqs;
802 u32 pending_cause_rx;
804 /* Per-CPU port control */
805 struct mvpp2_port_pcpu __percpu *pcpu;
812 struct mvpp2_pcpu_stats __percpu *stats;
814 struct phy_device *phy_dev;
815 phy_interface_t phy_interface;
823 struct mvpp2_bm_pool *pool_long;
824 struct mvpp2_bm_pool *pool_short;
826 /* Index of first port's physical RXQ */
829 u8 dev_addr[ETH_ALEN];
832 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
833 * layout of the transmit and reception DMA descriptors, and their
834 * layout is therefore defined by the hardware design
837 #define MVPP2_TXD_L3_OFF_SHIFT 0
838 #define MVPP2_TXD_IP_HLEN_SHIFT 8
839 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
840 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
841 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
842 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
843 #define MVPP2_TXD_L4_UDP BIT(24)
844 #define MVPP2_TXD_L3_IP6 BIT(26)
845 #define MVPP2_TXD_L_DESC BIT(28)
846 #define MVPP2_TXD_F_DESC BIT(29)
848 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
849 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
850 #define MVPP2_RXD_ERR_CRC 0x0
851 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
852 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
853 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
854 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
855 #define MVPP2_RXD_HWF_SYNC BIT(21)
856 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
857 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
858 #define MVPP2_RXD_L4_TCP BIT(25)
859 #define MVPP2_RXD_L4_UDP BIT(26)
860 #define MVPP2_RXD_L3_IP4 BIT(28)
861 #define MVPP2_RXD_L3_IP6 BIT(30)
862 #define MVPP2_RXD_BUF_HDR BIT(31)
864 /* HW TX descriptor for PPv2.1 */
865 struct mvpp21_tx_desc {
866 u32 command; /* Options used by HW for packet transmitting.*/
867 u8 packet_offset; /* the offset from the buffer beginning */
868 u8 phys_txq; /* destination queue ID */
869 u16 data_size; /* data size of transmitted packet in bytes */
870 u32 buf_dma_addr; /* physical addr of transmitted buffer */
871 u32 buf_cookie; /* cookie for access to TX buffer in tx path */
872 u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
873 u32 reserved2; /* reserved (for future use) */
876 /* HW RX descriptor for PPv2.1 */
877 struct mvpp21_rx_desc {
878 u32 status; /* info about received packet */
879 u16 reserved1; /* parser_info (for future use, PnC) */
880 u16 data_size; /* size of received packet in bytes */
881 u32 buf_dma_addr; /* physical address of the buffer */
882 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
883 u16 reserved2; /* gem_port_id (for future use, PON) */
884 u16 reserved3; /* csum_l4 (for future use, PnC) */
885 u8 reserved4; /* bm_qset (for future use, BM) */
887 u16 reserved6; /* classify_info (for future use, PnC) */
888 u32 reserved7; /* flow_id (for future use, PnC) */
892 /* HW TX descriptor for PPv2.2 */
893 struct mvpp22_tx_desc {
899 u64 buf_dma_addr_ptp;
903 /* HW RX descriptor for PPv2.2 */
904 struct mvpp22_rx_desc {
910 u64 buf_dma_addr_key_hash;
914 /* Opaque type used by the driver to manipulate the HW TX and RX
917 struct mvpp2_tx_desc {
919 struct mvpp21_tx_desc pp21;
920 struct mvpp22_tx_desc pp22;
924 struct mvpp2_rx_desc {
926 struct mvpp21_rx_desc pp21;
927 struct mvpp22_rx_desc pp22;
931 /* Per-CPU Tx queue control */
932 struct mvpp2_txq_pcpu {
935 /* Number of Tx DMA descriptors in the descriptor ring */
938 /* Number of currently used Tx DMA descriptor in the
943 /* Number of Tx DMA descriptors reserved for each CPU */
946 /* Index of last TX DMA descriptor that was inserted */
949 /* Index of the TX DMA descriptor to be cleaned up */
953 struct mvpp2_tx_queue {
954 /* Physical number of this Tx queue */
957 /* Logical number of this Tx queue */
960 /* Number of Tx DMA descriptors in the descriptor ring */
963 /* Number of currently used Tx DMA descriptor in the descriptor ring */
966 /* Per-CPU control of physical Tx queues */
967 struct mvpp2_txq_pcpu __percpu *pcpu;
971 /* Virtual address of thex Tx DMA descriptors array */
972 struct mvpp2_tx_desc *descs;
974 /* DMA address of the Tx DMA descriptors array */
975 dma_addr_t descs_dma;
977 /* Index of the last Tx DMA descriptor */
980 /* Index of the next Tx DMA descriptor to process */
981 int next_desc_to_proc;
984 struct mvpp2_rx_queue {
985 /* RX queue number, in the range 0-31 for physical RXQs */
988 /* Num of rx descriptors in the rx descriptor ring */
994 /* Virtual address of the RX DMA descriptors array */
995 struct mvpp2_rx_desc *descs;
997 /* DMA address of the RX DMA descriptors array */
998 dma_addr_t descs_dma;
1000 /* Index of the last RX DMA descriptor */
1003 /* Index of the next RX DMA descriptor to process */
1004 int next_desc_to_proc;
1006 /* ID of port to which physical RXQ is mapped */
1009 /* Port's logic RXQ number to which physical RXQ is mapped */
1013 union mvpp2_prs_tcam_entry {
1014 u32 word[MVPP2_PRS_TCAM_WORDS];
1015 u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
1018 union mvpp2_prs_sram_entry {
1019 u32 word[MVPP2_PRS_SRAM_WORDS];
1020 u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
1023 struct mvpp2_prs_entry {
1025 union mvpp2_prs_tcam_entry tcam;
1026 union mvpp2_prs_sram_entry sram;
1029 struct mvpp2_prs_shadow {
1036 /* User defined offset */
1044 struct mvpp2_cls_flow_entry {
1046 u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
1049 struct mvpp2_cls_lookup_entry {
1055 struct mvpp2_bm_pool {
1056 /* Pool number in the range 0-7 */
1058 enum mvpp2_bm_type type;
1060 /* Buffer Pointers Pool External (BPPE) size */
1062 /* Number of buffers for this pool */
1064 /* Pool buffer size */
1069 /* BPPE virtual base address */
1070 unsigned long *virt_addr;
1071 /* BPPE DMA base address */
1072 dma_addr_t dma_addr;
1074 /* Ports using BM pool */
1077 /* Occupied buffers indicator */
1081 /* Static declaractions */
1083 /* Number of RXQs used by single port */
1084 static int rxq_number = MVPP2_DEFAULT_RXQ;
1085 /* Number of TXQs used by single port */
1086 static int txq_number = MVPP2_DEFAULT_TXQ;
1088 #define MVPP2_DRIVER_NAME "mvpp2"
1089 #define MVPP2_DRIVER_VERSION "1.0"
1092 * U-Boot internal data, mostly uncached buffers for descriptors and data
1094 struct buffer_location {
1095 struct mvpp2_tx_desc *aggr_tx_descs;
1096 struct mvpp2_tx_desc *tx_descs;
1097 struct mvpp2_rx_desc *rx_descs;
1098 unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
1099 unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
1104 * All 4 interfaces use the same global buffer, since only one interface
1105 * can be enabled at once
1107 static struct buffer_location buffer_loc;
1110 * Page table entries are set to 1MB, or multiples of 1MB
1111 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
1113 #define BD_SPACE (1 << 20)
1115 /* Utility/helper methods */
1117 static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
1119 writel(data, priv->base + offset);
1122 static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
1124 return readl(priv->base + offset);
1127 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
1128 struct mvpp2_tx_desc *tx_desc,
1129 dma_addr_t dma_addr)
1131 if (port->priv->hw_version == MVPP21) {
1132 tx_desc->pp21.buf_dma_addr = dma_addr;
1134 u64 val = (u64)dma_addr;
1136 tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
1137 tx_desc->pp22.buf_dma_addr_ptp |= val;
1141 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
1142 struct mvpp2_tx_desc *tx_desc,
1145 if (port->priv->hw_version == MVPP21)
1146 tx_desc->pp21.data_size = size;
1148 tx_desc->pp22.data_size = size;
1151 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
1152 struct mvpp2_tx_desc *tx_desc,
1155 if (port->priv->hw_version == MVPP21)
1156 tx_desc->pp21.phys_txq = txq;
1158 tx_desc->pp22.phys_txq = txq;
1161 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
1162 struct mvpp2_tx_desc *tx_desc,
1163 unsigned int command)
1165 if (port->priv->hw_version == MVPP21)
1166 tx_desc->pp21.command = command;
1168 tx_desc->pp22.command = command;
1171 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
1172 struct mvpp2_tx_desc *tx_desc,
1173 unsigned int offset)
1175 if (port->priv->hw_version == MVPP21)
1176 tx_desc->pp21.packet_offset = offset;
1178 tx_desc->pp22.packet_offset = offset;
1181 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
1182 struct mvpp2_rx_desc *rx_desc)
1184 if (port->priv->hw_version == MVPP21)
1185 return rx_desc->pp21.buf_dma_addr;
1187 return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
1190 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
1191 struct mvpp2_rx_desc *rx_desc)
1193 if (port->priv->hw_version == MVPP21)
1194 return rx_desc->pp21.buf_cookie;
1196 return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
1199 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
1200 struct mvpp2_rx_desc *rx_desc)
1202 if (port->priv->hw_version == MVPP21)
1203 return rx_desc->pp21.data_size;
1205 return rx_desc->pp22.data_size;
1208 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
1209 struct mvpp2_rx_desc *rx_desc)
1211 if (port->priv->hw_version == MVPP21)
1212 return rx_desc->pp21.status;
1214 return rx_desc->pp22.status;
1217 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
1219 txq_pcpu->txq_get_index++;
1220 if (txq_pcpu->txq_get_index == txq_pcpu->size)
1221 txq_pcpu->txq_get_index = 0;
1224 /* Get number of physical egress port */
1225 static inline int mvpp2_egress_port(struct mvpp2_port *port)
1227 return MVPP2_MAX_TCONT + port->id;
1230 /* Get number of physical TXQ */
1231 static inline int mvpp2_txq_phys(int port, int txq)
1233 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
1236 /* Parser configuration routines */
1238 /* Update parser tcam and sram hw entries */
1239 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1243 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1246 /* Clear entry invalidation bit */
1247 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1249 /* Write tcam index - indirect access */
1250 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1251 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1252 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1254 /* Write sram index - indirect access */
1255 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1256 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1257 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1262 /* Read tcam entry from hw */
1263 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1267 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1270 /* Write tcam index - indirect access */
1271 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1273 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
1274 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
1275 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
1276 return MVPP2_PRS_TCAM_ENTRY_INVALID;
1278 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1279 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
1281 /* Write sram index - indirect access */
1282 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1283 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1284 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
1289 /* Invalidate tcam hw entry */
1290 static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
1292 /* Write index - indirect access */
1293 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1294 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
1295 MVPP2_PRS_TCAM_INV_MASK);
1298 /* Enable shadow table entry and set its lookup ID */
1299 static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
1301 priv->prs_shadow[index].valid = true;
1302 priv->prs_shadow[index].lu = lu;
1305 /* Update ri fields in shadow table entry */
1306 static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
1307 unsigned int ri, unsigned int ri_mask)
1309 priv->prs_shadow[index].ri_mask = ri_mask;
1310 priv->prs_shadow[index].ri = ri;
1313 /* Update lookup field in tcam sw entry */
1314 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
1316 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
1318 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
1319 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
1322 /* Update mask for single port in tcam sw entry */
1323 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
1324 unsigned int port, bool add)
1326 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1329 pe->tcam.byte[enable_off] &= ~(1 << port);
1331 pe->tcam.byte[enable_off] |= 1 << port;
1334 /* Update port map in tcam sw entry */
1335 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
1338 unsigned char port_mask = MVPP2_PRS_PORT_MASK;
1339 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1341 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
1342 pe->tcam.byte[enable_off] &= ~port_mask;
1343 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
1346 /* Obtain port map from tcam sw entry */
1347 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
1349 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1351 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
1354 /* Set byte of data and its enable bits in tcam sw entry */
1355 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
1356 unsigned int offs, unsigned char byte,
1357 unsigned char enable)
1359 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
1360 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
1363 /* Get byte of data and its enable bits from tcam sw entry */
1364 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
1365 unsigned int offs, unsigned char *byte,
1366 unsigned char *enable)
1368 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
1369 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
1372 /* Set ethertype in tcam sw entry */
1373 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
1374 unsigned short ethertype)
1376 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
1377 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
1380 /* Set bits in sram sw entry */
1381 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
1384 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
1387 /* Clear bits in sram sw entry */
1388 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
1391 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
1394 /* Update ri bits in sram sw entry */
1395 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
1396 unsigned int bits, unsigned int mask)
1400 for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
1401 int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
1403 if (!(mask & BIT(i)))
1407 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
1409 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
1411 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
1415 /* Update ai bits in sram sw entry */
1416 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
1417 unsigned int bits, unsigned int mask)
1420 int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
1422 for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
1424 if (!(mask & BIT(i)))
1428 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
1430 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
1432 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
1436 /* Read ai bits from sram sw entry */
1437 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
1440 int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
1441 int ai_en_off = ai_off + 1;
1442 int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
1444 bits = (pe->sram.byte[ai_off] >> ai_shift) |
1445 (pe->sram.byte[ai_en_off] << (8 - ai_shift));
1450 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1453 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
1456 int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
1458 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
1459 MVPP2_PRS_SRAM_NEXT_LU_MASK);
1460 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
1463 /* In the sram sw entry set sign and value of the next lookup offset
1464 * and the offset value generated to the classifier
1466 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
1471 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1474 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1478 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
1479 (unsigned char)shift;
1481 /* Reset and set operation */
1482 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
1483 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
1484 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
1486 /* Set base offset as current */
1487 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1490 /* In the sram sw entry set sign and value of the user defined offset
1491 * generated to the classifier
1493 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
1494 unsigned int type, int offset,
1499 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1500 offset = 0 - offset;
1502 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1506 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
1507 MVPP2_PRS_SRAM_UDF_MASK);
1508 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
1509 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1510 MVPP2_PRS_SRAM_UDF_BITS)] &=
1511 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1512 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1513 MVPP2_PRS_SRAM_UDF_BITS)] |=
1514 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1516 /* Set offset type */
1517 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
1518 MVPP2_PRS_SRAM_UDF_TYPE_MASK);
1519 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
1521 /* Set offset operation */
1522 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
1523 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
1524 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
1526 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1527 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
1528 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
1529 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1531 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1532 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
1533 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1535 /* Set base offset as current */
1536 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1539 /* Find parser flow entry */
1540 static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
1542 struct mvpp2_prs_entry *pe;
1545 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1548 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
1550 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1551 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
1554 if (!priv->prs_shadow[tid].valid ||
1555 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
1559 mvpp2_prs_hw_read(priv, pe);
1560 bits = mvpp2_prs_sram_ai_get(pe);
1562 /* Sram store classification lookup ID in AI bits [5:0] */
1563 if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
1571 /* Return first free tcam index, seeking from start to end */
1572 static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
1580 if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
1581 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
1583 for (tid = start; tid <= end; tid++) {
1584 if (!priv->prs_shadow[tid].valid)
1591 /* Enable/disable dropping all mac da's */
1592 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
1594 struct mvpp2_prs_entry pe;
1596 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
1597 /* Entry exist - update port only */
1598 pe.index = MVPP2_PE_DROP_ALL;
1599 mvpp2_prs_hw_read(priv, &pe);
1601 /* Entry doesn't exist - create new */
1602 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1603 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1604 pe.index = MVPP2_PE_DROP_ALL;
1606 /* Non-promiscuous mode for all ports - DROP unknown packets */
1607 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1608 MVPP2_PRS_RI_DROP_MASK);
1610 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1611 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1613 /* Update shadow table */
1614 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1616 /* Mask all ports */
1617 mvpp2_prs_tcam_port_map_set(&pe, 0);
1620 /* Update port mask */
1621 mvpp2_prs_tcam_port_set(&pe, port, add);
1623 mvpp2_prs_hw_write(priv, &pe);
1626 /* Set port to promiscuous mode */
1627 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
1629 struct mvpp2_prs_entry pe;
1631 /* Promiscuous mode - Accept unknown packets */
1633 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
1634 /* Entry exist - update port only */
1635 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1636 mvpp2_prs_hw_read(priv, &pe);
1638 /* Entry doesn't exist - create new */
1639 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1640 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1641 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1643 /* Continue - set next lookup */
1644 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1646 /* Set result info bits */
1647 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
1648 MVPP2_PRS_RI_L2_CAST_MASK);
1650 /* Shift to ethertype */
1651 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1652 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1654 /* Mask all ports */
1655 mvpp2_prs_tcam_port_map_set(&pe, 0);
1657 /* Update shadow table */
1658 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1661 /* Update port mask */
1662 mvpp2_prs_tcam_port_set(&pe, port, add);
1664 mvpp2_prs_hw_write(priv, &pe);
1667 /* Accept multicast */
1668 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
1671 struct mvpp2_prs_entry pe;
1672 unsigned char da_mc;
1674 /* Ethernet multicast address first byte is
1675 * 0x01 for IPv4 and 0x33 for IPv6
1677 da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
1679 if (priv->prs_shadow[index].valid) {
1680 /* Entry exist - update port only */
1682 mvpp2_prs_hw_read(priv, &pe);
1684 /* Entry doesn't exist - create new */
1685 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1686 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1689 /* Continue - set next lookup */
1690 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1692 /* Set result info bits */
1693 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
1694 MVPP2_PRS_RI_L2_CAST_MASK);
1696 /* Update tcam entry data first byte */
1697 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
1699 /* Shift to ethertype */
1700 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1701 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1703 /* Mask all ports */
1704 mvpp2_prs_tcam_port_map_set(&pe, 0);
1706 /* Update shadow table */
1707 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1710 /* Update port mask */
1711 mvpp2_prs_tcam_port_set(&pe, port, add);
1713 mvpp2_prs_hw_write(priv, &pe);
1716 /* Parser per-port initialization */
1717 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
1718 int lu_max, int offset)
1723 val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
1724 val &= ~MVPP2_PRS_PORT_LU_MASK(port);
1725 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
1726 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
1728 /* Set maximum number of loops for packet received from port */
1729 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
1730 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
1731 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
1732 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
1734 /* Set initial offset for packet header extraction for the first
1737 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
1738 val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
1739 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
1740 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
1743 /* Default flow entries initialization for all ports */
1744 static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
1746 struct mvpp2_prs_entry pe;
1749 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
1750 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1751 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1752 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
1754 /* Mask all ports */
1755 mvpp2_prs_tcam_port_map_set(&pe, 0);
1758 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
1759 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
1761 /* Update shadow table and hw entry */
1762 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
1763 mvpp2_prs_hw_write(priv, &pe);
1767 /* Set default entry for Marvell Header field */
1768 static void mvpp2_prs_mh_init(struct mvpp2 *priv)
1770 struct mvpp2_prs_entry pe;
1772 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1774 pe.index = MVPP2_PE_MH_DEFAULT;
1775 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1776 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1777 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1778 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
1780 /* Unmask all ports */
1781 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1783 /* Update shadow table and hw entry */
1784 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1785 mvpp2_prs_hw_write(priv, &pe);
1788 /* Set default entires (place holder) for promiscuous, non-promiscuous and
1789 * multicast MAC addresses
1791 static void mvpp2_prs_mac_init(struct mvpp2 *priv)
1793 struct mvpp2_prs_entry pe;
1795 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1797 /* Non-promiscuous mode for all ports - DROP unknown packets */
1798 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
1799 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1801 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1802 MVPP2_PRS_RI_DROP_MASK);
1803 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1804 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1806 /* Unmask all ports */
1807 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1809 /* Update shadow table and hw entry */
1810 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1811 mvpp2_prs_hw_write(priv, &pe);
1813 /* place holders only - no ports */
1814 mvpp2_prs_mac_drop_all_set(priv, 0, false);
1815 mvpp2_prs_mac_promisc_set(priv, 0, false);
1816 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
1817 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
1820 /* Match basic ethertypes */
1821 static int mvpp2_prs_etype_init(struct mvpp2 *priv)
1823 struct mvpp2_prs_entry pe;
1826 /* Ethertype: PPPoE */
1827 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1828 MVPP2_PE_LAST_FREE_TID);
1832 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1833 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1836 mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
1838 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
1839 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1840 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1841 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
1842 MVPP2_PRS_RI_PPPOE_MASK);
1844 /* Update shadow table and hw entry */
1845 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1846 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1847 priv->prs_shadow[pe.index].finish = false;
1848 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
1849 MVPP2_PRS_RI_PPPOE_MASK);
1850 mvpp2_prs_hw_write(priv, &pe);
1852 /* Ethertype: ARP */
1853 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1854 MVPP2_PE_LAST_FREE_TID);
1858 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1859 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1862 mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
1864 /* Generate flow in the next iteration*/
1865 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1866 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1867 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
1868 MVPP2_PRS_RI_L3_PROTO_MASK);
1870 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1872 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1874 /* Update shadow table and hw entry */
1875 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1876 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1877 priv->prs_shadow[pe.index].finish = true;
1878 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
1879 MVPP2_PRS_RI_L3_PROTO_MASK);
1880 mvpp2_prs_hw_write(priv, &pe);
1882 /* Ethertype: LBTD */
1883 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1884 MVPP2_PE_LAST_FREE_TID);
1888 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1889 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1892 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
1894 /* Generate flow in the next iteration*/
1895 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1896 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1897 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
1898 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
1899 MVPP2_PRS_RI_CPU_CODE_MASK |
1900 MVPP2_PRS_RI_UDF3_MASK);
1902 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1904 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1906 /* Update shadow table and hw entry */
1907 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1908 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1909 priv->prs_shadow[pe.index].finish = true;
1910 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
1911 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
1912 MVPP2_PRS_RI_CPU_CODE_MASK |
1913 MVPP2_PRS_RI_UDF3_MASK);
1914 mvpp2_prs_hw_write(priv, &pe);
1916 /* Ethertype: IPv4 without options */
1917 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1918 MVPP2_PE_LAST_FREE_TID);
1922 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1923 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1926 mvpp2_prs_match_etype(&pe, 0, PROT_IP);
1927 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1928 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
1929 MVPP2_PRS_IPV4_HEAD_MASK |
1930 MVPP2_PRS_IPV4_IHL_MASK);
1932 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1933 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
1934 MVPP2_PRS_RI_L3_PROTO_MASK);
1935 /* Skip eth_type + 4 bytes of IP header */
1936 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
1937 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1939 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1941 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1943 /* Update shadow table and hw entry */
1944 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1945 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1946 priv->prs_shadow[pe.index].finish = false;
1947 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
1948 MVPP2_PRS_RI_L3_PROTO_MASK);
1949 mvpp2_prs_hw_write(priv, &pe);
1951 /* Ethertype: IPv4 with options */
1952 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1953 MVPP2_PE_LAST_FREE_TID);
1959 /* Clear tcam data before updating */
1960 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
1961 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
1963 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1964 MVPP2_PRS_IPV4_HEAD,
1965 MVPP2_PRS_IPV4_HEAD_MASK);
1967 /* Clear ri before updating */
1968 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
1969 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
1970 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
1971 MVPP2_PRS_RI_L3_PROTO_MASK);
1973 /* Update shadow table and hw entry */
1974 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1975 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1976 priv->prs_shadow[pe.index].finish = false;
1977 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
1978 MVPP2_PRS_RI_L3_PROTO_MASK);
1979 mvpp2_prs_hw_write(priv, &pe);
1981 /* Ethertype: IPv6 without options */
1982 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1983 MVPP2_PE_LAST_FREE_TID);
1987 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1988 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1991 mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
1993 /* Skip DIP of IPV6 header */
1994 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
1995 MVPP2_MAX_L3_ADDR_SIZE,
1996 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1997 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
1998 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
1999 MVPP2_PRS_RI_L3_PROTO_MASK);
2001 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2003 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2005 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2006 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2007 priv->prs_shadow[pe.index].finish = false;
2008 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
2009 MVPP2_PRS_RI_L3_PROTO_MASK);
2010 mvpp2_prs_hw_write(priv, &pe);
2012 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
2013 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
2014 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
2015 pe.index = MVPP2_PE_ETH_TYPE_UN;
2017 /* Unmask all ports */
2018 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
2020 /* Generate flow in the next iteration*/
2021 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
2022 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
2023 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
2024 MVPP2_PRS_RI_L3_PROTO_MASK);
2025 /* Set L3 offset even it's unknown L3 */
2026 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
2028 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
2030 /* Update shadow table and hw entry */
2031 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
2032 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
2033 priv->prs_shadow[pe.index].finish = true;
2034 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
2035 MVPP2_PRS_RI_L3_PROTO_MASK);
2036 mvpp2_prs_hw_write(priv, &pe);
2041 /* Parser default initialization */
2042 static int mvpp2_prs_default_init(struct udevice *dev,
2047 /* Enable tcam table */
2048 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
2050 /* Clear all tcam and sram entries */
2051 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
2052 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
2053 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
2054 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
2056 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
2057 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
2058 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
2061 /* Invalidate all tcam entries */
2062 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
2063 mvpp2_prs_hw_inv(priv, index);
2065 priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
2066 sizeof(struct mvpp2_prs_shadow),
2068 if (!priv->prs_shadow)
2071 /* Always start from lookup = 0 */
2072 for (index = 0; index < MVPP2_MAX_PORTS; index++)
2073 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
2074 MVPP2_PRS_PORT_LU_MAX, 0);
2076 mvpp2_prs_def_flow_init(priv);
2078 mvpp2_prs_mh_init(priv);
2080 mvpp2_prs_mac_init(priv);
2082 err = mvpp2_prs_etype_init(priv);
2089 /* Compare MAC DA with tcam entry data */
2090 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
2091 const u8 *da, unsigned char *mask)
2093 unsigned char tcam_byte, tcam_mask;
2096 for (index = 0; index < ETH_ALEN; index++) {
2097 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
2098 if (tcam_mask != mask[index])
2101 if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
2108 /* Find tcam entry with matched pair <MAC DA, port> */
2109 static struct mvpp2_prs_entry *
2110 mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
2111 unsigned char *mask, int udf_type)
2113 struct mvpp2_prs_entry *pe;
2116 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2119 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2121 /* Go through the all entires with MVPP2_PRS_LU_MAC */
2122 for (tid = MVPP2_PE_FIRST_FREE_TID;
2123 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
2124 unsigned int entry_pmap;
2126 if (!priv->prs_shadow[tid].valid ||
2127 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
2128 (priv->prs_shadow[tid].udf != udf_type))
2132 mvpp2_prs_hw_read(priv, pe);
2133 entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
2135 if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
2144 /* Update parser's mac da entry */
2145 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
2146 const u8 *da, bool add)
2148 struct mvpp2_prs_entry *pe;
2149 unsigned int pmap, len, ri;
2150 unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2153 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
2154 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
2155 MVPP2_PRS_UDF_MAC_DEF);
2162 /* Create new TCAM entry */
2163 /* Find first range mac entry*/
2164 for (tid = MVPP2_PE_FIRST_FREE_TID;
2165 tid <= MVPP2_PE_LAST_FREE_TID; tid++)
2166 if (priv->prs_shadow[tid].valid &&
2167 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
2168 (priv->prs_shadow[tid].udf ==
2169 MVPP2_PRS_UDF_MAC_RANGE))
2172 /* Go through the all entries from first to last */
2173 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2178 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2181 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2184 /* Mask all ports */
2185 mvpp2_prs_tcam_port_map_set(pe, 0);
2188 /* Update port mask */
2189 mvpp2_prs_tcam_port_set(pe, port, add);
2191 /* Invalidate the entry if no ports are left enabled */
2192 pmap = mvpp2_prs_tcam_port_map_get(pe);
2198 mvpp2_prs_hw_inv(priv, pe->index);
2199 priv->prs_shadow[pe->index].valid = false;
2204 /* Continue - set next lookup */
2205 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
2207 /* Set match on DA */
2210 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
2212 /* Set result info bits */
2213 ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
2215 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2216 MVPP2_PRS_RI_MAC_ME_MASK);
2217 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2218 MVPP2_PRS_RI_MAC_ME_MASK);
2220 /* Shift to ethertype */
2221 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
2222 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2224 /* Update shadow table and hw entry */
2225 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
2226 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
2227 mvpp2_prs_hw_write(priv, pe);
2234 static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
2238 /* Remove old parser entry */
2239 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
2244 /* Add new parser entry */
2245 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
2249 /* Set addr in the device */
2250 memcpy(port->dev_addr, da, ETH_ALEN);
2255 /* Set prs flow for the port */
2256 static int mvpp2_prs_def_flow(struct mvpp2_port *port)
2258 struct mvpp2_prs_entry *pe;
2261 pe = mvpp2_prs_flow_find(port->priv, port->id);
2263 /* Such entry not exist */
2265 /* Go through the all entires from last to first */
2266 tid = mvpp2_prs_tcam_first_free(port->priv,
2267 MVPP2_PE_LAST_FREE_TID,
2268 MVPP2_PE_FIRST_FREE_TID);
2272 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2276 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
2280 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
2281 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2283 /* Update shadow table */
2284 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
2287 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
2288 mvpp2_prs_hw_write(port->priv, pe);
2294 /* Classifier configuration routines */
2296 /* Update classification flow table registers */
2297 static void mvpp2_cls_flow_write(struct mvpp2 *priv,
2298 struct mvpp2_cls_flow_entry *fe)
2300 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
2301 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
2302 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
2303 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
2306 /* Update classification lookup table register */
2307 static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
2308 struct mvpp2_cls_lookup_entry *le)
2312 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
2313 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
2314 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
2317 /* Classifier default initialization */
2318 static void mvpp2_cls_init(struct mvpp2 *priv)
2320 struct mvpp2_cls_lookup_entry le;
2321 struct mvpp2_cls_flow_entry fe;
2324 /* Enable classifier */
2325 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
2327 /* Clear classifier flow table */
2328 memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
2329 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
2331 mvpp2_cls_flow_write(priv, &fe);
2334 /* Clear classifier lookup table */
2336 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
2339 mvpp2_cls_lookup_write(priv, &le);
2342 mvpp2_cls_lookup_write(priv, &le);
2346 static void mvpp2_cls_port_config(struct mvpp2_port *port)
2348 struct mvpp2_cls_lookup_entry le;
2351 /* Set way for the port */
2352 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
2353 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
2354 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
2356 /* Pick the entry to be accessed in lookup ID decoding table
2357 * according to the way and lkpid.
2359 le.lkpid = port->id;
2363 /* Set initial CPU queue for receiving packets */
2364 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
2365 le.data |= port->first_rxq;
2367 /* Disable classification engines */
2368 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
2370 /* Update lookup ID table entry */
2371 mvpp2_cls_lookup_write(port->priv, &le);
2374 /* Set CPU queue number for oversize packets */
2375 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
2379 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
2380 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
2382 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
2383 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
2385 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
2386 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
2387 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
2390 /* Buffer Manager configuration routines */
2393 static int mvpp2_bm_pool_create(struct udevice *dev,
2395 struct mvpp2_bm_pool *bm_pool, int size)
2399 /* Number of buffer pointers must be a multiple of 16, as per
2400 * hardware constraints
2402 if (!IS_ALIGNED(size, 16))
2405 bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
2406 bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
2407 if (!bm_pool->virt_addr)
2410 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
2411 MVPP2_BM_POOL_PTR_ALIGN)) {
2412 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
2413 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
2417 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
2418 lower_32_bits(bm_pool->dma_addr));
2419 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
2421 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2422 val |= MVPP2_BM_START_MASK;
2423 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2425 bm_pool->type = MVPP2_BM_FREE;
2426 bm_pool->size = size;
2427 bm_pool->pkt_size = 0;
2428 bm_pool->buf_num = 0;
2433 /* Set pool buffer size */
2434 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
2435 struct mvpp2_bm_pool *bm_pool,
2440 bm_pool->buf_size = buf_size;
2442 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
2443 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
2446 /* Free all buffers from the pool */
2447 static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
2448 struct mvpp2_bm_pool *bm_pool)
2450 bm_pool->buf_num = 0;
2454 static int mvpp2_bm_pool_destroy(struct udevice *dev,
2456 struct mvpp2_bm_pool *bm_pool)
2460 mvpp2_bm_bufs_free(dev, priv, bm_pool);
2461 if (bm_pool->buf_num) {
2462 dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
2466 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2467 val |= MVPP2_BM_STOP_MASK;
2468 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2473 static int mvpp2_bm_pools_init(struct udevice *dev,
2477 struct mvpp2_bm_pool *bm_pool;
2479 /* Create all pools with maximum size */
2480 size = MVPP2_BM_POOL_SIZE_MAX;
2481 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2482 bm_pool = &priv->bm_pools[i];
2484 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
2486 goto err_unroll_pools;
2487 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
2492 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
2493 for (i = i - 1; i >= 0; i--)
2494 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
2498 static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
2502 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2503 /* Mask BM all interrupts */
2504 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
2505 /* Clear BM cause register */
2506 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
2509 /* Allocate and initialize BM pools */
2510 priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
2511 sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
2512 if (!priv->bm_pools)
2515 err = mvpp2_bm_pools_init(dev, priv);
2521 /* Attach long pool to rxq */
2522 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
2523 int lrxq, int long_pool)
2528 /* Get queue physical ID */
2529 prxq = port->rxqs[lrxq]->id;
2531 if (port->priv->hw_version == MVPP21)
2532 mask = MVPP21_RXQ_POOL_LONG_MASK;
2534 mask = MVPP22_RXQ_POOL_LONG_MASK;
2536 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2538 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
2539 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2542 /* Set pool number in a BM cookie */
2543 static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
2547 bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
2548 bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
2553 /* Get pool number from a BM cookie */
2554 static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
2556 return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
2559 /* Release buffer to BM */
2560 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
2561 dma_addr_t buf_dma_addr,
2562 unsigned long buf_phys_addr)
2564 if (port->priv->hw_version == MVPP22) {
2567 if (sizeof(dma_addr_t) == 8)
2568 val |= upper_32_bits(buf_dma_addr) &
2569 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
2571 if (sizeof(phys_addr_t) == 8)
2572 val |= (upper_32_bits(buf_phys_addr)
2573 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
2574 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
2576 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
2579 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
2580 * returned in the "cookie" field of the RX
2581 * descriptor. Instead of storing the virtual address, we
2582 * store the physical address
2584 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
2585 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
2588 /* Refill BM pool */
2589 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
2590 dma_addr_t dma_addr,
2591 phys_addr_t phys_addr)
2593 int pool = mvpp2_bm_cookie_pool_get(bm);
2595 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2598 /* Allocate buffers for the pool */
2599 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
2600 struct mvpp2_bm_pool *bm_pool, int buf_num)
2605 (buf_num + bm_pool->buf_num > bm_pool->size)) {
2606 netdev_err(port->dev,
2607 "cannot allocate %d buffers for pool %d\n",
2608 buf_num, bm_pool->id);
2612 for (i = 0; i < buf_num; i++) {
2613 mvpp2_bm_pool_put(port, bm_pool->id,
2614 (dma_addr_t)buffer_loc.rx_buffer[i],
2615 (unsigned long)buffer_loc.rx_buffer[i]);
2619 /* Update BM driver with number of buffers added to pool */
2620 bm_pool->buf_num += i;
2621 bm_pool->in_use_thresh = bm_pool->buf_num / 4;
2626 /* Notify the driver that BM pool is being used as specific type and return the
2627 * pool pointer on success
2629 static struct mvpp2_bm_pool *
2630 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
2633 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
2636 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
2637 netdev_err(port->dev, "mixing pool types is forbidden\n");
2641 if (new_pool->type == MVPP2_BM_FREE)
2642 new_pool->type = type;
2644 /* Allocate buffers in case BM pool is used as long pool, but packet
2645 * size doesn't match MTU or BM pool hasn't being used yet
2647 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
2648 (new_pool->pkt_size == 0)) {
2651 /* Set default buffer number or free all the buffers in case
2652 * the pool is not empty
2654 pkts_num = new_pool->buf_num;
2656 pkts_num = type == MVPP2_BM_SWF_LONG ?
2657 MVPP2_BM_LONG_BUF_NUM :
2658 MVPP2_BM_SHORT_BUF_NUM;
2660 mvpp2_bm_bufs_free(NULL,
2661 port->priv, new_pool);
2663 new_pool->pkt_size = pkt_size;
2665 /* Allocate buffers for this pool */
2666 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
2667 if (num != pkts_num) {
2668 dev_err(dev, "pool %d: %d of %d allocated\n",
2669 new_pool->id, num, pkts_num);
2674 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
2675 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
2680 /* Initialize pools for swf */
2681 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
2685 if (!port->pool_long) {
2687 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
2690 if (!port->pool_long)
2693 port->pool_long->port_map |= (1 << port->id);
2695 for (rxq = 0; rxq < rxq_number; rxq++)
2696 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
2702 /* Port configuration routines */
2704 static void mvpp2_port_mii_set(struct mvpp2_port *port)
2708 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2710 switch (port->phy_interface) {
2711 case PHY_INTERFACE_MODE_SGMII:
2712 val |= MVPP2_GMAC_INBAND_AN_MASK;
2714 case PHY_INTERFACE_MODE_RGMII:
2715 val |= MVPP2_GMAC_PORT_RGMII_MASK;
2717 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
2720 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2723 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
2727 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2728 val |= MVPP2_GMAC_FC_ADV_EN;
2729 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2732 static void mvpp2_port_enable(struct mvpp2_port *port)
2736 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2737 val |= MVPP2_GMAC_PORT_EN_MASK;
2738 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
2739 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2742 static void mvpp2_port_disable(struct mvpp2_port *port)
2746 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2747 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
2748 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2751 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
2752 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
2756 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
2757 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
2758 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2761 /* Configure loopback port */
2762 static void mvpp2_port_loopback_set(struct mvpp2_port *port)
2766 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
2768 if (port->speed == 1000)
2769 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
2771 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
2773 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
2774 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
2776 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
2778 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2781 static void mvpp2_port_reset(struct mvpp2_port *port)
2785 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2786 ~MVPP2_GMAC_PORT_RESET_MASK;
2787 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2789 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2790 MVPP2_GMAC_PORT_RESET_MASK)
2794 /* Change maximum receive size of the port */
2795 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2799 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2800 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2801 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2802 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2803 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2806 /* Set defaults to the MVPP2 port */
2807 static void mvpp2_defaults_set(struct mvpp2_port *port)
2809 int tx_port_num, val, queue, ptxq, lrxq;
2811 if (port->priv->hw_version == MVPP21) {
2812 /* Configure port to loopback if needed */
2813 if (port->flags & MVPP2_F_LOOPBACK)
2814 mvpp2_port_loopback_set(port);
2816 /* Update TX FIFO MIN Threshold */
2817 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2818 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
2819 /* Min. TX threshold must be less than minimal packet length */
2820 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
2821 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2824 /* Disable Legacy WRR, Disable EJP, Release from reset */
2825 tx_port_num = mvpp2_egress_port(port);
2826 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
2828 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
2830 /* Close bandwidth for all queues */
2831 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
2832 ptxq = mvpp2_txq_phys(port->id, queue);
2833 mvpp2_write(port->priv,
2834 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
2837 /* Set refill period to 1 usec, refill tokens
2838 * and bucket size to maximum
2840 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
2841 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
2842 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
2843 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
2844 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
2845 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
2846 val = MVPP2_TXP_TOKEN_SIZE_MAX;
2847 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2849 /* Set MaximumLowLatencyPacketSize value to 256 */
2850 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
2851 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
2852 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
2854 /* Enable Rx cache snoop */
2855 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2856 queue = port->rxqs[lrxq]->id;
2857 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2858 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
2859 MVPP2_SNOOP_BUF_HDR_MASK;
2860 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2864 /* Enable/disable receiving packets */
2865 static void mvpp2_ingress_enable(struct mvpp2_port *port)
2870 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2871 queue = port->rxqs[lrxq]->id;
2872 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2873 val &= ~MVPP2_RXQ_DISABLE_MASK;
2874 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2878 static void mvpp2_ingress_disable(struct mvpp2_port *port)
2883 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2884 queue = port->rxqs[lrxq]->id;
2885 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2886 val |= MVPP2_RXQ_DISABLE_MASK;
2887 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2891 /* Enable transmit via physical egress queue
2892 * - HW starts take descriptors from DRAM
2894 static void mvpp2_egress_enable(struct mvpp2_port *port)
2898 int tx_port_num = mvpp2_egress_port(port);
2900 /* Enable all initialized TXs. */
2902 for (queue = 0; queue < txq_number; queue++) {
2903 struct mvpp2_tx_queue *txq = port->txqs[queue];
2905 if (txq->descs != NULL)
2906 qmap |= (1 << queue);
2909 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2910 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
2913 /* Disable transmit via physical egress queue
2914 * - HW doesn't take descriptors from DRAM
2916 static void mvpp2_egress_disable(struct mvpp2_port *port)
2920 int tx_port_num = mvpp2_egress_port(port);
2922 /* Issue stop command for active channels only */
2923 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2924 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
2925 MVPP2_TXP_SCHED_ENQ_MASK;
2927 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
2928 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
2930 /* Wait for all Tx activity to terminate. */
2933 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
2934 netdev_warn(port->dev,
2935 "Tx stop timed out, status=0x%08x\n",
2942 /* Check port TX Command register that all
2943 * Tx queues are stopped
2945 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
2946 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
2949 /* Rx descriptors helper methods */
2951 /* Get number of Rx descriptors occupied by received packets */
2953 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
2955 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
2957 return val & MVPP2_RXQ_OCCUPIED_MASK;
2960 /* Update Rx queue status with the number of occupied and available
2961 * Rx descriptor slots.
2964 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
2965 int used_count, int free_count)
2967 /* Decrement the number of used descriptors and increment count
2968 * increment the number of free descriptors.
2970 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
2972 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
2975 /* Get pointer to next RX descriptor to be processed by SW */
2976 static inline struct mvpp2_rx_desc *
2977 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
2979 int rx_desc = rxq->next_desc_to_proc;
2981 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
2982 prefetch(rxq->descs + rxq->next_desc_to_proc);
2983 return rxq->descs + rx_desc;
2986 /* Set rx queue offset */
2987 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
2988 int prxq, int offset)
2992 /* Convert offset from bytes to units of 32 bytes */
2993 offset = offset >> 5;
2995 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2996 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
2999 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
3000 MVPP2_RXQ_PACKET_OFFSET_MASK);
3002 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
3005 /* Obtain BM cookie information from descriptor */
3006 static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
3007 struct mvpp2_rx_desc *rx_desc)
3009 int cpu = smp_processor_id();
3012 pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
3013 MVPP2_RXD_BM_POOL_ID_MASK) >>
3014 MVPP2_RXD_BM_POOL_ID_OFFS;
3016 return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
3017 ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
3020 /* Tx descriptors helper methods */
3022 /* Get number of Tx descriptors waiting to be transmitted by HW */
3023 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
3024 struct mvpp2_tx_queue *txq)
3028 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3029 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3031 return val & MVPP2_TXQ_PENDING_MASK;
3034 /* Get pointer to next Tx descriptor to be processed (send) by HW */
3035 static struct mvpp2_tx_desc *
3036 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
3038 int tx_desc = txq->next_desc_to_proc;
3040 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
3041 return txq->descs + tx_desc;
3044 /* Update HW with number of aggregated Tx descriptors to be sent */
3045 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
3047 /* aggregated access - relevant TXQ number is written in TX desc */
3048 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
3051 /* Get number of sent descriptors and decrement counter.
3052 * The number of sent descriptors is returned.
3055 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
3056 struct mvpp2_tx_queue *txq)
3060 /* Reading status reg resets transmitted descriptor counter */
3061 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
3063 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
3064 MVPP2_TRANSMITTED_COUNT_OFFSET;
3067 static void mvpp2_txq_sent_counter_clear(void *arg)
3069 struct mvpp2_port *port = arg;
3072 for (queue = 0; queue < txq_number; queue++) {
3073 int id = port->txqs[queue]->id;
3075 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
3079 /* Set max sizes for Tx queues */
3080 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
3083 int txq, tx_port_num;
3085 mtu = port->pkt_size * 8;
3086 if (mtu > MVPP2_TXP_MTU_MAX)
3087 mtu = MVPP2_TXP_MTU_MAX;
3089 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
3092 /* Indirect access to registers */
3093 tx_port_num = mvpp2_egress_port(port);
3094 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3097 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
3098 val &= ~MVPP2_TXP_MTU_MAX;
3100 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
3102 /* TXP token size and all TXQs token size must be larger that MTU */
3103 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
3104 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
3107 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
3109 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3112 for (txq = 0; txq < txq_number; txq++) {
3113 val = mvpp2_read(port->priv,
3114 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
3115 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
3119 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
3121 mvpp2_write(port->priv,
3122 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
3128 /* Free Tx queue skbuffs */
3129 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
3130 struct mvpp2_tx_queue *txq,
3131 struct mvpp2_txq_pcpu *txq_pcpu, int num)
3135 for (i = 0; i < num; i++)
3136 mvpp2_txq_inc_get(txq_pcpu);
3139 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
3142 int queue = fls(cause) - 1;
3144 return port->rxqs[queue];
3147 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
3150 int queue = fls(cause) - 1;
3152 return port->txqs[queue];
3155 /* Rx/Tx queue initialization/cleanup methods */
3157 /* Allocate and initialize descriptors for aggr TXQ */
3158 static int mvpp2_aggr_txq_init(struct udevice *dev,
3159 struct mvpp2_tx_queue *aggr_txq,
3160 int desc_num, int cpu,
3165 /* Allocate memory for TX descriptors */
3166 aggr_txq->descs = buffer_loc.aggr_tx_descs;
3167 aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
3168 if (!aggr_txq->descs)
3171 /* Make sure descriptor address is cache line size aligned */
3172 BUG_ON(aggr_txq->descs !=
3173 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3175 aggr_txq->last_desc = aggr_txq->size - 1;
3177 /* Aggr TXQ no reset WA */
3178 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
3179 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
3181 /* Set Tx descriptors queue starting address indirect
3184 if (priv->hw_version == MVPP21)
3185 txq_dma = aggr_txq->descs_dma;
3187 txq_dma = aggr_txq->descs_dma >>
3188 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
3190 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
3191 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
3196 /* Create a specified Rx queue */
3197 static int mvpp2_rxq_init(struct mvpp2_port *port,
3198 struct mvpp2_rx_queue *rxq)
3203 rxq->size = port->rx_ring_size;
3205 /* Allocate memory for RX descriptors */
3206 rxq->descs = buffer_loc.rx_descs;
3207 rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
3211 BUG_ON(rxq->descs !=
3212 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3214 rxq->last_desc = rxq->size - 1;
3216 /* Zero occupied and non-occupied counters - direct access */
3217 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
3219 /* Set Rx descriptors queue starting address - indirect access */
3220 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
3221 if (port->priv->hw_version == MVPP21)
3222 rxq_dma = rxq->descs_dma;
3224 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
3225 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
3226 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
3227 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
3230 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
3232 /* Add number of descriptors ready for receiving packets */
3233 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
3238 /* Push packets received by the RXQ to BM pool */
3239 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
3240 struct mvpp2_rx_queue *rxq)
3244 rx_received = mvpp2_rxq_received(port, rxq->id);
3248 for (i = 0; i < rx_received; i++) {
3249 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3250 u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
3252 mvpp2_pool_refill(port, bm,
3253 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
3254 mvpp2_rxdesc_cookie_get(port, rx_desc));
3256 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
3259 /* Cleanup Rx queue */
3260 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
3261 struct mvpp2_rx_queue *rxq)
3263 mvpp2_rxq_drop_pkts(port, rxq);
3267 rxq->next_desc_to_proc = 0;
3270 /* Clear Rx descriptors queue starting address and size;
3271 * free descriptor number
3273 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
3274 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
3275 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
3276 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
3279 /* Create and initialize a Tx queue */
3280 static int mvpp2_txq_init(struct mvpp2_port *port,
3281 struct mvpp2_tx_queue *txq)
3284 int cpu, desc, desc_per_txq, tx_port_num;
3285 struct mvpp2_txq_pcpu *txq_pcpu;
3287 txq->size = port->tx_ring_size;
3289 /* Allocate memory for Tx descriptors */
3290 txq->descs = buffer_loc.tx_descs;
3291 txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
3295 /* Make sure descriptor address is cache line size aligned */
3296 BUG_ON(txq->descs !=
3297 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3299 txq->last_desc = txq->size - 1;
3301 /* Set Tx descriptors queue starting address - indirect access */
3302 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3303 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
3304 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
3305 MVPP2_TXQ_DESC_SIZE_MASK);
3306 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
3307 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
3308 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
3309 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3310 val &= ~MVPP2_TXQ_PENDING_MASK;
3311 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
3313 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
3314 * for each existing TXQ.
3315 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
3316 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
3319 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
3320 (txq->log_id * desc_per_txq);
3322 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
3323 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
3324 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
3326 /* WRR / EJP configuration - indirect access */
3327 tx_port_num = mvpp2_egress_port(port);
3328 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3330 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
3331 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
3332 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
3333 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
3334 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
3336 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
3337 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
3340 for_each_present_cpu(cpu) {
3341 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3342 txq_pcpu->size = txq->size;
3348 /* Free allocated TXQ resources */
3349 static void mvpp2_txq_deinit(struct mvpp2_port *port,
3350 struct mvpp2_tx_queue *txq)
3354 txq->next_desc_to_proc = 0;
3357 /* Set minimum bandwidth for disabled TXQs */
3358 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
3360 /* Set Tx descriptors queue starting address and size */
3361 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3362 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
3363 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
3366 /* Cleanup Tx ports */
3367 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
3369 struct mvpp2_txq_pcpu *txq_pcpu;
3370 int delay, pending, cpu;
3373 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3374 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
3375 val |= MVPP2_TXQ_DRAIN_EN_MASK;
3376 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
3378 /* The napi queue has been stopped so wait for all packets
3379 * to be transmitted.
3383 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
3384 netdev_warn(port->dev,
3385 "port %d: cleaning queue %d timed out\n",
3386 port->id, txq->log_id);
3392 pending = mvpp2_txq_pend_desc_num_get(port, txq);
3395 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
3396 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
3398 for_each_present_cpu(cpu) {
3399 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3401 /* Release all packets */
3402 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
3405 txq_pcpu->count = 0;
3406 txq_pcpu->txq_put_index = 0;
3407 txq_pcpu->txq_get_index = 0;
3411 /* Cleanup all Tx queues */
3412 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
3414 struct mvpp2_tx_queue *txq;
3418 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
3420 /* Reset Tx ports and delete Tx queues */
3421 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
3422 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3424 for (queue = 0; queue < txq_number; queue++) {
3425 txq = port->txqs[queue];
3426 mvpp2_txq_clean(port, txq);
3427 mvpp2_txq_deinit(port, txq);
3430 mvpp2_txq_sent_counter_clear(port);
3432 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
3433 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3436 /* Cleanup all Rx queues */
3437 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
3441 for (queue = 0; queue < rxq_number; queue++)
3442 mvpp2_rxq_deinit(port, port->rxqs[queue]);
3445 /* Init all Rx queues for port */
3446 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
3450 for (queue = 0; queue < rxq_number; queue++) {
3451 err = mvpp2_rxq_init(port, port->rxqs[queue]);
3458 mvpp2_cleanup_rxqs(port);
3462 /* Init all tx queues for port */
3463 static int mvpp2_setup_txqs(struct mvpp2_port *port)
3465 struct mvpp2_tx_queue *txq;
3468 for (queue = 0; queue < txq_number; queue++) {
3469 txq = port->txqs[queue];
3470 err = mvpp2_txq_init(port, txq);
3475 mvpp2_txq_sent_counter_clear(port);
3479 mvpp2_cleanup_txqs(port);
3484 static void mvpp2_link_event(struct mvpp2_port *port)
3486 struct phy_device *phydev = port->phy_dev;
3487 int status_change = 0;
3491 if ((port->speed != phydev->speed) ||
3492 (port->duplex != phydev->duplex)) {
3495 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3496 val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
3497 MVPP2_GMAC_CONFIG_GMII_SPEED |
3498 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
3499 MVPP2_GMAC_AN_SPEED_EN |
3500 MVPP2_GMAC_AN_DUPLEX_EN);
3503 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
3505 if (phydev->speed == SPEED_1000)
3506 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
3507 else if (phydev->speed == SPEED_100)
3508 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
3510 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3512 port->duplex = phydev->duplex;
3513 port->speed = phydev->speed;
3517 if (phydev->link != port->link) {
3518 if (!phydev->link) {
3523 port->link = phydev->link;
3527 if (status_change) {
3529 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3530 val |= (MVPP2_GMAC_FORCE_LINK_PASS |
3531 MVPP2_GMAC_FORCE_LINK_DOWN);
3532 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3533 mvpp2_egress_enable(port);
3534 mvpp2_ingress_enable(port);
3536 mvpp2_ingress_disable(port);
3537 mvpp2_egress_disable(port);
3542 /* Main RX/TX processing routines */
3544 /* Display more error info */
3545 static void mvpp2_rx_error(struct mvpp2_port *port,
3546 struct mvpp2_rx_desc *rx_desc)
3548 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
3549 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
3551 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
3552 case MVPP2_RXD_ERR_CRC:
3553 netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
3556 case MVPP2_RXD_ERR_OVERRUN:
3557 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
3560 case MVPP2_RXD_ERR_RESOURCE:
3561 netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
3567 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
3568 static int mvpp2_rx_refill(struct mvpp2_port *port,
3569 struct mvpp2_bm_pool *bm_pool,
3570 u32 bm, dma_addr_t dma_addr)
3572 mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
3576 /* Set hw internals when starting port */
3577 static void mvpp2_start_dev(struct mvpp2_port *port)
3579 mvpp2_gmac_max_rx_size_set(port);
3580 mvpp2_txp_max_tx_size_set(port);
3582 mvpp2_port_enable(port);
3585 /* Set hw internals when stopping port */
3586 static void mvpp2_stop_dev(struct mvpp2_port *port)
3588 /* Stop new packets from arriving to RXQs */
3589 mvpp2_ingress_disable(port);
3591 mvpp2_egress_disable(port);
3592 mvpp2_port_disable(port);
3595 static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
3597 struct phy_device *phy_dev;
3599 if (!port->init || port->link == 0) {
3600 phy_dev = phy_connect(port->priv->bus, port->phyaddr, dev,
3601 port->phy_interface);
3602 port->phy_dev = phy_dev;
3604 netdev_err(port->dev, "cannot connect to phy\n");
3607 phy_dev->supported &= PHY_GBIT_FEATURES;
3608 phy_dev->advertising = phy_dev->supported;
3610 port->phy_dev = phy_dev;
3615 phy_config(phy_dev);
3616 phy_startup(phy_dev);
3617 if (!phy_dev->link) {
3618 printf("%s: No link\n", phy_dev->dev->name);
3624 mvpp2_egress_enable(port);
3625 mvpp2_ingress_enable(port);
3631 static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
3633 unsigned char mac_bcast[ETH_ALEN] = {
3634 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3637 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
3639 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
3642 err = mvpp2_prs_mac_da_accept(port->priv, port->id,
3643 port->dev_addr, true);
3645 netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
3648 err = mvpp2_prs_def_flow(port);
3650 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
3654 /* Allocate the Rx/Tx queues */
3655 err = mvpp2_setup_rxqs(port);
3657 netdev_err(port->dev, "cannot allocate Rx queues\n");
3661 err = mvpp2_setup_txqs(port);
3663 netdev_err(port->dev, "cannot allocate Tx queues\n");
3667 err = mvpp2_phy_connect(dev, port);
3671 mvpp2_link_event(port);
3673 mvpp2_start_dev(port);
3678 /* No Device ops here in U-Boot */
3680 /* Driver initialization */
3682 static void mvpp2_port_power_up(struct mvpp2_port *port)
3684 struct mvpp2 *priv = port->priv;
3686 mvpp2_port_mii_set(port);
3687 mvpp2_port_periodic_xon_disable(port);
3688 if (priv->hw_version == MVPP21)
3689 mvpp2_port_fc_adv_enable(port);
3690 mvpp2_port_reset(port);
3693 /* Initialize port HW */
3694 static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
3696 struct mvpp2 *priv = port->priv;
3697 struct mvpp2_txq_pcpu *txq_pcpu;
3698 int queue, cpu, err;
3700 if (port->first_rxq + rxq_number >
3701 MVPP2_MAX_PORTS * priv->max_port_rxqs)
3705 mvpp2_egress_disable(port);
3706 mvpp2_port_disable(port);
3708 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
3713 /* Associate physical Tx queues to this port and initialize.
3714 * The mapping is predefined.
3716 for (queue = 0; queue < txq_number; queue++) {
3717 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
3718 struct mvpp2_tx_queue *txq;
3720 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
3724 txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
3729 txq->id = queue_phy_id;
3730 txq->log_id = queue;
3731 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
3732 for_each_present_cpu(cpu) {
3733 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3734 txq_pcpu->cpu = cpu;
3737 port->txqs[queue] = txq;
3740 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
3745 /* Allocate and initialize Rx queue for this port */
3746 for (queue = 0; queue < rxq_number; queue++) {
3747 struct mvpp2_rx_queue *rxq;
3749 /* Map physical Rx queue to port's logical Rx queue */
3750 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
3753 /* Map this Rx queue to a physical queue */
3754 rxq->id = port->first_rxq + queue;
3755 rxq->port = port->id;
3756 rxq->logic_rxq = queue;
3758 port->rxqs[queue] = rxq;
3761 /* Configure Rx queue group interrupt for this port */
3762 if (priv->hw_version == MVPP21) {
3763 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
3768 val = (port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
3769 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
3771 val = (CONFIG_MV_ETH_RXQ <<
3772 MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
3773 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
3776 /* Create Rx descriptor rings */
3777 for (queue = 0; queue < rxq_number; queue++) {
3778 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
3780 rxq->size = port->rx_ring_size;
3781 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
3782 rxq->time_coal = MVPP2_RX_COAL_USEC;
3785 mvpp2_ingress_disable(port);
3787 /* Port default configuration */
3788 mvpp2_defaults_set(port);
3790 /* Port's classifier configuration */
3791 mvpp2_cls_oversize_rxq_set(port);
3792 mvpp2_cls_port_config(port);
3794 /* Provide an initial Rx packet size */
3795 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
3797 /* Initialize pools for swf */
3798 err = mvpp2_swf_bm_pool_init(port);
3805 /* Ports initialization */
3806 static int mvpp2_port_probe(struct udevice *dev,
3807 struct mvpp2_port *port,
3814 const char *phy_mode_str;
3816 int priv_common_regs_num = 2;
3819 phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
3821 dev_err(&pdev->dev, "missing phy\n");
3825 phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
3827 phy_mode = phy_get_interface_by_name(phy_mode_str);
3828 if (phy_mode == -1) {
3829 dev_err(&pdev->dev, "incorrect phy mode\n");
3833 id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
3835 dev_err(&pdev->dev, "missing port-id value\n");
3839 phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
3843 if (priv->hw_version == MVPP21)
3844 port->first_rxq = port->id * rxq_number;
3846 port->first_rxq = port->id * priv->max_port_rxqs;
3847 port->phy_node = phy_node;
3848 port->phy_interface = phy_mode;
3849 port->phyaddr = phyaddr;
3851 if (priv->hw_version == MVPP21) {
3852 port->base = (void __iomem *)dev_get_addr_index(
3853 dev->parent, priv_common_regs_num + id);
3854 if (IS_ERR(port->base))
3855 return PTR_ERR(port->base);
3859 gop_id = fdtdec_get_int(gd->fdt_blob, port_node,
3862 dev_err(&pdev->dev, "missing gop-port-id value\n");
3866 port->base = priv->iface_base + MVPP22_PORT_BASE +
3867 gop_id * MVPP22_PORT_OFFSET;
3870 port->tx_ring_size = MVPP2_MAX_TXD;
3871 port->rx_ring_size = MVPP2_MAX_RXD;
3873 err = mvpp2_port_init(dev, port);
3875 dev_err(&pdev->dev, "failed to init port %d\n", id);
3878 mvpp2_port_power_up(port);
3880 priv->port_list[id] = port;
3884 /* Initialize decoding windows */
3885 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
3891 for (i = 0; i < 6; i++) {
3892 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
3893 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
3896 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
3901 for (i = 0; i < dram->num_cs; i++) {
3902 const struct mbus_dram_window *cs = dram->cs + i;
3904 mvpp2_write(priv, MVPP2_WIN_BASE(i),
3905 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
3906 dram->mbus_dram_target_id);
3908 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
3909 (cs->size - 1) & 0xffff0000);
3911 win_enable |= (1 << i);
3914 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
3917 /* Initialize Rx FIFO's */
3918 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
3922 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
3923 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
3924 MVPP2_RX_FIFO_PORT_DATA_SIZE);
3925 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
3926 MVPP2_RX_FIFO_PORT_ATTR_SIZE);
3929 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
3930 MVPP2_RX_FIFO_PORT_MIN_PKT);
3931 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
3934 static void mvpp2_axi_init(struct mvpp2 *priv)
3936 u32 val, rdval, wrval;
3938 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
3940 /* AXI Bridge Configuration */
3942 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
3943 << MVPP22_AXI_ATTR_CACHE_OFFS;
3944 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
3945 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
3947 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
3948 << MVPP22_AXI_ATTR_CACHE_OFFS;
3949 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
3950 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
3953 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
3954 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
3957 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
3958 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
3959 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
3960 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
3963 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
3964 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
3966 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
3967 << MVPP22_AXI_CODE_CACHE_OFFS;
3968 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
3969 << MVPP22_AXI_CODE_DOMAIN_OFFS;
3970 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
3971 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
3973 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
3974 << MVPP22_AXI_CODE_CACHE_OFFS;
3975 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
3976 << MVPP22_AXI_CODE_DOMAIN_OFFS;
3978 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
3980 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
3981 << MVPP22_AXI_CODE_CACHE_OFFS;
3982 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
3983 << MVPP22_AXI_CODE_DOMAIN_OFFS;
3985 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
3988 /* Initialize network controller common part HW */
3989 static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
3991 const struct mbus_dram_target_info *dram_target_info;
3995 /* Checks for hardware constraints (U-Boot uses only one rxq) */
3996 if ((rxq_number > priv->max_port_rxqs) ||
3997 (txq_number > MVPP2_MAX_TXQ)) {
3998 dev_err(&pdev->dev, "invalid queue size parameter\n");
4002 /* MBUS windows configuration */
4003 dram_target_info = mvebu_mbus_dram_info();
4004 if (dram_target_info)
4005 mvpp2_conf_mbus_windows(dram_target_info, priv);
4007 if (priv->hw_version == MVPP22)
4008 mvpp2_axi_init(priv);
4010 /* Disable HW PHY polling */
4011 if (priv->hw_version == MVPP21) {
4012 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
4013 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
4014 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
4016 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
4017 val &= ~MVPP22_SMI_POLLING_EN;
4018 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
4021 /* Allocate and initialize aggregated TXQs */
4022 priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
4023 sizeof(struct mvpp2_tx_queue),
4025 if (!priv->aggr_txqs)
4028 for_each_present_cpu(i) {
4029 priv->aggr_txqs[i].id = i;
4030 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
4031 err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
4032 MVPP2_AGGR_TXQ_SIZE, i, priv);
4038 mvpp2_rx_fifo_init(priv);
4040 /* Reset Rx queue group interrupt configuration */
4041 for (i = 0; i < MVPP2_MAX_PORTS; i++) {
4042 if (priv->hw_version == MVPP21) {
4043 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(i),
4049 val = (i << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET);
4050 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
4052 val = (CONFIG_MV_ETH_RXQ <<
4053 MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET);
4055 MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
4059 if (priv->hw_version == MVPP21)
4060 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
4061 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
4063 /* Allow cache snoop when transmiting packets */
4064 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
4066 /* Buffer Manager initialization */
4067 err = mvpp2_bm_init(dev, priv);
4071 /* Parser default initialization */
4072 err = mvpp2_prs_default_init(dev, priv);
4076 /* Classifier default initialization */
4077 mvpp2_cls_init(priv);
4082 /* SMI / MDIO functions */
4084 static int smi_wait_ready(struct mvpp2 *priv)
4086 u32 timeout = MVPP2_SMI_TIMEOUT;
4089 /* wait till the SMI is not busy */
4091 /* read smi register */
4092 smi_reg = readl(priv->lms_base + MVPP2_SMI);
4093 if (timeout-- == 0) {
4094 printf("Error: SMI busy timeout\n");
4097 } while (smi_reg & MVPP2_SMI_BUSY);
4103 * mpp2_mdio_read - miiphy_read callback function.
4105 * Returns 16bit phy register value, or 0xffff on error
4107 static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
4109 struct mvpp2 *priv = bus->priv;
4113 /* check parameters */
4114 if (addr > MVPP2_PHY_ADDR_MASK) {
4115 printf("Error: Invalid PHY address %d\n", addr);
4119 if (reg > MVPP2_PHY_REG_MASK) {
4120 printf("Err: Invalid register offset %d\n", reg);
4124 /* wait till the SMI is not busy */
4125 if (smi_wait_ready(priv) < 0)
4128 /* fill the phy address and regiser offset and read opcode */
4129 smi_reg = (addr << MVPP2_SMI_DEV_ADDR_OFFS)
4130 | (reg << MVPP2_SMI_REG_ADDR_OFFS)
4131 | MVPP2_SMI_OPCODE_READ;
4133 /* write the smi register */
4134 writel(smi_reg, priv->lms_base + MVPP2_SMI);
4136 /* wait till read value is ready */
4137 timeout = MVPP2_SMI_TIMEOUT;
4140 /* read smi register */
4141 smi_reg = readl(priv->lms_base + MVPP2_SMI);
4142 if (timeout-- == 0) {
4143 printf("Err: SMI read ready timeout\n");
4146 } while (!(smi_reg & MVPP2_SMI_READ_VALID));
4148 /* Wait for the data to update in the SMI register */
4149 for (timeout = 0; timeout < MVPP2_SMI_TIMEOUT; timeout++)
4152 return readl(priv->lms_base + MVPP2_SMI) & MVPP2_SMI_DATA_MASK;
4156 * mpp2_mdio_write - miiphy_write callback function.
4158 * Returns 0 if write succeed, -EINVAL on bad parameters
4161 static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
4164 struct mvpp2 *priv = bus->priv;
4167 /* check parameters */
4168 if (addr > MVPP2_PHY_ADDR_MASK) {
4169 printf("Error: Invalid PHY address %d\n", addr);
4173 if (reg > MVPP2_PHY_REG_MASK) {
4174 printf("Err: Invalid register offset %d\n", reg);
4178 /* wait till the SMI is not busy */
4179 if (smi_wait_ready(priv) < 0)
4182 /* fill the phy addr and reg offset and write opcode and data */
4183 smi_reg = value << MVPP2_SMI_DATA_OFFS;
4184 smi_reg |= (addr << MVPP2_SMI_DEV_ADDR_OFFS)
4185 | (reg << MVPP2_SMI_REG_ADDR_OFFS);
4186 smi_reg &= ~MVPP2_SMI_OPCODE_READ;
4188 /* write the smi register */
4189 writel(smi_reg, priv->lms_base + MVPP2_SMI);
4194 static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
4196 struct mvpp2_port *port = dev_get_priv(dev);
4197 struct mvpp2_rx_desc *rx_desc;
4198 struct mvpp2_bm_pool *bm_pool;
4199 dma_addr_t dma_addr;
4201 int pool, rx_bytes, err;
4203 struct mvpp2_rx_queue *rxq;
4204 u32 cause_rx_tx, cause_rx, cause_misc;
4207 cause_rx_tx = mvpp2_read(port->priv,
4208 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
4209 cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
4210 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
4211 if (!cause_rx_tx && !cause_misc)
4214 cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
4216 /* Process RX packets */
4217 cause_rx |= port->pending_cause_rx;
4218 rxq = mvpp2_get_rx_queue(port, cause_rx);
4220 /* Get number of received packets and clamp the to-do */
4221 rx_received = mvpp2_rxq_received(port, rxq->id);
4223 /* Return if no packets are received */
4227 rx_desc = mvpp2_rxq_next_desc_get(rxq);
4228 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
4229 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
4230 rx_bytes -= MVPP2_MH_SIZE;
4231 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
4233 bm = mvpp2_bm_cookie_build(port, rx_desc);
4234 pool = mvpp2_bm_cookie_pool_get(bm);
4235 bm_pool = &port->priv->bm_pools[pool];
4237 /* In case of an error, release the requested buffer pointer
4238 * to the Buffer Manager. This request process is controlled
4239 * by the hardware, and the information about the buffer is
4240 * comprised by the RX descriptor.
4242 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
4243 mvpp2_rx_error(port, rx_desc);
4244 /* Return the buffer to the pool */
4245 mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
4249 err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
4251 netdev_err(port->dev, "failed to refill BM pools\n");
4255 /* Update Rx queue management counters */
4257 mvpp2_rxq_status_update(port, rxq->id, 1, 1);
4259 /* give packet to stack - skip on first n bytes */
4260 data = (u8 *)dma_addr + 2 + 32;
4266 * No cache invalidation needed here, since the rx_buffer's are
4267 * located in a uncached memory region
4275 static void mvpp2_txq_drain(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
4280 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4281 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
4283 val |= MVPP2_TXQ_DRAIN_EN_MASK;
4285 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
4286 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4289 static int mvpp2_send(struct udevice *dev, void *packet, int length)
4291 struct mvpp2_port *port = dev_get_priv(dev);
4292 struct mvpp2_tx_queue *txq, *aggr_txq;
4293 struct mvpp2_tx_desc *tx_desc;
4297 txq = port->txqs[0];
4298 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
4300 /* Get a descriptor for the first part of the packet */
4301 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4302 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4303 mvpp2_txdesc_size_set(port, tx_desc, length);
4304 mvpp2_txdesc_offset_set(port, tx_desc,
4305 (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
4306 mvpp2_txdesc_dma_addr_set(port, tx_desc,
4307 (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
4308 /* First and Last descriptor */
4309 mvpp2_txdesc_cmd_set(port, tx_desc,
4310 MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
4311 | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
4314 flush_dcache_range((unsigned long)packet,
4315 (unsigned long)packet + ALIGN(length, PKTALIGN));
4317 /* Enable transmit */
4319 mvpp2_aggr_txq_pend_desc_add(port, 1);
4321 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4325 if (timeout++ > 10000) {
4326 printf("timeout: packet not sent from aggregated to phys TXQ\n");
4329 tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
4332 /* Enable TXQ drain */
4333 mvpp2_txq_drain(port, txq, 1);
4337 if (timeout++ > 10000) {
4338 printf("timeout: packet not sent\n");
4341 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
4344 /* Disable TXQ drain */
4345 mvpp2_txq_drain(port, txq, 0);
4350 static int mvpp2_start(struct udevice *dev)
4352 struct eth_pdata *pdata = dev_get_platdata(dev);
4353 struct mvpp2_port *port = dev_get_priv(dev);
4355 /* Load current MAC address */
4356 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
4358 /* Reconfigure parser accept the original MAC address */
4359 mvpp2_prs_update_mac_da(port, port->dev_addr);
4361 mvpp2_port_power_up(port);
4363 mvpp2_open(dev, port);
4368 static void mvpp2_stop(struct udevice *dev)
4370 struct mvpp2_port *port = dev_get_priv(dev);
4372 mvpp2_stop_dev(port);
4373 mvpp2_cleanup_rxqs(port);
4374 mvpp2_cleanup_txqs(port);
4377 static int mvpp2_probe(struct udevice *dev)
4379 struct mvpp2_port *port = dev_get_priv(dev);
4380 struct mvpp2 *priv = dev_get_priv(dev->parent);
4383 /* Initialize network controller */
4384 err = mvpp2_init(dev, priv);
4386 dev_err(&pdev->dev, "failed to initialize controller\n");
4390 return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
4393 static const struct eth_ops mvpp2_ops = {
4394 .start = mvpp2_start,
4400 static struct driver mvpp2_driver = {
4403 .probe = mvpp2_probe,
4405 .priv_auto_alloc_size = sizeof(struct mvpp2_port),
4406 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
4410 * Use a MISC device to bind the n instances (child nodes) of the
4411 * network base controller in UCLASS_ETH.
4413 static int mvpp2_base_probe(struct udevice *dev)
4415 struct mvpp2 *priv = dev_get_priv(dev);
4416 struct mii_dev *bus;
4421 /* Save hw-version */
4422 priv->hw_version = dev_get_driver_data(dev);
4425 * U-Boot special buffer handling:
4427 * Allocate buffer area for descs and rx_buffers. This is only
4428 * done once for all interfaces. As only one interface can
4429 * be active. Make this area DMA-safe by disabling the D-cache
4432 /* Align buffer area for descs and rx_buffers to 1MiB */
4433 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
4434 mmu_set_region_dcache_behaviour((unsigned long)bd_space,
4435 BD_SPACE, DCACHE_OFF);
4437 buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
4438 size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
4440 buffer_loc.tx_descs =
4441 (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
4442 size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
4444 buffer_loc.rx_descs =
4445 (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
4446 size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
4448 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
4449 buffer_loc.bm_pool[i] =
4450 (unsigned long *)((unsigned long)bd_space + size);
4451 if (priv->hw_version == MVPP21)
4452 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
4454 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
4457 for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
4458 buffer_loc.rx_buffer[i] =
4459 (unsigned long *)((unsigned long)bd_space + size);
4460 size += RX_BUFFER_SIZE;
4463 /* Save base addresses for later use */
4464 priv->base = (void *)dev_get_addr_index(dev, 0);
4465 if (IS_ERR(priv->base))
4466 return PTR_ERR(priv->base);
4468 if (priv->hw_version == MVPP21) {
4469 priv->lms_base = (void *)dev_get_addr_index(dev, 1);
4470 if (IS_ERR(priv->lms_base))
4471 return PTR_ERR(priv->lms_base);
4473 priv->iface_base = (void *)dev_get_addr_index(dev, 1);
4474 if (IS_ERR(priv->iface_base))
4475 return PTR_ERR(priv->iface_base);
4478 if (priv->hw_version == MVPP21)
4479 priv->max_port_rxqs = 8;
4481 priv->max_port_rxqs = 32;
4483 /* Finally create and register the MDIO bus driver */
4486 printf("Failed to allocate MDIO bus\n");
4490 bus->read = mpp2_mdio_read;
4491 bus->write = mpp2_mdio_write;
4492 snprintf(bus->name, sizeof(bus->name), dev->name);
4493 bus->priv = (void *)priv;
4496 return mdio_register(bus);
4499 static int mvpp2_base_bind(struct udevice *parent)
4501 const void *blob = gd->fdt_blob;
4502 int node = dev_of_offset(parent);
4503 struct uclass_driver *drv;
4504 struct udevice *dev;
4505 struct eth_pdata *plat;
4510 /* Lookup eth driver */
4511 drv = lists_uclass_lookup(UCLASS_ETH);
4513 puts("Cannot find eth driver\n");
4517 fdt_for_each_subnode(subnode, blob, node) {
4518 /* Skip disabled ports */
4519 if (!fdtdec_get_is_enabled(blob, subnode))
4522 plat = calloc(1, sizeof(*plat));
4526 id = fdtdec_get_int(blob, subnode, "port-id", -1);
4528 name = calloc(1, 16);
4529 sprintf(name, "mvpp2-%d", id);
4531 /* Create child device UCLASS_ETH and bind it */
4532 device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
4533 dev_set_of_offset(dev, subnode);
4539 static const struct udevice_id mvpp2_ids[] = {
4541 .compatible = "marvell,armada-375-pp2",
4547 U_BOOT_DRIVER(mvpp2_base) = {
4548 .name = "mvpp2_base",
4550 .of_match = mvpp2_ids,
4551 .bind = mvpp2_base_bind,
4552 .probe = mvpp2_base_probe,
4553 .priv_auto_alloc_size = sizeof(struct mvpp2),