2 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
4 * Copyright (C) 2014 Marvell
6 * Marcin Wojtas <mw@semihalf.com>
9 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
18 #include <dm/device-internal.h>
25 #include <linux/errno.h>
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/soc.h>
31 #include <linux/compat.h>
32 #include <linux/mbus.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 /* Some linux -> U-Boot compatibility stuff */
37 #define netdev_err(dev, fmt, args...) \
39 #define netdev_warn(dev, fmt, args...) \
41 #define netdev_info(dev, fmt, args...) \
43 #define netdev_dbg(dev, fmt, args...) \
46 #define ETH_ALEN 6 /* Octets in one ethernet addr */
48 #define __verify_pcpu_ptr(ptr) \
50 const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
54 #define VERIFY_PERCPU_PTR(__p) \
56 __verify_pcpu_ptr(__p); \
57 (typeof(*(__p)) __kernel __force *)(__p); \
60 #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
61 #define smp_processor_id() 0
62 #define num_present_cpus() 1
63 #define for_each_present_cpu(cpu) \
64 for ((cpu) = 0; (cpu) < 1; (cpu)++)
66 #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
68 #define CONFIG_NR_CPUS 1
69 #define ETH_HLEN ETHER_HDR_SIZE /* Total octets in header */
71 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
72 #define WRAP (2 + ETH_HLEN + 4 + 32)
74 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
76 #define MVPP2_SMI_TIMEOUT 10000
78 /* RX Fifo Registers */
79 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
80 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
81 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
82 #define MVPP2_RX_FIFO_INIT_REG 0x64
84 /* RX DMA Top Registers */
85 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
86 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
87 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
88 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
89 #define MVPP2_POOL_BUF_SIZE_OFFSET 5
90 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
91 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
92 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
93 #define MVPP2_RXQ_POOL_SHORT_OFFS 20
94 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
95 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
96 #define MVPP2_RXQ_POOL_LONG_OFFS 24
97 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
98 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
99 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
100 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
101 #define MVPP2_RXQ_DISABLE_MASK BIT(31)
103 /* Parser Registers */
104 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
105 #define MVPP2_PRS_PORT_LU_MAX 0xf
106 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
107 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
108 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
109 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
110 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
111 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
112 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
113 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
114 #define MVPP2_PRS_TCAM_IDX_REG 0x1100
115 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
116 #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
117 #define MVPP2_PRS_SRAM_IDX_REG 0x1200
118 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
119 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
120 #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
122 /* Classifier Registers */
123 #define MVPP2_CLS_MODE_REG 0x1800
124 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
125 #define MVPP2_CLS_PORT_WAY_REG 0x1810
126 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
127 #define MVPP2_CLS_LKP_INDEX_REG 0x1814
128 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
129 #define MVPP2_CLS_LKP_TBL_REG 0x1818
130 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
131 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
132 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
133 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
134 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
135 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
136 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
137 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
138 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
139 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
140 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
141 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
143 /* Descriptor Manager Top Registers */
144 #define MVPP2_RXQ_NUM_REG 0x2040
145 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
146 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
147 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
148 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
149 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
150 #define MVPP2_RXQ_NUM_NEW_OFFSET 16
151 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
152 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
153 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
154 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
155 #define MVPP2_RXQ_THRESH_REG 0x204c
156 #define MVPP2_OCCUPIED_THRESH_OFFSET 0
157 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
158 #define MVPP2_RXQ_INDEX_REG 0x2050
159 #define MVPP2_TXQ_NUM_REG 0x2080
160 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
161 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
162 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
163 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
164 #define MVPP2_TXQ_THRESH_REG 0x2094
165 #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
166 #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
167 #define MVPP2_TXQ_INDEX_REG 0x2098
168 #define MVPP2_TXQ_PREF_BUF_REG 0x209c
169 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
170 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
171 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
172 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
173 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
174 #define MVPP2_TXQ_PENDING_REG 0x20a0
175 #define MVPP2_TXQ_PENDING_MASK 0x3fff
176 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
177 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
178 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
179 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
180 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
181 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
182 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
183 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
184 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
185 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
186 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
187 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
188 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
189 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
190 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
191 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
193 /* MBUS bridge registers */
194 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
195 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
196 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
197 #define MVPP2_BASE_ADDR_ENABLE 0x4060
199 /* Interrupt Cause and Mask registers */
200 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
201 #define MVPP2_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
202 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
203 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
204 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
205 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
206 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
207 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
208 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
209 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
210 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
211 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
212 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
213 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
214 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
215 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
216 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
217 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
218 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
219 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
221 /* Buffer Manager registers */
222 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
223 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
224 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
225 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
226 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
227 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
228 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
229 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
230 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
231 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
232 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
233 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
234 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
235 #define MVPP2_BM_START_MASK BIT(0)
236 #define MVPP2_BM_STOP_MASK BIT(1)
237 #define MVPP2_BM_STATE_MASK BIT(4)
238 #define MVPP2_BM_LOW_THRESH_OFFS 8
239 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
240 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
241 MVPP2_BM_LOW_THRESH_OFFS)
242 #define MVPP2_BM_HIGH_THRESH_OFFS 16
243 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
244 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
245 MVPP2_BM_HIGH_THRESH_OFFS)
246 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
247 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
248 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
249 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
250 #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
251 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
252 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
253 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
254 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
255 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
256 #define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
257 #define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
258 #define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
259 #define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
260 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
261 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
262 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
263 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
264 #define MVPP2_BM_VIRT_RLS_REG 0x64c0
265 #define MVPP21_BM_MC_RLS_REG 0x64c4
266 #define MVPP2_BM_MC_ID_MASK 0xfff
267 #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
268 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
269 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
270 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
271 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
272 #define MVPP22_BM_MC_RLS_REG 0x64d4
274 /* TX Scheduler registers */
275 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
276 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
277 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
278 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
279 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
280 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
281 #define MVPP2_TXP_SCHED_MTU_REG 0x801c
282 #define MVPP2_TXP_MTU_MAX 0x7FFFF
283 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
284 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
285 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
286 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
287 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
288 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
289 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
290 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
291 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
292 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
293 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
294 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
295 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
296 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
298 /* TX general registers */
299 #define MVPP2_TX_SNOOP_REG 0x8800
300 #define MVPP2_TX_PORT_FLUSH_REG 0x8810
301 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
304 #define MVPP2_SRC_ADDR_MIDDLE 0x24
305 #define MVPP2_SRC_ADDR_HIGH 0x28
306 #define MVPP2_PHY_AN_CFG0_REG 0x34
307 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
308 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
309 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
311 /* Per-port registers */
312 #define MVPP2_GMAC_CTRL_0_REG 0x0
313 #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
314 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
315 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
316 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
317 #define MVPP2_GMAC_CTRL_1_REG 0x4
318 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
319 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
320 #define MVPP2_GMAC_PCS_LB_EN_BIT 6
321 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
322 #define MVPP2_GMAC_SA_LOW_OFFS 7
323 #define MVPP2_GMAC_CTRL_2_REG 0x8
324 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
325 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
326 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
327 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
328 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
329 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
330 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
331 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
332 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
333 #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
334 #define MVPP2_GMAC_FC_ADV_EN BIT(9)
335 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
336 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
337 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
338 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
339 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
340 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
341 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
343 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
345 /* Descriptor ring Macros */
346 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
347 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
349 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
350 #define MVPP2_SMI 0x0054
351 #define MVPP2_PHY_REG_MASK 0x1f
352 /* SMI register fields */
353 #define MVPP2_SMI_DATA_OFFS 0 /* Data */
354 #define MVPP2_SMI_DATA_MASK (0xffff << MVPP2_SMI_DATA_OFFS)
355 #define MVPP2_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
356 #define MVPP2_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
357 #define MVPP2_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
358 #define MVPP2_SMI_OPCODE_READ (1 << MVPP2_SMI_OPCODE_OFFS)
359 #define MVPP2_SMI_READ_VALID (1 << 27) /* Read Valid */
360 #define MVPP2_SMI_BUSY (1 << 28) /* Busy */
362 #define MVPP2_PHY_ADDR_MASK 0x1f
363 #define MVPP2_PHY_REG_MASK 0x1f
365 /* Various constants */
368 #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
369 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
370 #define MVPP2_RX_COAL_PKTS 32
371 #define MVPP2_RX_COAL_USEC 100
373 /* The two bytes Marvell header. Either contains a special value used
374 * by Marvell switches when a specific hardware mode is enabled (not
375 * supported by this driver) or is filled automatically by zeroes on
376 * the RX side. Those two bytes being at the front of the Ethernet
377 * header, they allow to have the IP header aligned on a 4 bytes
378 * boundary automatically: the hardware skips those two bytes on its
381 #define MVPP2_MH_SIZE 2
382 #define MVPP2_ETH_TYPE_LEN 2
383 #define MVPP2_PPPOE_HDR_SIZE 8
384 #define MVPP2_VLAN_TAG_LEN 4
386 /* Lbtd 802.3 type */
387 #define MVPP2_IP_LBDT_TYPE 0xfffa
389 #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
390 #define MVPP2_TX_CSUM_MAX_SIZE 9800
392 /* Timeout constants */
393 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
394 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
396 #define MVPP2_TX_MTU_MAX 0x7ffff
398 /* Maximum number of T-CONTs of PON port */
399 #define MVPP2_MAX_TCONT 16
401 /* Maximum number of supported ports */
402 #define MVPP2_MAX_PORTS 4
404 /* Maximum number of TXQs used by single port */
405 #define MVPP2_MAX_TXQ 8
407 /* Maximum number of RXQs used by single port */
408 #define MVPP2_MAX_RXQ 8
410 /* Default number of TXQs in use */
411 #define MVPP2_DEFAULT_TXQ 1
413 /* Dfault number of RXQs in use */
414 #define MVPP2_DEFAULT_RXQ 1
415 #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
417 /* Total number of RXQs available to all ports */
418 #define MVPP2_RXQ_TOTAL_NUM (MVPP2_MAX_PORTS * MVPP2_MAX_RXQ)
420 /* Max number of Rx descriptors */
421 #define MVPP2_MAX_RXD 16
423 /* Max number of Tx descriptors */
424 #define MVPP2_MAX_TXD 16
426 /* Amount of Tx descriptors that can be reserved at once by CPU */
427 #define MVPP2_CPU_DESC_CHUNK 64
429 /* Max number of Tx descriptors in each aggregated queue */
430 #define MVPP2_AGGR_TXQ_SIZE 256
432 /* Descriptor aligned size */
433 #define MVPP2_DESC_ALIGNED_SIZE 32
435 /* Descriptor alignment mask */
436 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
438 /* RX FIFO constants */
439 #define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000
440 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80
441 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
443 /* RX buffer constants */
444 #define MVPP2_SKB_SHINFO_SIZE \
447 #define MVPP2_RX_PKT_SIZE(mtu) \
448 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
449 ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
451 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
452 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
453 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
454 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
456 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
458 /* IPv6 max L3 address size */
459 #define MVPP2_MAX_L3_ADDR_SIZE 16
462 #define MVPP2_F_LOOPBACK BIT(0)
464 /* Marvell tag types */
465 enum mvpp2_tag_type {
466 MVPP2_TAG_TYPE_NONE = 0,
467 MVPP2_TAG_TYPE_MH = 1,
468 MVPP2_TAG_TYPE_DSA = 2,
469 MVPP2_TAG_TYPE_EDSA = 3,
470 MVPP2_TAG_TYPE_VLAN = 4,
471 MVPP2_TAG_TYPE_LAST = 5
474 /* Parser constants */
475 #define MVPP2_PRS_TCAM_SRAM_SIZE 256
476 #define MVPP2_PRS_TCAM_WORDS 6
477 #define MVPP2_PRS_SRAM_WORDS 4
478 #define MVPP2_PRS_FLOW_ID_SIZE 64
479 #define MVPP2_PRS_FLOW_ID_MASK 0x3f
480 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
481 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
482 #define MVPP2_PRS_IPV4_HEAD 0x40
483 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
484 #define MVPP2_PRS_IPV4_MC 0xe0
485 #define MVPP2_PRS_IPV4_MC_MASK 0xf0
486 #define MVPP2_PRS_IPV4_BC_MASK 0xff
487 #define MVPP2_PRS_IPV4_IHL 0x5
488 #define MVPP2_PRS_IPV4_IHL_MASK 0xf
489 #define MVPP2_PRS_IPV6_MC 0xff
490 #define MVPP2_PRS_IPV6_MC_MASK 0xff
491 #define MVPP2_PRS_IPV6_HOP_MASK 0xff
492 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
493 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
494 #define MVPP2_PRS_DBL_VLANS_MAX 100
497 * - lookup ID - 4 bits
499 * - additional information - 1 byte
500 * - header data - 8 bytes
501 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
503 #define MVPP2_PRS_AI_BITS 8
504 #define MVPP2_PRS_PORT_MASK 0xff
505 #define MVPP2_PRS_LU_MASK 0xf
506 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
507 (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
508 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
509 (((offs) * 2) - ((offs) % 2) + 2)
510 #define MVPP2_PRS_TCAM_AI_BYTE 16
511 #define MVPP2_PRS_TCAM_PORT_BYTE 17
512 #define MVPP2_PRS_TCAM_LU_BYTE 20
513 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
514 #define MVPP2_PRS_TCAM_INV_WORD 5
515 /* Tcam entries ID */
516 #define MVPP2_PE_DROP_ALL 0
517 #define MVPP2_PE_FIRST_FREE_TID 1
518 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
519 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
520 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
521 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
522 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
523 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
524 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
525 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
526 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
527 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
528 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
529 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
530 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
531 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
532 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
533 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
534 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
535 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
536 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
537 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
538 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
539 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
540 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
541 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
542 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
545 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
547 #define MVPP2_PRS_SRAM_RI_OFFS 0
548 #define MVPP2_PRS_SRAM_RI_WORD 0
549 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
550 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
551 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
552 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
553 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
554 #define MVPP2_PRS_SRAM_UDF_OFFS 73
555 #define MVPP2_PRS_SRAM_UDF_BITS 8
556 #define MVPP2_PRS_SRAM_UDF_MASK 0xff
557 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
558 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
559 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
560 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
561 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
562 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
563 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
564 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
565 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
566 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
567 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
568 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
569 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
570 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
571 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
572 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
573 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
574 #define MVPP2_PRS_SRAM_AI_OFFS 90
575 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
576 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
577 #define MVPP2_PRS_SRAM_AI_MASK 0xff
578 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
579 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
580 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
581 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
583 /* Sram result info bits assignment */
584 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
585 #define MVPP2_PRS_RI_DSA_MASK 0x2
586 #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
587 #define MVPP2_PRS_RI_VLAN_NONE 0x0
588 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
589 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
590 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
591 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
592 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
593 #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
594 #define MVPP2_PRS_RI_L2_UCAST 0x0
595 #define MVPP2_PRS_RI_L2_MCAST BIT(9)
596 #define MVPP2_PRS_RI_L2_BCAST BIT(10)
597 #define MVPP2_PRS_RI_PPPOE_MASK 0x800
598 #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
599 #define MVPP2_PRS_RI_L3_UN 0x0
600 #define MVPP2_PRS_RI_L3_IP4 BIT(12)
601 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
602 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
603 #define MVPP2_PRS_RI_L3_IP6 BIT(14)
604 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
605 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
606 #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
607 #define MVPP2_PRS_RI_L3_UCAST 0x0
608 #define MVPP2_PRS_RI_L3_MCAST BIT(15)
609 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
610 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
611 #define MVPP2_PRS_RI_UDF3_MASK 0x300000
612 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
613 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
614 #define MVPP2_PRS_RI_L4_TCP BIT(22)
615 #define MVPP2_PRS_RI_L4_UDP BIT(23)
616 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
617 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
618 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
619 #define MVPP2_PRS_RI_DROP_MASK 0x80000000
621 /* Sram additional info bits assignment */
622 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
623 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
624 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
625 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
626 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
627 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
628 #define MVPP2_PRS_SINGLE_VLAN_AI 0
629 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
632 #define MVPP2_PRS_TAGGED true
633 #define MVPP2_PRS_UNTAGGED false
634 #define MVPP2_PRS_EDSA true
635 #define MVPP2_PRS_DSA false
637 /* MAC entries, shadow udf */
639 MVPP2_PRS_UDF_MAC_DEF,
640 MVPP2_PRS_UDF_MAC_RANGE,
641 MVPP2_PRS_UDF_L2_DEF,
642 MVPP2_PRS_UDF_L2_DEF_COPY,
643 MVPP2_PRS_UDF_L2_USER,
647 enum mvpp2_prs_lookup {
661 enum mvpp2_prs_l3_cast {
662 MVPP2_PRS_L3_UNI_CAST,
663 MVPP2_PRS_L3_MULTI_CAST,
664 MVPP2_PRS_L3_BROAD_CAST
667 /* Classifier constants */
668 #define MVPP2_CLS_FLOWS_TBL_SIZE 512
669 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
670 #define MVPP2_CLS_LKP_TBL_SIZE 64
673 #define MVPP2_BM_POOLS_NUM 1
674 #define MVPP2_BM_LONG_BUF_NUM 16
675 #define MVPP2_BM_SHORT_BUF_NUM 16
676 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
677 #define MVPP2_BM_POOL_PTR_ALIGN 128
678 #define MVPP2_BM_SWF_LONG_POOL(port) 0
680 /* BM cookie (32 bits) definition */
681 #define MVPP2_BM_COOKIE_POOL_OFFS 8
682 #define MVPP2_BM_COOKIE_CPU_OFFS 24
684 /* BM short pool packet size
685 * These value assure that for SWF the total number
686 * of bytes allocated for each buffer will be 512
688 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
698 /* Shared Packet Processor resources */
700 /* Shared registers' base addresses */
702 void __iomem *lms_base;
704 /* List of pointers to port structures */
705 struct mvpp2_port **port_list;
707 /* Aggregated TXQs */
708 struct mvpp2_tx_queue *aggr_txqs;
711 struct mvpp2_bm_pool *bm_pools;
713 /* PRS shadow table */
714 struct mvpp2_prs_shadow *prs_shadow;
715 /* PRS auxiliary table for double vlan entries control */
716 bool *prs_double_vlans;
722 enum { MVPP21, MVPP22 } hw_version;
727 struct mvpp2_pcpu_stats {
741 /* Per-port registers' base address */
744 struct mvpp2_rx_queue **rxqs;
745 struct mvpp2_tx_queue **txqs;
749 u32 pending_cause_rx;
751 /* Per-CPU port control */
752 struct mvpp2_port_pcpu __percpu *pcpu;
759 struct mvpp2_pcpu_stats __percpu *stats;
761 struct phy_device *phy_dev;
762 phy_interface_t phy_interface;
770 struct mvpp2_bm_pool *pool_long;
771 struct mvpp2_bm_pool *pool_short;
773 /* Index of first port's physical RXQ */
776 u8 dev_addr[ETH_ALEN];
779 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
780 * layout of the transmit and reception DMA descriptors, and their
781 * layout is therefore defined by the hardware design
784 #define MVPP2_TXD_L3_OFF_SHIFT 0
785 #define MVPP2_TXD_IP_HLEN_SHIFT 8
786 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
787 #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
788 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
789 #define MVPP2_TXD_PADDING_DISABLE BIT(23)
790 #define MVPP2_TXD_L4_UDP BIT(24)
791 #define MVPP2_TXD_L3_IP6 BIT(26)
792 #define MVPP2_TXD_L_DESC BIT(28)
793 #define MVPP2_TXD_F_DESC BIT(29)
795 #define MVPP2_RXD_ERR_SUMMARY BIT(15)
796 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
797 #define MVPP2_RXD_ERR_CRC 0x0
798 #define MVPP2_RXD_ERR_OVERRUN BIT(13)
799 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
800 #define MVPP2_RXD_BM_POOL_ID_OFFS 16
801 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
802 #define MVPP2_RXD_HWF_SYNC BIT(21)
803 #define MVPP2_RXD_L4_CSUM_OK BIT(22)
804 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
805 #define MVPP2_RXD_L4_TCP BIT(25)
806 #define MVPP2_RXD_L4_UDP BIT(26)
807 #define MVPP2_RXD_L3_IP4 BIT(28)
808 #define MVPP2_RXD_L3_IP6 BIT(30)
809 #define MVPP2_RXD_BUF_HDR BIT(31)
811 /* HW TX descriptor for PPv2.1 */
812 struct mvpp21_tx_desc {
813 u32 command; /* Options used by HW for packet transmitting.*/
814 u8 packet_offset; /* the offset from the buffer beginning */
815 u8 phys_txq; /* destination queue ID */
816 u16 data_size; /* data size of transmitted packet in bytes */
817 u32 buf_dma_addr; /* physical addr of transmitted buffer */
818 u32 buf_cookie; /* cookie for access to TX buffer in tx path */
819 u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
820 u32 reserved2; /* reserved (for future use) */
823 /* HW RX descriptor for PPv2.1 */
824 struct mvpp21_rx_desc {
825 u32 status; /* info about received packet */
826 u16 reserved1; /* parser_info (for future use, PnC) */
827 u16 data_size; /* size of received packet in bytes */
828 u32 buf_dma_addr; /* physical address of the buffer */
829 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
830 u16 reserved2; /* gem_port_id (for future use, PON) */
831 u16 reserved3; /* csum_l4 (for future use, PnC) */
832 u8 reserved4; /* bm_qset (for future use, BM) */
834 u16 reserved6; /* classify_info (for future use, PnC) */
835 u32 reserved7; /* flow_id (for future use, PnC) */
839 /* HW TX descriptor for PPv2.2 */
840 struct mvpp22_tx_desc {
846 u64 buf_dma_addr_ptp;
850 /* HW RX descriptor for PPv2.2 */
851 struct mvpp22_rx_desc {
857 u64 buf_dma_addr_key_hash;
861 /* Opaque type used by the driver to manipulate the HW TX and RX
864 struct mvpp2_tx_desc {
866 struct mvpp21_tx_desc pp21;
867 struct mvpp22_tx_desc pp22;
871 struct mvpp2_rx_desc {
873 struct mvpp21_rx_desc pp21;
874 struct mvpp22_rx_desc pp22;
878 /* Per-CPU Tx queue control */
879 struct mvpp2_txq_pcpu {
882 /* Number of Tx DMA descriptors in the descriptor ring */
885 /* Number of currently used Tx DMA descriptor in the
890 /* Number of Tx DMA descriptors reserved for each CPU */
893 /* Index of last TX DMA descriptor that was inserted */
896 /* Index of the TX DMA descriptor to be cleaned up */
900 struct mvpp2_tx_queue {
901 /* Physical number of this Tx queue */
904 /* Logical number of this Tx queue */
907 /* Number of Tx DMA descriptors in the descriptor ring */
910 /* Number of currently used Tx DMA descriptor in the descriptor ring */
913 /* Per-CPU control of physical Tx queues */
914 struct mvpp2_txq_pcpu __percpu *pcpu;
918 /* Virtual address of thex Tx DMA descriptors array */
919 struct mvpp2_tx_desc *descs;
921 /* DMA address of the Tx DMA descriptors array */
922 dma_addr_t descs_dma;
924 /* Index of the last Tx DMA descriptor */
927 /* Index of the next Tx DMA descriptor to process */
928 int next_desc_to_proc;
931 struct mvpp2_rx_queue {
932 /* RX queue number, in the range 0-31 for physical RXQs */
935 /* Num of rx descriptors in the rx descriptor ring */
941 /* Virtual address of the RX DMA descriptors array */
942 struct mvpp2_rx_desc *descs;
944 /* DMA address of the RX DMA descriptors array */
945 dma_addr_t descs_dma;
947 /* Index of the last RX DMA descriptor */
950 /* Index of the next RX DMA descriptor to process */
951 int next_desc_to_proc;
953 /* ID of port to which physical RXQ is mapped */
956 /* Port's logic RXQ number to which physical RXQ is mapped */
960 union mvpp2_prs_tcam_entry {
961 u32 word[MVPP2_PRS_TCAM_WORDS];
962 u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
965 union mvpp2_prs_sram_entry {
966 u32 word[MVPP2_PRS_SRAM_WORDS];
967 u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
970 struct mvpp2_prs_entry {
972 union mvpp2_prs_tcam_entry tcam;
973 union mvpp2_prs_sram_entry sram;
976 struct mvpp2_prs_shadow {
983 /* User defined offset */
991 struct mvpp2_cls_flow_entry {
993 u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
996 struct mvpp2_cls_lookup_entry {
1002 struct mvpp2_bm_pool {
1003 /* Pool number in the range 0-7 */
1005 enum mvpp2_bm_type type;
1007 /* Buffer Pointers Pool External (BPPE) size */
1009 /* Number of buffers for this pool */
1011 /* Pool buffer size */
1016 /* BPPE virtual base address */
1017 unsigned long *virt_addr;
1018 /* BPPE DMA base address */
1019 dma_addr_t dma_addr;
1021 /* Ports using BM pool */
1024 /* Occupied buffers indicator */
1028 /* Static declaractions */
1030 /* Number of RXQs used by single port */
1031 static int rxq_number = MVPP2_DEFAULT_RXQ;
1032 /* Number of TXQs used by single port */
1033 static int txq_number = MVPP2_DEFAULT_TXQ;
1035 #define MVPP2_DRIVER_NAME "mvpp2"
1036 #define MVPP2_DRIVER_VERSION "1.0"
1039 * U-Boot internal data, mostly uncached buffers for descriptors and data
1041 struct buffer_location {
1042 struct mvpp2_tx_desc *aggr_tx_descs;
1043 struct mvpp2_tx_desc *tx_descs;
1044 struct mvpp2_rx_desc *rx_descs;
1045 unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
1046 unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
1051 * All 4 interfaces use the same global buffer, since only one interface
1052 * can be enabled at once
1054 static struct buffer_location buffer_loc;
1057 * Page table entries are set to 1MB, or multiples of 1MB
1058 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
1060 #define BD_SPACE (1 << 20)
1062 /* Utility/helper methods */
1064 static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
1066 writel(data, priv->base + offset);
1069 static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
1071 return readl(priv->base + offset);
1074 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
1075 struct mvpp2_tx_desc *tx_desc,
1076 dma_addr_t dma_addr)
1078 if (port->priv->hw_version == MVPP21) {
1079 tx_desc->pp21.buf_dma_addr = dma_addr;
1081 u64 val = (u64)dma_addr;
1083 tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
1084 tx_desc->pp22.buf_dma_addr_ptp |= val;
1088 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
1089 struct mvpp2_tx_desc *tx_desc,
1092 if (port->priv->hw_version == MVPP21)
1093 tx_desc->pp21.data_size = size;
1095 tx_desc->pp22.data_size = size;
1098 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
1099 struct mvpp2_tx_desc *tx_desc,
1102 if (port->priv->hw_version == MVPP21)
1103 tx_desc->pp21.phys_txq = txq;
1105 tx_desc->pp22.phys_txq = txq;
1108 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
1109 struct mvpp2_tx_desc *tx_desc,
1110 unsigned int command)
1112 if (port->priv->hw_version == MVPP21)
1113 tx_desc->pp21.command = command;
1115 tx_desc->pp22.command = command;
1118 static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
1119 struct mvpp2_tx_desc *tx_desc,
1120 unsigned int offset)
1122 if (port->priv->hw_version == MVPP21)
1123 tx_desc->pp21.packet_offset = offset;
1125 tx_desc->pp22.packet_offset = offset;
1128 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
1129 struct mvpp2_rx_desc *rx_desc)
1131 if (port->priv->hw_version == MVPP21)
1132 return rx_desc->pp21.buf_dma_addr;
1134 return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
1137 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
1138 struct mvpp2_rx_desc *rx_desc)
1140 if (port->priv->hw_version == MVPP21)
1141 return rx_desc->pp21.buf_cookie;
1143 return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
1146 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
1147 struct mvpp2_rx_desc *rx_desc)
1149 if (port->priv->hw_version == MVPP21)
1150 return rx_desc->pp21.data_size;
1152 return rx_desc->pp22.data_size;
1155 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
1156 struct mvpp2_rx_desc *rx_desc)
1158 if (port->priv->hw_version == MVPP21)
1159 return rx_desc->pp21.status;
1161 return rx_desc->pp22.status;
1164 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
1166 txq_pcpu->txq_get_index++;
1167 if (txq_pcpu->txq_get_index == txq_pcpu->size)
1168 txq_pcpu->txq_get_index = 0;
1171 /* Get number of physical egress port */
1172 static inline int mvpp2_egress_port(struct mvpp2_port *port)
1174 return MVPP2_MAX_TCONT + port->id;
1177 /* Get number of physical TXQ */
1178 static inline int mvpp2_txq_phys(int port, int txq)
1180 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
1183 /* Parser configuration routines */
1185 /* Update parser tcam and sram hw entries */
1186 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1190 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1193 /* Clear entry invalidation bit */
1194 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
1196 /* Write tcam index - indirect access */
1197 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1198 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1199 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
1201 /* Write sram index - indirect access */
1202 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1203 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1204 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
1209 /* Read tcam entry from hw */
1210 static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
1214 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
1217 /* Write tcam index - indirect access */
1218 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
1220 pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
1221 MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
1222 if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
1223 return MVPP2_PRS_TCAM_ENTRY_INVALID;
1225 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
1226 pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
1228 /* Write sram index - indirect access */
1229 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
1230 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
1231 pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
1236 /* Invalidate tcam hw entry */
1237 static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
1239 /* Write index - indirect access */
1240 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
1241 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
1242 MVPP2_PRS_TCAM_INV_MASK);
1245 /* Enable shadow table entry and set its lookup ID */
1246 static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
1248 priv->prs_shadow[index].valid = true;
1249 priv->prs_shadow[index].lu = lu;
1252 /* Update ri fields in shadow table entry */
1253 static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
1254 unsigned int ri, unsigned int ri_mask)
1256 priv->prs_shadow[index].ri_mask = ri_mask;
1257 priv->prs_shadow[index].ri = ri;
1260 /* Update lookup field in tcam sw entry */
1261 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
1263 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
1265 pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
1266 pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
1269 /* Update mask for single port in tcam sw entry */
1270 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
1271 unsigned int port, bool add)
1273 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1276 pe->tcam.byte[enable_off] &= ~(1 << port);
1278 pe->tcam.byte[enable_off] |= 1 << port;
1281 /* Update port map in tcam sw entry */
1282 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
1285 unsigned char port_mask = MVPP2_PRS_PORT_MASK;
1286 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1288 pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
1289 pe->tcam.byte[enable_off] &= ~port_mask;
1290 pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
1293 /* Obtain port map from tcam sw entry */
1294 static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
1296 int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
1298 return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
1301 /* Set byte of data and its enable bits in tcam sw entry */
1302 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
1303 unsigned int offs, unsigned char byte,
1304 unsigned char enable)
1306 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
1307 pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
1310 /* Get byte of data and its enable bits from tcam sw entry */
1311 static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
1312 unsigned int offs, unsigned char *byte,
1313 unsigned char *enable)
1315 *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
1316 *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
1319 /* Set ethertype in tcam sw entry */
1320 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
1321 unsigned short ethertype)
1323 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
1324 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
1327 /* Set bits in sram sw entry */
1328 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
1331 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
1334 /* Clear bits in sram sw entry */
1335 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
1338 pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
1341 /* Update ri bits in sram sw entry */
1342 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
1343 unsigned int bits, unsigned int mask)
1347 for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
1348 int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
1350 if (!(mask & BIT(i)))
1354 mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
1356 mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
1358 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
1362 /* Update ai bits in sram sw entry */
1363 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
1364 unsigned int bits, unsigned int mask)
1367 int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
1369 for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
1371 if (!(mask & BIT(i)))
1375 mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
1377 mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
1379 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
1383 /* Read ai bits from sram sw entry */
1384 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
1387 int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
1388 int ai_en_off = ai_off + 1;
1389 int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
1391 bits = (pe->sram.byte[ai_off] >> ai_shift) |
1392 (pe->sram.byte[ai_en_off] << (8 - ai_shift));
1397 /* In sram sw entry set lookup ID field of the tcam key to be used in the next
1400 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
1403 int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
1405 mvpp2_prs_sram_bits_clear(pe, sram_next_off,
1406 MVPP2_PRS_SRAM_NEXT_LU_MASK);
1407 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
1410 /* In the sram sw entry set sign and value of the next lookup offset
1411 * and the offset value generated to the classifier
1413 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
1418 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1421 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
1425 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
1426 (unsigned char)shift;
1428 /* Reset and set operation */
1429 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
1430 MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
1431 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
1433 /* Set base offset as current */
1434 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1437 /* In the sram sw entry set sign and value of the user defined offset
1438 * generated to the classifier
1440 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
1441 unsigned int type, int offset,
1446 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1447 offset = 0 - offset;
1449 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
1453 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
1454 MVPP2_PRS_SRAM_UDF_MASK);
1455 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
1456 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1457 MVPP2_PRS_SRAM_UDF_BITS)] &=
1458 ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1459 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
1460 MVPP2_PRS_SRAM_UDF_BITS)] |=
1461 (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
1463 /* Set offset type */
1464 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
1465 MVPP2_PRS_SRAM_UDF_TYPE_MASK);
1466 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
1468 /* Set offset operation */
1469 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
1470 MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
1471 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
1473 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1474 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
1475 ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
1476 (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1478 pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
1479 MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
1480 (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
1482 /* Set base offset as current */
1483 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
1486 /* Find parser flow entry */
1487 static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
1489 struct mvpp2_prs_entry *pe;
1492 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
1495 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
1497 /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
1498 for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
1501 if (!priv->prs_shadow[tid].valid ||
1502 priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
1506 mvpp2_prs_hw_read(priv, pe);
1507 bits = mvpp2_prs_sram_ai_get(pe);
1509 /* Sram store classification lookup ID in AI bits [5:0] */
1510 if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
1518 /* Return first free tcam index, seeking from start to end */
1519 static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
1527 if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
1528 end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
1530 for (tid = start; tid <= end; tid++) {
1531 if (!priv->prs_shadow[tid].valid)
1538 /* Enable/disable dropping all mac da's */
1539 static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
1541 struct mvpp2_prs_entry pe;
1543 if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
1544 /* Entry exist - update port only */
1545 pe.index = MVPP2_PE_DROP_ALL;
1546 mvpp2_prs_hw_read(priv, &pe);
1548 /* Entry doesn't exist - create new */
1549 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1550 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1551 pe.index = MVPP2_PE_DROP_ALL;
1553 /* Non-promiscuous mode for all ports - DROP unknown packets */
1554 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1555 MVPP2_PRS_RI_DROP_MASK);
1557 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1558 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1560 /* Update shadow table */
1561 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1563 /* Mask all ports */
1564 mvpp2_prs_tcam_port_map_set(&pe, 0);
1567 /* Update port mask */
1568 mvpp2_prs_tcam_port_set(&pe, port, add);
1570 mvpp2_prs_hw_write(priv, &pe);
1573 /* Set port to promiscuous mode */
1574 static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
1576 struct mvpp2_prs_entry pe;
1578 /* Promiscuous mode - Accept unknown packets */
1580 if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
1581 /* Entry exist - update port only */
1582 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1583 mvpp2_prs_hw_read(priv, &pe);
1585 /* Entry doesn't exist - create new */
1586 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1587 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1588 pe.index = MVPP2_PE_MAC_PROMISCUOUS;
1590 /* Continue - set next lookup */
1591 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1593 /* Set result info bits */
1594 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
1595 MVPP2_PRS_RI_L2_CAST_MASK);
1597 /* Shift to ethertype */
1598 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1599 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1601 /* Mask all ports */
1602 mvpp2_prs_tcam_port_map_set(&pe, 0);
1604 /* Update shadow table */
1605 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1608 /* Update port mask */
1609 mvpp2_prs_tcam_port_set(&pe, port, add);
1611 mvpp2_prs_hw_write(priv, &pe);
1614 /* Accept multicast */
1615 static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
1618 struct mvpp2_prs_entry pe;
1619 unsigned char da_mc;
1621 /* Ethernet multicast address first byte is
1622 * 0x01 for IPv4 and 0x33 for IPv6
1624 da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
1626 if (priv->prs_shadow[index].valid) {
1627 /* Entry exist - update port only */
1629 mvpp2_prs_hw_read(priv, &pe);
1631 /* Entry doesn't exist - create new */
1632 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1633 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1636 /* Continue - set next lookup */
1637 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
1639 /* Set result info bits */
1640 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
1641 MVPP2_PRS_RI_L2_CAST_MASK);
1643 /* Update tcam entry data first byte */
1644 mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
1646 /* Shift to ethertype */
1647 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
1648 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1650 /* Mask all ports */
1651 mvpp2_prs_tcam_port_map_set(&pe, 0);
1653 /* Update shadow table */
1654 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1657 /* Update port mask */
1658 mvpp2_prs_tcam_port_set(&pe, port, add);
1660 mvpp2_prs_hw_write(priv, &pe);
1663 /* Parser per-port initialization */
1664 static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
1665 int lu_max, int offset)
1670 val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
1671 val &= ~MVPP2_PRS_PORT_LU_MASK(port);
1672 val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
1673 mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
1675 /* Set maximum number of loops for packet received from port */
1676 val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
1677 val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
1678 val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
1679 mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
1681 /* Set initial offset for packet header extraction for the first
1684 val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
1685 val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
1686 val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
1687 mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
1690 /* Default flow entries initialization for all ports */
1691 static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
1693 struct mvpp2_prs_entry pe;
1696 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
1697 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1698 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1699 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
1701 /* Mask all ports */
1702 mvpp2_prs_tcam_port_map_set(&pe, 0);
1705 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
1706 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
1708 /* Update shadow table and hw entry */
1709 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
1710 mvpp2_prs_hw_write(priv, &pe);
1714 /* Set default entry for Marvell Header field */
1715 static void mvpp2_prs_mh_init(struct mvpp2 *priv)
1717 struct mvpp2_prs_entry pe;
1719 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1721 pe.index = MVPP2_PE_MH_DEFAULT;
1722 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
1723 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
1724 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1725 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
1727 /* Unmask all ports */
1728 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1730 /* Update shadow table and hw entry */
1731 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
1732 mvpp2_prs_hw_write(priv, &pe);
1735 /* Set default entires (place holder) for promiscuous, non-promiscuous and
1736 * multicast MAC addresses
1738 static void mvpp2_prs_mac_init(struct mvpp2 *priv)
1740 struct mvpp2_prs_entry pe;
1742 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1744 /* Non-promiscuous mode for all ports - DROP unknown packets */
1745 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
1746 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
1748 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
1749 MVPP2_PRS_RI_DROP_MASK);
1750 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1751 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1753 /* Unmask all ports */
1754 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1756 /* Update shadow table and hw entry */
1757 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
1758 mvpp2_prs_hw_write(priv, &pe);
1760 /* place holders only - no ports */
1761 mvpp2_prs_mac_drop_all_set(priv, 0, false);
1762 mvpp2_prs_mac_promisc_set(priv, 0, false);
1763 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
1764 mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
1767 /* Match basic ethertypes */
1768 static int mvpp2_prs_etype_init(struct mvpp2 *priv)
1770 struct mvpp2_prs_entry pe;
1773 /* Ethertype: PPPoE */
1774 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1775 MVPP2_PE_LAST_FREE_TID);
1779 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1780 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1783 mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
1785 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
1786 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1787 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
1788 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
1789 MVPP2_PRS_RI_PPPOE_MASK);
1791 /* Update shadow table and hw entry */
1792 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1793 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1794 priv->prs_shadow[pe.index].finish = false;
1795 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
1796 MVPP2_PRS_RI_PPPOE_MASK);
1797 mvpp2_prs_hw_write(priv, &pe);
1799 /* Ethertype: ARP */
1800 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1801 MVPP2_PE_LAST_FREE_TID);
1805 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1806 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1809 mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
1811 /* Generate flow in the next iteration*/
1812 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1813 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1814 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
1815 MVPP2_PRS_RI_L3_PROTO_MASK);
1817 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1819 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1821 /* Update shadow table and hw entry */
1822 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1823 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1824 priv->prs_shadow[pe.index].finish = true;
1825 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
1826 MVPP2_PRS_RI_L3_PROTO_MASK);
1827 mvpp2_prs_hw_write(priv, &pe);
1829 /* Ethertype: LBTD */
1830 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1831 MVPP2_PE_LAST_FREE_TID);
1835 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1836 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1839 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
1841 /* Generate flow in the next iteration*/
1842 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1843 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1844 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
1845 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
1846 MVPP2_PRS_RI_CPU_CODE_MASK |
1847 MVPP2_PRS_RI_UDF3_MASK);
1849 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1851 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1853 /* Update shadow table and hw entry */
1854 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1855 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1856 priv->prs_shadow[pe.index].finish = true;
1857 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
1858 MVPP2_PRS_RI_UDF3_RX_SPECIAL,
1859 MVPP2_PRS_RI_CPU_CODE_MASK |
1860 MVPP2_PRS_RI_UDF3_MASK);
1861 mvpp2_prs_hw_write(priv, &pe);
1863 /* Ethertype: IPv4 without options */
1864 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1865 MVPP2_PE_LAST_FREE_TID);
1869 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1870 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1873 mvpp2_prs_match_etype(&pe, 0, PROT_IP);
1874 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1875 MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
1876 MVPP2_PRS_IPV4_HEAD_MASK |
1877 MVPP2_PRS_IPV4_IHL_MASK);
1879 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
1880 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
1881 MVPP2_PRS_RI_L3_PROTO_MASK);
1882 /* Skip eth_type + 4 bytes of IP header */
1883 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
1884 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1886 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1888 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1890 /* Update shadow table and hw entry */
1891 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1892 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1893 priv->prs_shadow[pe.index].finish = false;
1894 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
1895 MVPP2_PRS_RI_L3_PROTO_MASK);
1896 mvpp2_prs_hw_write(priv, &pe);
1898 /* Ethertype: IPv4 with options */
1899 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1900 MVPP2_PE_LAST_FREE_TID);
1906 /* Clear tcam data before updating */
1907 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
1908 pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
1910 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
1911 MVPP2_PRS_IPV4_HEAD,
1912 MVPP2_PRS_IPV4_HEAD_MASK);
1914 /* Clear ri before updating */
1915 pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
1916 pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
1917 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
1918 MVPP2_PRS_RI_L3_PROTO_MASK);
1920 /* Update shadow table and hw entry */
1921 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1922 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1923 priv->prs_shadow[pe.index].finish = false;
1924 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
1925 MVPP2_PRS_RI_L3_PROTO_MASK);
1926 mvpp2_prs_hw_write(priv, &pe);
1928 /* Ethertype: IPv6 without options */
1929 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
1930 MVPP2_PE_LAST_FREE_TID);
1934 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1935 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1938 mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
1940 /* Skip DIP of IPV6 header */
1941 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
1942 MVPP2_MAX_L3_ADDR_SIZE,
1943 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1944 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
1945 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
1946 MVPP2_PRS_RI_L3_PROTO_MASK);
1948 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1950 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1952 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1953 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1954 priv->prs_shadow[pe.index].finish = false;
1955 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
1956 MVPP2_PRS_RI_L3_PROTO_MASK);
1957 mvpp2_prs_hw_write(priv, &pe);
1959 /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
1960 memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
1961 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
1962 pe.index = MVPP2_PE_ETH_TYPE_UN;
1964 /* Unmask all ports */
1965 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
1967 /* Generate flow in the next iteration*/
1968 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
1969 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
1970 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
1971 MVPP2_PRS_RI_L3_PROTO_MASK);
1972 /* Set L3 offset even it's unknown L3 */
1973 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
1975 MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
1977 /* Update shadow table and hw entry */
1978 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
1979 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
1980 priv->prs_shadow[pe.index].finish = true;
1981 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
1982 MVPP2_PRS_RI_L3_PROTO_MASK);
1983 mvpp2_prs_hw_write(priv, &pe);
1988 /* Parser default initialization */
1989 static int mvpp2_prs_default_init(struct udevice *dev,
1994 /* Enable tcam table */
1995 mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
1997 /* Clear all tcam and sram entries */
1998 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
1999 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
2000 for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
2001 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
2003 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
2004 for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
2005 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
2008 /* Invalidate all tcam entries */
2009 for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
2010 mvpp2_prs_hw_inv(priv, index);
2012 priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
2013 sizeof(struct mvpp2_prs_shadow),
2015 if (!priv->prs_shadow)
2018 /* Always start from lookup = 0 */
2019 for (index = 0; index < MVPP2_MAX_PORTS; index++)
2020 mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
2021 MVPP2_PRS_PORT_LU_MAX, 0);
2023 mvpp2_prs_def_flow_init(priv);
2025 mvpp2_prs_mh_init(priv);
2027 mvpp2_prs_mac_init(priv);
2029 err = mvpp2_prs_etype_init(priv);
2036 /* Compare MAC DA with tcam entry data */
2037 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
2038 const u8 *da, unsigned char *mask)
2040 unsigned char tcam_byte, tcam_mask;
2043 for (index = 0; index < ETH_ALEN; index++) {
2044 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
2045 if (tcam_mask != mask[index])
2048 if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
2055 /* Find tcam entry with matched pair <MAC DA, port> */
2056 static struct mvpp2_prs_entry *
2057 mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
2058 unsigned char *mask, int udf_type)
2060 struct mvpp2_prs_entry *pe;
2063 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2066 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2068 /* Go through the all entires with MVPP2_PRS_LU_MAC */
2069 for (tid = MVPP2_PE_FIRST_FREE_TID;
2070 tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
2071 unsigned int entry_pmap;
2073 if (!priv->prs_shadow[tid].valid ||
2074 (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
2075 (priv->prs_shadow[tid].udf != udf_type))
2079 mvpp2_prs_hw_read(priv, pe);
2080 entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
2082 if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
2091 /* Update parser's mac da entry */
2092 static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
2093 const u8 *da, bool add)
2095 struct mvpp2_prs_entry *pe;
2096 unsigned int pmap, len, ri;
2097 unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2100 /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
2101 pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
2102 MVPP2_PRS_UDF_MAC_DEF);
2109 /* Create new TCAM entry */
2110 /* Find first range mac entry*/
2111 for (tid = MVPP2_PE_FIRST_FREE_TID;
2112 tid <= MVPP2_PE_LAST_FREE_TID; tid++)
2113 if (priv->prs_shadow[tid].valid &&
2114 (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
2115 (priv->prs_shadow[tid].udf ==
2116 MVPP2_PRS_UDF_MAC_RANGE))
2119 /* Go through the all entries from first to last */
2120 tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
2125 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2128 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
2131 /* Mask all ports */
2132 mvpp2_prs_tcam_port_map_set(pe, 0);
2135 /* Update port mask */
2136 mvpp2_prs_tcam_port_set(pe, port, add);
2138 /* Invalidate the entry if no ports are left enabled */
2139 pmap = mvpp2_prs_tcam_port_map_get(pe);
2145 mvpp2_prs_hw_inv(priv, pe->index);
2146 priv->prs_shadow[pe->index].valid = false;
2151 /* Continue - set next lookup */
2152 mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
2154 /* Set match on DA */
2157 mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
2159 /* Set result info bits */
2160 ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
2162 mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2163 MVPP2_PRS_RI_MAC_ME_MASK);
2164 mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
2165 MVPP2_PRS_RI_MAC_ME_MASK);
2167 /* Shift to ethertype */
2168 mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
2169 MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
2171 /* Update shadow table and hw entry */
2172 priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
2173 mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
2174 mvpp2_prs_hw_write(priv, pe);
2181 static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
2185 /* Remove old parser entry */
2186 err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
2191 /* Add new parser entry */
2192 err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
2196 /* Set addr in the device */
2197 memcpy(port->dev_addr, da, ETH_ALEN);
2202 /* Set prs flow for the port */
2203 static int mvpp2_prs_def_flow(struct mvpp2_port *port)
2205 struct mvpp2_prs_entry *pe;
2208 pe = mvpp2_prs_flow_find(port->priv, port->id);
2210 /* Such entry not exist */
2212 /* Go through the all entires from last to first */
2213 tid = mvpp2_prs_tcam_first_free(port->priv,
2214 MVPP2_PE_LAST_FREE_TID,
2215 MVPP2_PE_FIRST_FREE_TID);
2219 pe = kzalloc(sizeof(*pe), GFP_KERNEL);
2223 mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
2227 mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
2228 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
2230 /* Update shadow table */
2231 mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
2234 mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
2235 mvpp2_prs_hw_write(port->priv, pe);
2241 /* Classifier configuration routines */
2243 /* Update classification flow table registers */
2244 static void mvpp2_cls_flow_write(struct mvpp2 *priv,
2245 struct mvpp2_cls_flow_entry *fe)
2247 mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
2248 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
2249 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
2250 mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
2253 /* Update classification lookup table register */
2254 static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
2255 struct mvpp2_cls_lookup_entry *le)
2259 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
2260 mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
2261 mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
2264 /* Classifier default initialization */
2265 static void mvpp2_cls_init(struct mvpp2 *priv)
2267 struct mvpp2_cls_lookup_entry le;
2268 struct mvpp2_cls_flow_entry fe;
2271 /* Enable classifier */
2272 mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
2274 /* Clear classifier flow table */
2275 memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
2276 for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
2278 mvpp2_cls_flow_write(priv, &fe);
2281 /* Clear classifier lookup table */
2283 for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
2286 mvpp2_cls_lookup_write(priv, &le);
2289 mvpp2_cls_lookup_write(priv, &le);
2293 static void mvpp2_cls_port_config(struct mvpp2_port *port)
2295 struct mvpp2_cls_lookup_entry le;
2298 /* Set way for the port */
2299 val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
2300 val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
2301 mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
2303 /* Pick the entry to be accessed in lookup ID decoding table
2304 * according to the way and lkpid.
2306 le.lkpid = port->id;
2310 /* Set initial CPU queue for receiving packets */
2311 le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
2312 le.data |= port->first_rxq;
2314 /* Disable classification engines */
2315 le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
2317 /* Update lookup ID table entry */
2318 mvpp2_cls_lookup_write(port->priv, &le);
2321 /* Set CPU queue number for oversize packets */
2322 static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
2326 mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
2327 port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
2329 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
2330 (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
2332 val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
2333 val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
2334 mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
2337 /* Buffer Manager configuration routines */
2340 static int mvpp2_bm_pool_create(struct udevice *dev,
2342 struct mvpp2_bm_pool *bm_pool, int size)
2346 /* Number of buffer pointers must be a multiple of 16, as per
2347 * hardware constraints
2349 if (!IS_ALIGNED(size, 16))
2352 bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
2353 bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
2354 if (!bm_pool->virt_addr)
2357 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
2358 MVPP2_BM_POOL_PTR_ALIGN)) {
2359 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
2360 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
2364 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
2365 lower_32_bits(bm_pool->dma_addr));
2366 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
2368 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2369 val |= MVPP2_BM_START_MASK;
2370 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2372 bm_pool->type = MVPP2_BM_FREE;
2373 bm_pool->size = size;
2374 bm_pool->pkt_size = 0;
2375 bm_pool->buf_num = 0;
2380 /* Set pool buffer size */
2381 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
2382 struct mvpp2_bm_pool *bm_pool,
2387 bm_pool->buf_size = buf_size;
2389 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
2390 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
2393 /* Free all buffers from the pool */
2394 static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
2395 struct mvpp2_bm_pool *bm_pool)
2397 bm_pool->buf_num = 0;
2401 static int mvpp2_bm_pool_destroy(struct udevice *dev,
2403 struct mvpp2_bm_pool *bm_pool)
2407 mvpp2_bm_bufs_free(dev, priv, bm_pool);
2408 if (bm_pool->buf_num) {
2409 dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
2413 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
2414 val |= MVPP2_BM_STOP_MASK;
2415 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
2420 static int mvpp2_bm_pools_init(struct udevice *dev,
2424 struct mvpp2_bm_pool *bm_pool;
2426 /* Create all pools with maximum size */
2427 size = MVPP2_BM_POOL_SIZE_MAX;
2428 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2429 bm_pool = &priv->bm_pools[i];
2431 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
2433 goto err_unroll_pools;
2434 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
2439 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
2440 for (i = i - 1; i >= 0; i--)
2441 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
2445 static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
2449 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
2450 /* Mask BM all interrupts */
2451 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
2452 /* Clear BM cause register */
2453 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
2456 /* Allocate and initialize BM pools */
2457 priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
2458 sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
2459 if (!priv->bm_pools)
2462 err = mvpp2_bm_pools_init(dev, priv);
2468 /* Attach long pool to rxq */
2469 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
2470 int lrxq, int long_pool)
2475 /* Get queue physical ID */
2476 prxq = port->rxqs[lrxq]->id;
2478 if (port->priv->hw_version == MVPP21)
2479 mask = MVPP21_RXQ_POOL_LONG_MASK;
2481 mask = MVPP22_RXQ_POOL_LONG_MASK;
2483 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2485 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
2486 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2489 /* Set pool number in a BM cookie */
2490 static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
2494 bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
2495 bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
2500 /* Get pool number from a BM cookie */
2501 static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
2503 return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
2506 /* Release buffer to BM */
2507 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
2508 dma_addr_t buf_dma_addr,
2509 unsigned long buf_phys_addr)
2511 if (port->priv->hw_version == MVPP22) {
2514 if (sizeof(dma_addr_t) == 8)
2515 val |= upper_32_bits(buf_dma_addr) &
2516 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
2518 if (sizeof(phys_addr_t) == 8)
2519 val |= (upper_32_bits(buf_phys_addr)
2520 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
2521 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
2523 mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
2526 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
2527 * returned in the "cookie" field of the RX
2528 * descriptor. Instead of storing the virtual address, we
2529 * store the physical address
2531 mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
2532 mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
2535 /* Refill BM pool */
2536 static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
2537 dma_addr_t dma_addr,
2538 phys_addr_t phys_addr)
2540 int pool = mvpp2_bm_cookie_pool_get(bm);
2542 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2545 /* Allocate buffers for the pool */
2546 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
2547 struct mvpp2_bm_pool *bm_pool, int buf_num)
2552 (buf_num + bm_pool->buf_num > bm_pool->size)) {
2553 netdev_err(port->dev,
2554 "cannot allocate %d buffers for pool %d\n",
2555 buf_num, bm_pool->id);
2559 for (i = 0; i < buf_num; i++) {
2560 mvpp2_bm_pool_put(port, bm_pool->id,
2561 (dma_addr_t)buffer_loc.rx_buffer[i],
2562 (unsigned long)buffer_loc.rx_buffer[i]);
2566 /* Update BM driver with number of buffers added to pool */
2567 bm_pool->buf_num += i;
2568 bm_pool->in_use_thresh = bm_pool->buf_num / 4;
2573 /* Notify the driver that BM pool is being used as specific type and return the
2574 * pool pointer on success
2576 static struct mvpp2_bm_pool *
2577 mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
2580 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
2583 if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
2584 netdev_err(port->dev, "mixing pool types is forbidden\n");
2588 if (new_pool->type == MVPP2_BM_FREE)
2589 new_pool->type = type;
2591 /* Allocate buffers in case BM pool is used as long pool, but packet
2592 * size doesn't match MTU or BM pool hasn't being used yet
2594 if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
2595 (new_pool->pkt_size == 0)) {
2598 /* Set default buffer number or free all the buffers in case
2599 * the pool is not empty
2601 pkts_num = new_pool->buf_num;
2603 pkts_num = type == MVPP2_BM_SWF_LONG ?
2604 MVPP2_BM_LONG_BUF_NUM :
2605 MVPP2_BM_SHORT_BUF_NUM;
2607 mvpp2_bm_bufs_free(NULL,
2608 port->priv, new_pool);
2610 new_pool->pkt_size = pkt_size;
2612 /* Allocate buffers for this pool */
2613 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
2614 if (num != pkts_num) {
2615 dev_err(dev, "pool %d: %d of %d allocated\n",
2616 new_pool->id, num, pkts_num);
2621 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
2622 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
2627 /* Initialize pools for swf */
2628 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
2632 if (!port->pool_long) {
2634 mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
2637 if (!port->pool_long)
2640 port->pool_long->port_map |= (1 << port->id);
2642 for (rxq = 0; rxq < rxq_number; rxq++)
2643 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
2649 /* Port configuration routines */
2651 static void mvpp2_port_mii_set(struct mvpp2_port *port)
2655 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
2657 switch (port->phy_interface) {
2658 case PHY_INTERFACE_MODE_SGMII:
2659 val |= MVPP2_GMAC_INBAND_AN_MASK;
2661 case PHY_INTERFACE_MODE_RGMII:
2662 val |= MVPP2_GMAC_PORT_RGMII_MASK;
2664 val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
2667 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2670 static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
2674 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2675 val |= MVPP2_GMAC_FC_ADV_EN;
2676 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
2679 static void mvpp2_port_enable(struct mvpp2_port *port)
2683 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2684 val |= MVPP2_GMAC_PORT_EN_MASK;
2685 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
2686 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2689 static void mvpp2_port_disable(struct mvpp2_port *port)
2693 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2694 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
2695 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2698 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
2699 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
2703 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
2704 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
2705 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2708 /* Configure loopback port */
2709 static void mvpp2_port_loopback_set(struct mvpp2_port *port)
2713 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
2715 if (port->speed == 1000)
2716 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
2718 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
2720 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
2721 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
2723 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
2725 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
2728 static void mvpp2_port_reset(struct mvpp2_port *port)
2732 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2733 ~MVPP2_GMAC_PORT_RESET_MASK;
2734 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2736 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
2737 MVPP2_GMAC_PORT_RESET_MASK)
2741 /* Change maximum receive size of the port */
2742 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2746 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2747 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2748 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2749 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2750 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2753 /* Set defaults to the MVPP2 port */
2754 static void mvpp2_defaults_set(struct mvpp2_port *port)
2756 int tx_port_num, val, queue, ptxq, lrxq;
2758 /* Configure port to loopback if needed */
2759 if (port->flags & MVPP2_F_LOOPBACK)
2760 mvpp2_port_loopback_set(port);
2762 /* Update TX FIFO MIN Threshold */
2763 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2764 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
2765 /* Min. TX threshold must be less than minimal packet length */
2766 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
2767 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2769 /* Disable Legacy WRR, Disable EJP, Release from reset */
2770 tx_port_num = mvpp2_egress_port(port);
2771 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
2773 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
2775 /* Close bandwidth for all queues */
2776 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
2777 ptxq = mvpp2_txq_phys(port->id, queue);
2778 mvpp2_write(port->priv,
2779 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
2782 /* Set refill period to 1 usec, refill tokens
2783 * and bucket size to maximum
2785 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
2786 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
2787 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
2788 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
2789 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
2790 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
2791 val = MVPP2_TXP_TOKEN_SIZE_MAX;
2792 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2794 /* Set MaximumLowLatencyPacketSize value to 256 */
2795 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
2796 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
2797 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
2799 /* Enable Rx cache snoop */
2800 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2801 queue = port->rxqs[lrxq]->id;
2802 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2803 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
2804 MVPP2_SNOOP_BUF_HDR_MASK;
2805 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2809 /* Enable/disable receiving packets */
2810 static void mvpp2_ingress_enable(struct mvpp2_port *port)
2815 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2816 queue = port->rxqs[lrxq]->id;
2817 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2818 val &= ~MVPP2_RXQ_DISABLE_MASK;
2819 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2823 static void mvpp2_ingress_disable(struct mvpp2_port *port)
2828 for (lrxq = 0; lrxq < rxq_number; lrxq++) {
2829 queue = port->rxqs[lrxq]->id;
2830 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2831 val |= MVPP2_RXQ_DISABLE_MASK;
2832 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2836 /* Enable transmit via physical egress queue
2837 * - HW starts take descriptors from DRAM
2839 static void mvpp2_egress_enable(struct mvpp2_port *port)
2843 int tx_port_num = mvpp2_egress_port(port);
2845 /* Enable all initialized TXs. */
2847 for (queue = 0; queue < txq_number; queue++) {
2848 struct mvpp2_tx_queue *txq = port->txqs[queue];
2850 if (txq->descs != NULL)
2851 qmap |= (1 << queue);
2854 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2855 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
2858 /* Disable transmit via physical egress queue
2859 * - HW doesn't take descriptors from DRAM
2861 static void mvpp2_egress_disable(struct mvpp2_port *port)
2865 int tx_port_num = mvpp2_egress_port(port);
2867 /* Issue stop command for active channels only */
2868 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2869 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
2870 MVPP2_TXP_SCHED_ENQ_MASK;
2872 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
2873 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
2875 /* Wait for all Tx activity to terminate. */
2878 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
2879 netdev_warn(port->dev,
2880 "Tx stop timed out, status=0x%08x\n",
2887 /* Check port TX Command register that all
2888 * Tx queues are stopped
2890 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
2891 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
2894 /* Rx descriptors helper methods */
2896 /* Get number of Rx descriptors occupied by received packets */
2898 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
2900 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
2902 return val & MVPP2_RXQ_OCCUPIED_MASK;
2905 /* Update Rx queue status with the number of occupied and available
2906 * Rx descriptor slots.
2909 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
2910 int used_count, int free_count)
2912 /* Decrement the number of used descriptors and increment count
2913 * increment the number of free descriptors.
2915 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
2917 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
2920 /* Get pointer to next RX descriptor to be processed by SW */
2921 static inline struct mvpp2_rx_desc *
2922 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
2924 int rx_desc = rxq->next_desc_to_proc;
2926 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
2927 prefetch(rxq->descs + rxq->next_desc_to_proc);
2928 return rxq->descs + rx_desc;
2931 /* Set rx queue offset */
2932 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
2933 int prxq, int offset)
2937 /* Convert offset from bytes to units of 32 bytes */
2938 offset = offset >> 5;
2940 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2941 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
2944 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
2945 MVPP2_RXQ_PACKET_OFFSET_MASK);
2947 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2950 /* Obtain BM cookie information from descriptor */
2951 static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
2952 struct mvpp2_rx_desc *rx_desc)
2954 int cpu = smp_processor_id();
2957 pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
2958 MVPP2_RXD_BM_POOL_ID_MASK) >>
2959 MVPP2_RXD_BM_POOL_ID_OFFS;
2961 return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
2962 ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
2965 /* Tx descriptors helper methods */
2967 /* Get number of Tx descriptors waiting to be transmitted by HW */
2968 static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
2969 struct mvpp2_tx_queue *txq)
2973 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
2974 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
2976 return val & MVPP2_TXQ_PENDING_MASK;
2979 /* Get pointer to next Tx descriptor to be processed (send) by HW */
2980 static struct mvpp2_tx_desc *
2981 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
2983 int tx_desc = txq->next_desc_to_proc;
2985 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
2986 return txq->descs + tx_desc;
2989 /* Update HW with number of aggregated Tx descriptors to be sent */
2990 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
2992 /* aggregated access - relevant TXQ number is written in TX desc */
2993 mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
2996 /* Get number of sent descriptors and decrement counter.
2997 * The number of sent descriptors is returned.
3000 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
3001 struct mvpp2_tx_queue *txq)
3005 /* Reading status reg resets transmitted descriptor counter */
3006 val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
3008 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
3009 MVPP2_TRANSMITTED_COUNT_OFFSET;
3012 static void mvpp2_txq_sent_counter_clear(void *arg)
3014 struct mvpp2_port *port = arg;
3017 for (queue = 0; queue < txq_number; queue++) {
3018 int id = port->txqs[queue]->id;
3020 mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
3024 /* Set max sizes for Tx queues */
3025 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
3028 int txq, tx_port_num;
3030 mtu = port->pkt_size * 8;
3031 if (mtu > MVPP2_TXP_MTU_MAX)
3032 mtu = MVPP2_TXP_MTU_MAX;
3034 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
3037 /* Indirect access to registers */
3038 tx_port_num = mvpp2_egress_port(port);
3039 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3042 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
3043 val &= ~MVPP2_TXP_MTU_MAX;
3045 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
3047 /* TXP token size and all TXQs token size must be larger that MTU */
3048 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
3049 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
3052 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
3054 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
3057 for (txq = 0; txq < txq_number; txq++) {
3058 val = mvpp2_read(port->priv,
3059 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
3060 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
3064 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
3066 mvpp2_write(port->priv,
3067 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
3073 /* Free Tx queue skbuffs */
3074 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
3075 struct mvpp2_tx_queue *txq,
3076 struct mvpp2_txq_pcpu *txq_pcpu, int num)
3080 for (i = 0; i < num; i++)
3081 mvpp2_txq_inc_get(txq_pcpu);
3084 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
3087 int queue = fls(cause) - 1;
3089 return port->rxqs[queue];
3092 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
3095 int queue = fls(cause) - 1;
3097 return port->txqs[queue];
3100 /* Rx/Tx queue initialization/cleanup methods */
3102 /* Allocate and initialize descriptors for aggr TXQ */
3103 static int mvpp2_aggr_txq_init(struct udevice *dev,
3104 struct mvpp2_tx_queue *aggr_txq,
3105 int desc_num, int cpu,
3108 /* Allocate memory for TX descriptors */
3109 aggr_txq->descs = buffer_loc.aggr_tx_descs;
3110 aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
3111 if (!aggr_txq->descs)
3114 /* Make sure descriptor address is cache line size aligned */
3115 BUG_ON(aggr_txq->descs !=
3116 PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3118 aggr_txq->last_desc = aggr_txq->size - 1;
3120 /* Aggr TXQ no reset WA */
3121 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
3122 MVPP2_AGGR_TXQ_INDEX_REG(cpu));
3124 /* Set Tx descriptors queue starting address */
3125 /* indirect access */
3126 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu),
3127 aggr_txq->descs_dma);
3128 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
3133 /* Create a specified Rx queue */
3134 static int mvpp2_rxq_init(struct mvpp2_port *port,
3135 struct mvpp2_rx_queue *rxq)
3138 rxq->size = port->rx_ring_size;
3140 /* Allocate memory for RX descriptors */
3141 rxq->descs = buffer_loc.rx_descs;
3142 rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
3146 BUG_ON(rxq->descs !=
3147 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3149 rxq->last_desc = rxq->size - 1;
3151 /* Zero occupied and non-occupied counters - direct access */
3152 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
3154 /* Set Rx descriptors queue starting address - indirect access */
3155 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
3156 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_dma);
3157 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
3158 mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
3161 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
3163 /* Add number of descriptors ready for receiving packets */
3164 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
3169 /* Push packets received by the RXQ to BM pool */
3170 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
3171 struct mvpp2_rx_queue *rxq)
3175 rx_received = mvpp2_rxq_received(port, rxq->id);
3179 for (i = 0; i < rx_received; i++) {
3180 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3181 u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
3183 mvpp2_pool_refill(port, bm,
3184 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
3185 mvpp2_rxdesc_cookie_get(port, rx_desc));
3187 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
3190 /* Cleanup Rx queue */
3191 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
3192 struct mvpp2_rx_queue *rxq)
3194 mvpp2_rxq_drop_pkts(port, rxq);
3198 rxq->next_desc_to_proc = 0;
3201 /* Clear Rx descriptors queue starting address and size;
3202 * free descriptor number
3204 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
3205 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
3206 mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
3207 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
3210 /* Create and initialize a Tx queue */
3211 static int mvpp2_txq_init(struct mvpp2_port *port,
3212 struct mvpp2_tx_queue *txq)
3215 int cpu, desc, desc_per_txq, tx_port_num;
3216 struct mvpp2_txq_pcpu *txq_pcpu;
3218 txq->size = port->tx_ring_size;
3220 /* Allocate memory for Tx descriptors */
3221 txq->descs = buffer_loc.tx_descs;
3222 txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
3226 /* Make sure descriptor address is cache line size aligned */
3227 BUG_ON(txq->descs !=
3228 PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
3230 txq->last_desc = txq->size - 1;
3232 /* Set Tx descriptors queue starting address - indirect access */
3233 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3234 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
3235 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
3236 MVPP2_TXQ_DESC_SIZE_MASK);
3237 mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
3238 mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
3239 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
3240 val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
3241 val &= ~MVPP2_TXQ_PENDING_MASK;
3242 mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
3244 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
3245 * for each existing TXQ.
3246 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
3247 * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
3250 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
3251 (txq->log_id * desc_per_txq);
3253 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
3254 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
3255 MVPP2_PREF_BUF_THRESH(desc_per_txq/2));
3257 /* WRR / EJP configuration - indirect access */
3258 tx_port_num = mvpp2_egress_port(port);
3259 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3261 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
3262 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
3263 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
3264 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
3265 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
3267 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
3268 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
3271 for_each_present_cpu(cpu) {
3272 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3273 txq_pcpu->size = txq->size;
3279 /* Free allocated TXQ resources */
3280 static void mvpp2_txq_deinit(struct mvpp2_port *port,
3281 struct mvpp2_tx_queue *txq)
3285 txq->next_desc_to_proc = 0;
3288 /* Set minimum bandwidth for disabled TXQs */
3289 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
3291 /* Set Tx descriptors queue starting address and size */
3292 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3293 mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
3294 mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
3297 /* Cleanup Tx ports */
3298 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
3300 struct mvpp2_txq_pcpu *txq_pcpu;
3301 int delay, pending, cpu;
3304 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
3305 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
3306 val |= MVPP2_TXQ_DRAIN_EN_MASK;
3307 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
3309 /* The napi queue has been stopped so wait for all packets
3310 * to be transmitted.
3314 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
3315 netdev_warn(port->dev,
3316 "port %d: cleaning queue %d timed out\n",
3317 port->id, txq->log_id);
3323 pending = mvpp2_txq_pend_desc_num_get(port, txq);
3326 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
3327 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
3329 for_each_present_cpu(cpu) {
3330 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3332 /* Release all packets */
3333 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
3336 txq_pcpu->count = 0;
3337 txq_pcpu->txq_put_index = 0;
3338 txq_pcpu->txq_get_index = 0;
3342 /* Cleanup all Tx queues */
3343 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
3345 struct mvpp2_tx_queue *txq;
3349 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
3351 /* Reset Tx ports and delete Tx queues */
3352 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
3353 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3355 for (queue = 0; queue < txq_number; queue++) {
3356 txq = port->txqs[queue];
3357 mvpp2_txq_clean(port, txq);
3358 mvpp2_txq_deinit(port, txq);
3361 mvpp2_txq_sent_counter_clear(port);
3363 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
3364 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3367 /* Cleanup all Rx queues */
3368 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
3372 for (queue = 0; queue < rxq_number; queue++)
3373 mvpp2_rxq_deinit(port, port->rxqs[queue]);
3376 /* Init all Rx queues for port */
3377 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
3381 for (queue = 0; queue < rxq_number; queue++) {
3382 err = mvpp2_rxq_init(port, port->rxqs[queue]);
3389 mvpp2_cleanup_rxqs(port);
3393 /* Init all tx queues for port */
3394 static int mvpp2_setup_txqs(struct mvpp2_port *port)
3396 struct mvpp2_tx_queue *txq;
3399 for (queue = 0; queue < txq_number; queue++) {
3400 txq = port->txqs[queue];
3401 err = mvpp2_txq_init(port, txq);
3406 mvpp2_txq_sent_counter_clear(port);
3410 mvpp2_cleanup_txqs(port);
3415 static void mvpp2_link_event(struct mvpp2_port *port)
3417 struct phy_device *phydev = port->phy_dev;
3418 int status_change = 0;
3422 if ((port->speed != phydev->speed) ||
3423 (port->duplex != phydev->duplex)) {
3426 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3427 val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
3428 MVPP2_GMAC_CONFIG_GMII_SPEED |
3429 MVPP2_GMAC_CONFIG_FULL_DUPLEX |
3430 MVPP2_GMAC_AN_SPEED_EN |
3431 MVPP2_GMAC_AN_DUPLEX_EN);
3434 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
3436 if (phydev->speed == SPEED_1000)
3437 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
3438 else if (phydev->speed == SPEED_100)
3439 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
3441 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3443 port->duplex = phydev->duplex;
3444 port->speed = phydev->speed;
3448 if (phydev->link != port->link) {
3449 if (!phydev->link) {
3454 port->link = phydev->link;
3458 if (status_change) {
3460 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3461 val |= (MVPP2_GMAC_FORCE_LINK_PASS |
3462 MVPP2_GMAC_FORCE_LINK_DOWN);
3463 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
3464 mvpp2_egress_enable(port);
3465 mvpp2_ingress_enable(port);
3467 mvpp2_ingress_disable(port);
3468 mvpp2_egress_disable(port);
3473 /* Main RX/TX processing routines */
3475 /* Display more error info */
3476 static void mvpp2_rx_error(struct mvpp2_port *port,
3477 struct mvpp2_rx_desc *rx_desc)
3479 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
3480 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
3482 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
3483 case MVPP2_RXD_ERR_CRC:
3484 netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
3487 case MVPP2_RXD_ERR_OVERRUN:
3488 netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
3491 case MVPP2_RXD_ERR_RESOURCE:
3492 netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
3498 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
3499 static int mvpp2_rx_refill(struct mvpp2_port *port,
3500 struct mvpp2_bm_pool *bm_pool,
3501 u32 bm, dma_addr_t dma_addr)
3503 mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
3507 /* Set hw internals when starting port */
3508 static void mvpp2_start_dev(struct mvpp2_port *port)
3510 mvpp2_gmac_max_rx_size_set(port);
3511 mvpp2_txp_max_tx_size_set(port);
3513 mvpp2_port_enable(port);
3516 /* Set hw internals when stopping port */
3517 static void mvpp2_stop_dev(struct mvpp2_port *port)
3519 /* Stop new packets from arriving to RXQs */
3520 mvpp2_ingress_disable(port);
3522 mvpp2_egress_disable(port);
3523 mvpp2_port_disable(port);
3526 static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
3528 struct phy_device *phy_dev;
3530 if (!port->init || port->link == 0) {
3531 phy_dev = phy_connect(port->priv->bus, port->phyaddr, dev,
3532 port->phy_interface);
3533 port->phy_dev = phy_dev;
3535 netdev_err(port->dev, "cannot connect to phy\n");
3538 phy_dev->supported &= PHY_GBIT_FEATURES;
3539 phy_dev->advertising = phy_dev->supported;
3541 port->phy_dev = phy_dev;
3546 phy_config(phy_dev);
3547 phy_startup(phy_dev);
3548 if (!phy_dev->link) {
3549 printf("%s: No link\n", phy_dev->dev->name);
3555 mvpp2_egress_enable(port);
3556 mvpp2_ingress_enable(port);
3562 static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
3564 unsigned char mac_bcast[ETH_ALEN] = {
3565 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3568 err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
3570 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
3573 err = mvpp2_prs_mac_da_accept(port->priv, port->id,
3574 port->dev_addr, true);
3576 netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
3579 err = mvpp2_prs_def_flow(port);
3581 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
3585 /* Allocate the Rx/Tx queues */
3586 err = mvpp2_setup_rxqs(port);
3588 netdev_err(port->dev, "cannot allocate Rx queues\n");
3592 err = mvpp2_setup_txqs(port);
3594 netdev_err(port->dev, "cannot allocate Tx queues\n");
3598 err = mvpp2_phy_connect(dev, port);
3602 mvpp2_link_event(port);
3604 mvpp2_start_dev(port);
3609 /* No Device ops here in U-Boot */
3611 /* Driver initialization */
3613 static void mvpp2_port_power_up(struct mvpp2_port *port)
3615 mvpp2_port_mii_set(port);
3616 mvpp2_port_periodic_xon_disable(port);
3617 mvpp2_port_fc_adv_enable(port);
3618 mvpp2_port_reset(port);
3621 /* Initialize port HW */
3622 static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
3624 struct mvpp2 *priv = port->priv;
3625 struct mvpp2_txq_pcpu *txq_pcpu;
3626 int queue, cpu, err;
3628 if (port->first_rxq + rxq_number > MVPP2_RXQ_TOTAL_NUM)
3632 mvpp2_egress_disable(port);
3633 mvpp2_port_disable(port);
3635 port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
3640 /* Associate physical Tx queues to this port and initialize.
3641 * The mapping is predefined.
3643 for (queue = 0; queue < txq_number; queue++) {
3644 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
3645 struct mvpp2_tx_queue *txq;
3647 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
3651 txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
3656 txq->id = queue_phy_id;
3657 txq->log_id = queue;
3658 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
3659 for_each_present_cpu(cpu) {
3660 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
3661 txq_pcpu->cpu = cpu;
3664 port->txqs[queue] = txq;
3667 port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
3672 /* Allocate and initialize Rx queue for this port */
3673 for (queue = 0; queue < rxq_number; queue++) {
3674 struct mvpp2_rx_queue *rxq;
3676 /* Map physical Rx queue to port's logical Rx queue */
3677 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
3680 /* Map this Rx queue to a physical queue */
3681 rxq->id = port->first_rxq + queue;
3682 rxq->port = port->id;
3683 rxq->logic_rxq = queue;
3685 port->rxqs[queue] = rxq;
3688 /* Configure Rx queue group interrupt for this port */
3689 mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(port->id), CONFIG_MV_ETH_RXQ);
3691 /* Create Rx descriptor rings */
3692 for (queue = 0; queue < rxq_number; queue++) {
3693 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
3695 rxq->size = port->rx_ring_size;
3696 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
3697 rxq->time_coal = MVPP2_RX_COAL_USEC;
3700 mvpp2_ingress_disable(port);
3702 /* Port default configuration */
3703 mvpp2_defaults_set(port);
3705 /* Port's classifier configuration */
3706 mvpp2_cls_oversize_rxq_set(port);
3707 mvpp2_cls_port_config(port);
3709 /* Provide an initial Rx packet size */
3710 port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
3712 /* Initialize pools for swf */
3713 err = mvpp2_swf_bm_pool_init(port);
3720 /* Ports initialization */
3721 static int mvpp2_port_probe(struct udevice *dev,
3722 struct mvpp2_port *port,
3725 int *next_first_rxq)
3730 const char *phy_mode_str;
3732 int priv_common_regs_num = 2;
3735 phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
3737 dev_err(&pdev->dev, "missing phy\n");
3741 phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
3743 phy_mode = phy_get_interface_by_name(phy_mode_str);
3744 if (phy_mode == -1) {
3745 dev_err(&pdev->dev, "incorrect phy mode\n");
3749 id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
3751 dev_err(&pdev->dev, "missing port-id value\n");
3755 phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
3759 port->first_rxq = *next_first_rxq;
3760 port->phy_node = phy_node;
3761 port->phy_interface = phy_mode;
3762 port->phyaddr = phyaddr;
3764 port->base = (void __iomem *)dev_get_addr_index(dev->parent,
3765 priv_common_regs_num
3767 if (IS_ERR(port->base))
3768 return PTR_ERR(port->base);
3770 port->tx_ring_size = MVPP2_MAX_TXD;
3771 port->rx_ring_size = MVPP2_MAX_RXD;
3773 err = mvpp2_port_init(dev, port);
3775 dev_err(&pdev->dev, "failed to init port %d\n", id);
3778 mvpp2_port_power_up(port);
3780 /* Increment the first Rx queue number to be used by the next port */
3781 *next_first_rxq += CONFIG_MV_ETH_RXQ;
3782 priv->port_list[id] = port;
3786 /* Initialize decoding windows */
3787 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
3793 for (i = 0; i < 6; i++) {
3794 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
3795 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
3798 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
3803 for (i = 0; i < dram->num_cs; i++) {
3804 const struct mbus_dram_window *cs = dram->cs + i;
3806 mvpp2_write(priv, MVPP2_WIN_BASE(i),
3807 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
3808 dram->mbus_dram_target_id);
3810 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
3811 (cs->size - 1) & 0xffff0000);
3813 win_enable |= (1 << i);
3816 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
3819 /* Initialize Rx FIFO's */
3820 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
3824 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
3825 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
3826 MVPP2_RX_FIFO_PORT_DATA_SIZE);
3827 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
3828 MVPP2_RX_FIFO_PORT_ATTR_SIZE);
3831 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
3832 MVPP2_RX_FIFO_PORT_MIN_PKT);
3833 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
3836 /* Initialize network controller common part HW */
3837 static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
3839 const struct mbus_dram_target_info *dram_target_info;
3843 /* Checks for hardware constraints (U-Boot uses only one rxq) */
3844 if ((rxq_number > MVPP2_MAX_RXQ) || (txq_number > MVPP2_MAX_TXQ)) {
3845 dev_err(&pdev->dev, "invalid queue size parameter\n");
3849 /* MBUS windows configuration */
3850 dram_target_info = mvebu_mbus_dram_info();
3851 if (dram_target_info)
3852 mvpp2_conf_mbus_windows(dram_target_info, priv);
3854 /* Disable HW PHY polling */
3855 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
3856 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
3857 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
3859 /* Allocate and initialize aggregated TXQs */
3860 priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
3861 sizeof(struct mvpp2_tx_queue),
3863 if (!priv->aggr_txqs)
3866 for_each_present_cpu(i) {
3867 priv->aggr_txqs[i].id = i;
3868 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
3869 err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
3870 MVPP2_AGGR_TXQ_SIZE, i, priv);
3876 mvpp2_rx_fifo_init(priv);
3878 /* Reset Rx queue group interrupt configuration */
3879 for (i = 0; i < MVPP2_MAX_PORTS; i++)
3880 mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i),
3883 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
3884 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
3886 /* Allow cache snoop when transmiting packets */
3887 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
3889 /* Buffer Manager initialization */
3890 err = mvpp2_bm_init(dev, priv);
3894 /* Parser default initialization */
3895 err = mvpp2_prs_default_init(dev, priv);
3899 /* Classifier default initialization */
3900 mvpp2_cls_init(priv);
3905 /* SMI / MDIO functions */
3907 static int smi_wait_ready(struct mvpp2 *priv)
3909 u32 timeout = MVPP2_SMI_TIMEOUT;
3912 /* wait till the SMI is not busy */
3914 /* read smi register */
3915 smi_reg = readl(priv->lms_base + MVPP2_SMI);
3916 if (timeout-- == 0) {
3917 printf("Error: SMI busy timeout\n");
3920 } while (smi_reg & MVPP2_SMI_BUSY);
3926 * mpp2_mdio_read - miiphy_read callback function.
3928 * Returns 16bit phy register value, or 0xffff on error
3930 static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
3932 struct mvpp2 *priv = bus->priv;
3936 /* check parameters */
3937 if (addr > MVPP2_PHY_ADDR_MASK) {
3938 printf("Error: Invalid PHY address %d\n", addr);
3942 if (reg > MVPP2_PHY_REG_MASK) {
3943 printf("Err: Invalid register offset %d\n", reg);
3947 /* wait till the SMI is not busy */
3948 if (smi_wait_ready(priv) < 0)
3951 /* fill the phy address and regiser offset and read opcode */
3952 smi_reg = (addr << MVPP2_SMI_DEV_ADDR_OFFS)
3953 | (reg << MVPP2_SMI_REG_ADDR_OFFS)
3954 | MVPP2_SMI_OPCODE_READ;
3956 /* write the smi register */
3957 writel(smi_reg, priv->lms_base + MVPP2_SMI);
3959 /* wait till read value is ready */
3960 timeout = MVPP2_SMI_TIMEOUT;
3963 /* read smi register */
3964 smi_reg = readl(priv->lms_base + MVPP2_SMI);
3965 if (timeout-- == 0) {
3966 printf("Err: SMI read ready timeout\n");
3969 } while (!(smi_reg & MVPP2_SMI_READ_VALID));
3971 /* Wait for the data to update in the SMI register */
3972 for (timeout = 0; timeout < MVPP2_SMI_TIMEOUT; timeout++)
3975 return readl(priv->lms_base + MVPP2_SMI) & MVPP2_SMI_DATA_MASK;
3979 * mpp2_mdio_write - miiphy_write callback function.
3981 * Returns 0 if write succeed, -EINVAL on bad parameters
3984 static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
3987 struct mvpp2 *priv = bus->priv;
3990 /* check parameters */
3991 if (addr > MVPP2_PHY_ADDR_MASK) {
3992 printf("Error: Invalid PHY address %d\n", addr);
3996 if (reg > MVPP2_PHY_REG_MASK) {
3997 printf("Err: Invalid register offset %d\n", reg);
4001 /* wait till the SMI is not busy */
4002 if (smi_wait_ready(priv) < 0)
4005 /* fill the phy addr and reg offset and write opcode and data */
4006 smi_reg = value << MVPP2_SMI_DATA_OFFS;
4007 smi_reg |= (addr << MVPP2_SMI_DEV_ADDR_OFFS)
4008 | (reg << MVPP2_SMI_REG_ADDR_OFFS);
4009 smi_reg &= ~MVPP2_SMI_OPCODE_READ;
4011 /* write the smi register */
4012 writel(smi_reg, priv->lms_base + MVPP2_SMI);
4017 static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
4019 struct mvpp2_port *port = dev_get_priv(dev);
4020 struct mvpp2_rx_desc *rx_desc;
4021 struct mvpp2_bm_pool *bm_pool;
4022 dma_addr_t dma_addr;
4024 int pool, rx_bytes, err;
4026 struct mvpp2_rx_queue *rxq;
4027 u32 cause_rx_tx, cause_rx, cause_misc;
4030 cause_rx_tx = mvpp2_read(port->priv,
4031 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
4032 cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
4033 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
4034 if (!cause_rx_tx && !cause_misc)
4037 cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
4039 /* Process RX packets */
4040 cause_rx |= port->pending_cause_rx;
4041 rxq = mvpp2_get_rx_queue(port, cause_rx);
4043 /* Get number of received packets and clamp the to-do */
4044 rx_received = mvpp2_rxq_received(port, rxq->id);
4046 /* Return if no packets are received */
4050 rx_desc = mvpp2_rxq_next_desc_get(rxq);
4051 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
4052 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
4053 rx_bytes -= MVPP2_MH_SIZE;
4054 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
4056 bm = mvpp2_bm_cookie_build(port, rx_desc);
4057 pool = mvpp2_bm_cookie_pool_get(bm);
4058 bm_pool = &port->priv->bm_pools[pool];
4060 /* In case of an error, release the requested buffer pointer
4061 * to the Buffer Manager. This request process is controlled
4062 * by the hardware, and the information about the buffer is
4063 * comprised by the RX descriptor.
4065 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
4066 mvpp2_rx_error(port, rx_desc);
4067 /* Return the buffer to the pool */
4068 mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
4072 err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
4074 netdev_err(port->dev, "failed to refill BM pools\n");
4078 /* Update Rx queue management counters */
4080 mvpp2_rxq_status_update(port, rxq->id, 1, 1);
4082 /* give packet to stack - skip on first n bytes */
4083 data = (u8 *)dma_addr + 2 + 32;
4089 * No cache invalidation needed here, since the rx_buffer's are
4090 * located in a uncached memory region
4098 static void mvpp2_txq_drain(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
4103 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4104 val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
4106 val |= MVPP2_TXQ_DRAIN_EN_MASK;
4108 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
4109 mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
4112 static int mvpp2_send(struct udevice *dev, void *packet, int length)
4114 struct mvpp2_port *port = dev_get_priv(dev);
4115 struct mvpp2_tx_queue *txq, *aggr_txq;
4116 struct mvpp2_tx_desc *tx_desc;
4120 txq = port->txqs[0];
4121 aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
4123 /* Get a descriptor for the first part of the packet */
4124 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4125 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4126 mvpp2_txdesc_size_set(port, tx_desc, length);
4127 mvpp2_txdesc_offset_set(port, tx_desc,
4128 (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
4129 mvpp2_txdesc_dma_addr_set(port, tx_desc,
4130 (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
4131 /* First and Last descriptor */
4132 mvpp2_txdesc_cmd_set(port, tx_desc,
4133 MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
4134 | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
4137 flush_dcache_range((unsigned long)packet,
4138 (unsigned long)packet + ALIGN(length, PKTALIGN));
4140 /* Enable transmit */
4142 mvpp2_aggr_txq_pend_desc_add(port, 1);
4144 mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
4148 if (timeout++ > 10000) {
4149 printf("timeout: packet not sent from aggregated to phys TXQ\n");
4152 tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
4155 /* Enable TXQ drain */
4156 mvpp2_txq_drain(port, txq, 1);
4160 if (timeout++ > 10000) {
4161 printf("timeout: packet not sent\n");
4164 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
4167 /* Disable TXQ drain */
4168 mvpp2_txq_drain(port, txq, 0);
4173 static int mvpp2_start(struct udevice *dev)
4175 struct eth_pdata *pdata = dev_get_platdata(dev);
4176 struct mvpp2_port *port = dev_get_priv(dev);
4178 /* Load current MAC address */
4179 memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
4181 /* Reconfigure parser accept the original MAC address */
4182 mvpp2_prs_update_mac_da(port, port->dev_addr);
4184 mvpp2_port_power_up(port);
4186 mvpp2_open(dev, port);
4191 static void mvpp2_stop(struct udevice *dev)
4193 struct mvpp2_port *port = dev_get_priv(dev);
4195 mvpp2_stop_dev(port);
4196 mvpp2_cleanup_rxqs(port);
4197 mvpp2_cleanup_txqs(port);
4200 static int mvpp2_probe(struct udevice *dev)
4202 struct mvpp2_port *port = dev_get_priv(dev);
4203 struct mvpp2 *priv = dev_get_priv(dev->parent);
4206 /* Initialize network controller */
4207 err = mvpp2_init(dev, priv);
4209 dev_err(&pdev->dev, "failed to initialize controller\n");
4213 return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv,
4214 &buffer_loc.first_rxq);
4217 static const struct eth_ops mvpp2_ops = {
4218 .start = mvpp2_start,
4224 static struct driver mvpp2_driver = {
4227 .probe = mvpp2_probe,
4229 .priv_auto_alloc_size = sizeof(struct mvpp2_port),
4230 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
4234 * Use a MISC device to bind the n instances (child nodes) of the
4235 * network base controller in UCLASS_ETH.
4237 static int mvpp2_base_probe(struct udevice *dev)
4239 struct mvpp2 *priv = dev_get_priv(dev);
4240 struct mii_dev *bus;
4245 /* Save hw-version */
4246 priv->hw_version = dev_get_driver_data(dev);
4249 * U-Boot special buffer handling:
4251 * Allocate buffer area for descs and rx_buffers. This is only
4252 * done once for all interfaces. As only one interface can
4253 * be active. Make this area DMA-safe by disabling the D-cache
4256 /* Align buffer area for descs and rx_buffers to 1MiB */
4257 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
4258 mmu_set_region_dcache_behaviour((unsigned long)bd_space,
4259 BD_SPACE, DCACHE_OFF);
4261 buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
4262 size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
4264 buffer_loc.tx_descs =
4265 (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
4266 size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
4268 buffer_loc.rx_descs =
4269 (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
4270 size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
4272 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
4273 buffer_loc.bm_pool[i] =
4274 (unsigned long *)((unsigned long)bd_space + size);
4275 if (priv->hw_version == MVPP21)
4276 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
4278 size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
4281 for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
4282 buffer_loc.rx_buffer[i] =
4283 (unsigned long *)((unsigned long)bd_space + size);
4284 size += RX_BUFFER_SIZE;
4287 /* Save base addresses for later use */
4288 priv->base = (void *)dev_get_addr_index(dev, 0);
4289 if (IS_ERR(priv->base))
4290 return PTR_ERR(priv->base);
4292 priv->lms_base = (void *)dev_get_addr_index(dev, 1);
4293 if (IS_ERR(priv->lms_base))
4294 return PTR_ERR(priv->lms_base);
4296 /* Finally create and register the MDIO bus driver */
4299 printf("Failed to allocate MDIO bus\n");
4303 bus->read = mpp2_mdio_read;
4304 bus->write = mpp2_mdio_write;
4305 snprintf(bus->name, sizeof(bus->name), dev->name);
4306 bus->priv = (void *)priv;
4309 return mdio_register(bus);
4312 static int mvpp2_base_bind(struct udevice *parent)
4314 const void *blob = gd->fdt_blob;
4315 int node = dev_of_offset(parent);
4316 struct uclass_driver *drv;
4317 struct udevice *dev;
4318 struct eth_pdata *plat;
4323 /* Lookup eth driver */
4324 drv = lists_uclass_lookup(UCLASS_ETH);
4326 puts("Cannot find eth driver\n");
4330 fdt_for_each_subnode(subnode, blob, node) {
4331 /* Skip disabled ports */
4332 if (!fdtdec_get_is_enabled(blob, subnode))
4335 plat = calloc(1, sizeof(*plat));
4339 id = fdtdec_get_int(blob, subnode, "port-id", -1);
4341 name = calloc(1, 16);
4342 sprintf(name, "mvpp2-%d", id);
4344 /* Create child device UCLASS_ETH and bind it */
4345 device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
4346 dev_set_of_offset(dev, subnode);
4352 static const struct udevice_id mvpp2_ids[] = {
4354 .compatible = "marvell,armada-375-pp2",
4360 U_BOOT_DRIVER(mvpp2_base) = {
4361 .name = "mvpp2_base",
4363 .of_match = mvpp2_ids,
4364 .bind = mvpp2_base_bind,
4365 .probe = mvpp2_base_probe,
4366 .priv_auto_alloc_size = sizeof(struct mvpp2),