1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2010-2011 Freescale Semiconductor, Inc.
10 #define MIIM_DM9161_SCR 0x10
11 #define MIIM_DM9161_SCR_INIT 0x0610
13 /* DM9161 Specified Configuration and Status Register */
14 #define MIIM_DM9161_SCSR 0x11
15 #define MIIM_DM9161_SCSR_100F 0x8000
16 #define MIIM_DM9161_SCSR_100H 0x4000
17 #define MIIM_DM9161_SCSR_10F 0x2000
18 #define MIIM_DM9161_SCSR_10H 0x1000
20 /* DM9161 10BT Configuration/Status */
21 #define MIIM_DM9161_10BTCSR 0x12
22 #define MIIM_DM9161_10BTCSR_INIT 0x7800
26 static int dm9161_config(struct phy_device *phydev)
28 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_ISOLATE);
29 /* Do not bypass the scrambler/descrambler */
30 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCR,
31 MIIM_DM9161_SCR_INIT);
32 /* Clear 10BTCSR to default */
33 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_10BTCSR,
34 MIIM_DM9161_10BTCSR_INIT);
36 genphy_config_aneg(phydev);
41 static int dm9161_parse_status(struct phy_device *phydev)
45 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCSR);
47 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
48 phydev->speed = SPEED_100;
50 phydev->speed = SPEED_10;
52 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
53 phydev->duplex = DUPLEX_FULL;
55 phydev->duplex = DUPLEX_HALF;
60 static int dm9161_startup(struct phy_device *phydev)
64 ret = genphy_update_link(phydev);
68 return dm9161_parse_status(phydev);
71 static struct phy_driver DM9161_driver = {
72 .name = "Davicom DM9161E",
75 .features = PHY_BASIC_FEATURES,
76 .config = &dm9161_config,
77 .startup = &dm9161_startup,
78 .shutdown = &genphy_shutdown,
81 int phy_davicom_init(void)
83 phy_register(&DM9161_driver);