1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2010-2011 Freescale Semiconductor, Inc.
7 * (C) 2012 NetModule AG, David Andrey, added KSZ9031
8 * (C) Copyright 2017 Adaptrum, Inc.
9 * Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
20 * KSZ9021 - KSZ9031 common
23 #define MII_KSZ90xx_PHY_CTL 0x1f
24 #define MIIM_KSZ90xx_PHYCTL_1000 (1 << 6)
25 #define MIIM_KSZ90xx_PHYCTL_100 (1 << 5)
26 #define MIIM_KSZ90xx_PHYCTL_10 (1 << 4)
27 #define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 << 3)
29 /* KSZ9021 PHY Registers */
30 #define MII_KSZ9021_EXTENDED_CTRL 0x0b
31 #define MII_KSZ9021_EXTENDED_DATAW 0x0c
32 #define MII_KSZ9021_EXTENDED_DATAR 0x0d
34 #define CTRL1000_PREFER_MASTER (1 << 10)
35 #define CTRL1000_CONFIG_MASTER (1 << 11)
36 #define CTRL1000_MANUAL_CONFIG (1 << 12)
38 /* KSZ9031 PHY Registers */
39 #define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
40 #define MII_KSZ9031_MMD_REG_DATA 0x0e
42 static int ksz90xx_startup(struct phy_device *phydev)
47 ret = genphy_update_link(phydev);
51 phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
53 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
54 phydev->duplex = DUPLEX_FULL;
56 phydev->duplex = DUPLEX_HALF;
58 if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
59 phydev->speed = SPEED_1000;
60 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
61 phydev->speed = SPEED_100;
62 else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
63 phydev->speed = SPEED_10;
67 /* Common OF config bits for KSZ9021 and KSZ9031 */
69 struct ksz90x1_reg_field {
71 const u8 size; /* Size of the bitfield, in bits */
72 const u8 off; /* Offset from bit 0 */
73 const u8 dflt; /* Default value */
76 struct ksz90x1_ofcfg {
79 const struct ksz90x1_reg_field *grp;
83 static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
84 { "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
85 { "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
88 static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
89 { "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
90 { "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
93 static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
94 { "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
95 { "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
98 static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = {
99 { "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 }
102 static const struct ksz90x1_reg_field ksz9031_clk_grp[] = {
103 { "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf }
106 static int ksz90x1_of_config_group(struct phy_device *phydev,
107 struct ksz90x1_ofcfg *ofcfg)
109 struct udevice *dev = phydev->dev;
110 struct phy_driver *drv = phydev->drv;
111 const int ps_to_regval = 60;
113 int i, changed = 0, offset, max;
116 if (!drv || !drv->writeext)
119 for (i = 0; i < ofcfg->grpsz; i++) {
120 val[i] = dev_read_u32_default(dev, ofcfg->grp[i].name, ~0);
121 offset = ofcfg->grp[i].off;
123 /* Default register value for KSZ9021 */
124 regval |= ofcfg->grp[i].dflt << offset;
126 changed = 1; /* Value was changed in OF */
127 /* Calculate the register value and fix corner cases */
128 if (val[i] > ps_to_regval * 0xf) {
129 max = (1 << ofcfg->grp[i].size) - 1;
130 regval |= max << offset;
132 regval |= (val[i] / ps_to_regval) << offset;
140 return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
143 static int ksz9021_of_config(struct phy_device *phydev)
145 struct ksz90x1_ofcfg ofcfg[] = {
146 { MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
147 { MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
148 { MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
152 for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
153 ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
161 static int ksz9031_of_config(struct phy_device *phydev)
163 struct ksz90x1_ofcfg ofcfg[] = {
164 { MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
165 { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
166 { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
167 { MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
171 for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
172 ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
180 static int ksz9031_center_flp_timing(struct phy_device *phydev)
182 struct phy_driver *drv = phydev->drv;
185 if (!drv || !drv->writeext)
188 ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
192 ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
196 #else /* !CONFIG_DM_ETH */
197 static int ksz9021_of_config(struct phy_device *phydev)
202 static int ksz9031_of_config(struct phy_device *phydev)
207 static int ksz9031_center_flp_timing(struct phy_device *phydev)
216 int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
218 /* extended registers */
219 phy_write(phydev, MDIO_DEVAD_NONE,
220 MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
221 return phy_write(phydev, MDIO_DEVAD_NONE,
222 MII_KSZ9021_EXTENDED_DATAW, val);
225 int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
227 /* extended registers */
228 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
229 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
233 static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
236 return ksz9021_phy_extended_read(phydev, regnum);
239 static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
240 int devaddr, int regnum, u16 val)
242 return ksz9021_phy_extended_write(phydev, regnum, val);
245 static int ksz9021_config(struct phy_device *phydev)
247 unsigned ctrl1000 = 0;
248 const unsigned master = CTRL1000_PREFER_MASTER |
249 CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
250 unsigned features = phydev->drv->features;
253 ret = ksz9021_of_config(phydev);
257 if (env_get("disable_giga"))
258 features &= ~(SUPPORTED_1000baseT_Half |
259 SUPPORTED_1000baseT_Full);
260 /* force master mode for 1000BaseT due to chip errata */
261 if (features & SUPPORTED_1000baseT_Half)
262 ctrl1000 |= ADVERTISE_1000HALF | master;
263 if (features & SUPPORTED_1000baseT_Full)
264 ctrl1000 |= ADVERTISE_1000FULL | master;
265 phydev->advertising = features;
266 phydev->supported = features;
267 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
268 genphy_config_aneg(phydev);
269 genphy_restart_aneg(phydev);
273 static struct phy_driver ksz9021_driver = {
274 .name = "Micrel ksz9021",
277 .features = PHY_GBIT_FEATURES,
278 .config = &ksz9021_config,
279 .startup = &ksz90xx_startup,
280 .shutdown = &genphy_shutdown,
281 .writeext = &ksz9021_phy_extwrite,
282 .readext = &ksz9021_phy_extread,
288 int ksz9031_phy_extended_write(struct phy_device *phydev,
289 int devaddr, int regnum, u16 mode, u16 val)
291 /*select register addr for mmd*/
292 phy_write(phydev, MDIO_DEVAD_NONE,
293 MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
294 /*select register for mmd*/
295 phy_write(phydev, MDIO_DEVAD_NONE,
296 MII_KSZ9031_MMD_REG_DATA, regnum);
298 phy_write(phydev, MDIO_DEVAD_NONE,
299 MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
301 return phy_write(phydev, MDIO_DEVAD_NONE,
302 MII_KSZ9031_MMD_REG_DATA, val);
305 int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
306 int regnum, u16 mode)
308 phy_write(phydev, MDIO_DEVAD_NONE,
309 MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
310 phy_write(phydev, MDIO_DEVAD_NONE,
311 MII_KSZ9031_MMD_REG_DATA, regnum);
312 phy_write(phydev, MDIO_DEVAD_NONE,
313 MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode));
314 return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
317 static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
320 return ksz9031_phy_extended_read(phydev, devaddr, regnum,
321 MII_KSZ9031_MOD_DATA_NO_POST_INC);
324 static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
325 int devaddr, int regnum, u16 val)
327 return ksz9031_phy_extended_write(phydev, devaddr, regnum,
328 MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
331 static int ksz9031_config(struct phy_device *phydev)
335 ret = ksz9031_of_config(phydev);
338 ret = ksz9031_center_flp_timing(phydev);
342 /* add an option to disable the gigabit feature of this PHY */
343 if (env_get("disable_giga")) {
347 /* disable speed 1000 in features supported by the PHY */
348 features = phydev->drv->features;
349 features &= ~(SUPPORTED_1000baseT_Half |
350 SUPPORTED_1000baseT_Full);
351 phydev->advertising = phydev->supported = features;
353 /* disable speed 1000 in Basic Control Register */
354 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
356 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr);
358 /* disable speed 1000 in 1000Base-T Control Register */
359 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0);
362 genphy_config_aneg(phydev);
363 genphy_restart_aneg(phydev);
368 return genphy_config(phydev);
371 static struct phy_driver ksz9031_driver = {
372 .name = "Micrel ksz9031",
375 .features = PHY_GBIT_FEATURES,
376 .config = &ksz9031_config,
377 .startup = &ksz90xx_startup,
378 .shutdown = &genphy_shutdown,
379 .writeext = &ksz9031_phy_extwrite,
380 .readext = &ksz9031_phy_extread,
383 int phy_micrel_ksz90x1_init(void)
385 phy_register(&ksz9021_driver);
386 phy_register(&ksz9031_driver);