3 * Marvell Semiconductor <www.marvell.com>
4 * Prafulla Wadaskar <prafulla@marvell.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
27 #include "mv88e61xx.h"
29 #ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
31 * The Switch support two modes of operation
32 * 1. single chip mode and
34 * Refer section 9.2 &9.3 in chip datasheet-02 for more details
36 * By default single chip mode is configured
37 * multichip mode operation can be configured in board header
39 static int mv88e61xx_busychk_multic(u32 devaddr)
42 u32 timeout = MV88E61XX_PHY_TIMEOUT;
44 /* Poll till SMIBusy bit is clear */
46 miiphy_read(name, devaddr, 0x0, ®);
48 printf("SMI busy timeout\n");
51 } while (reg & (1 << 15));
55 static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data)
60 /* command to read PHY dev address */
61 if (!miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
62 printf("Error..could not read PHY dev address\n");
65 mv88e61xx_busychk_multic(mii_dev_addr);
66 /* Write data to Switch indirect data register */
67 miiphy_write(name, mii_dev_addr, 0x1, data);
68 /* Write command to Switch indirect command register (write) */
69 miiphy_write(name, mii_dev_addr, 0x0,
70 reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 <<
74 static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data)
79 /* command to read PHY dev address */
80 if (!miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
81 printf("Error..could not read PHY dev address\n");
84 mv88e61xx_busychk_multic(mii_dev_addr);
85 /* Write command to Switch indirect command register (read) */
86 miiphy_write(name, mii_dev_addr, 0x0,
87 reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 <<
89 mv88e61xx_busychk_multic(mii_dev_addr);
90 /* Read data from Switch indirect data register */
91 miiphy_read(name, mii_dev_addr, 0x1, (u16 *) & data);
93 #endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
95 static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig,
96 u32 max_prtnum, u32 ports_ofs)
100 char *name = swconfig->name;
101 u32 cpu_port = swconfig->cpuport;
102 u32 port_mask = swconfig->ports_enabled;
103 enum mv88e61xx_cfg_vlan vlancfg = swconfig->vlancfg;
105 /* be sure all ports are disabled */
106 for (prt = 0; prt < max_prtnum; prt++) {
107 RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, ®);
109 WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, reg);
111 if (!(cpu_port & (1 << prt)))
113 /* Set CPU port VID to 0x1 */
114 RD_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, ®);
117 WR_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, reg);
120 /* Setting Port default priority for all ports to zero */
121 for (prt = 0; prt < max_prtnum; prt++) {
122 RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, ®);
124 WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, reg);
126 /* Setting VID and VID map for all ports except CPU port */
127 for (prt = 0; prt < max_prtnum; prt++) {
128 /* only for enabled ports */
129 if ((1 << prt) & port_mask) {
131 if ((1 << prt) & cpu_port) {
133 * Set Vlan map table for cpu_port to see
136 RD_PHY(name, (ports_ofs + prt),
137 MV88E61XX_PRT_VMAP_REG, ®);
138 reg &= ~((1 << max_prtnum) - 1);
139 reg |= port_mask & ~(1 << prt);
140 WR_PHY(name, (ports_ofs + prt),
141 MV88E61XX_PRT_VMAP_REG, reg);
145 * set Ports VLAN Mapping.
146 * port prt <--> cpu_port VLAN #prt+1.
148 RD_PHY(name, ports_ofs + prt,
149 MV88E61XX_PRT_VID_REG, ®);
152 WR_PHY(name, ports_ofs + prt,
153 MV88E61XX_PRT_VID_REG, reg);
155 RD_PHY(name, ports_ofs + prt,
156 MV88E61XX_PRT_VMAP_REG, ®);
157 if (vlancfg == MV88E61XX_VLANCFG_DEFAULT) {
159 * all any port can send frames to all other ports
160 * ref: sec 3.2.1.1 of datasheet
164 } else if (vlancfg == MV88E61XX_VLANCFG_ROUTER) {
166 * all other ports can send frames to CPU port only
167 * ref: sec 3.2.1.2 of datasheet
169 reg &= ~((1 << max_prtnum) - 1);
172 WR_PHY(name, ports_ofs + prt,
173 MV88E61XX_PRT_VMAP_REG, reg);
179 * enable only appropriate ports to forwarding mode
180 * and disable the others
182 for (prt = 0; prt < max_prtnum; prt++) {
183 if ((1 << prt) & port_mask) {
184 RD_PHY(name, ports_ofs + prt,
185 MV88E61XX_PRT_CTRL_REG, ®);
187 WR_PHY(name, ports_ofs + prt,
188 MV88E61XX_PRT_CTRL_REG, reg);
191 RD_PHY(name, ports_ofs + prt,
192 MV88E61XX_PRT_CTRL_REG, ®);
194 WR_PHY(name, ports_ofs + prt,
195 MV88E61XX_PRT_CTRL_REG, reg);
201 * Make sure SMIBusy bit cleared before another
202 * SMI operation can take place
204 static int mv88e61xx_busychk(char *name)
207 u32 timeout = MV88E61XX_PHY_TIMEOUT;
209 RD_PHY(name, MV88E61XX_GLB2REG_DEVADR,
210 MV88E61XX_PHY_CMD, (u16 *) & reg);
211 if (timeout-- == 0) {
212 printf("SMI busy timeout\n");
215 } while (reg & 1 << 28); /* busy mask */
220 * Power up the specified port and reset PHY
222 static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 prt)
224 char *name = swconfig->name;
226 /* Write Copper Specific control reg1 (0x14) for-
227 * Enable Phy power up
228 * Energy Detect on (sense&Xmit NLP Periodically
229 * reset other settings default
231 WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x3360);
232 WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
233 MV88E61XX_PHY_CMD, (0x9410 | (prt << 5)));
235 if (mv88e61xx_busychk(name))
238 /* Write PHY ctrl reg (0x0) to apply
239 * Phy reset (set bit 15 low)
240 * reset other default values
242 WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x1140);
243 WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
244 MV88E61XX_PHY_CMD, (0x9400 | (prt << 5)));
246 if (mv88e61xx_busychk(name))
253 * Default Setup for LED[0]_Control (ref: Table 46 Datasheet-3)
254 * is set to "On-1000Mb/s Link, Off Else"
255 * This function sets it to "On-Link, Blink-Activity, Off-NoLink"
257 * This is optional settings may be needed on some boards
258 * to setup PHY LEDs default configuration to detect 10/100/1000Mb/s
261 static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 prt)
263 char *name = swconfig->name;
266 if (swconfig->led_init != MV88E61XX_LED_INIT_EN)
269 /* set page address to 3 */
271 WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
272 WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
273 MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
274 1 << MV88E61XX_MODE_OFST |
275 1 << MV88E61XX_OP_OFST |
276 prt << MV88E61XX_ADDR_OFST | 22));
278 if (mv88e61xx_busychk(name))
281 /* set LED Func Ctrl reg */
282 reg = 1; /* LED[0] On-Link, Blink-Activity, Off-NoLink */
283 WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
284 WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
285 MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
286 1 << MV88E61XX_MODE_OFST |
287 1 << MV88E61XX_OP_OFST |
288 prt << MV88E61XX_ADDR_OFST | 16));
290 if (mv88e61xx_busychk(name))
293 /* set page address to 0 */
295 WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
296 WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
297 MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
298 1 << MV88E61XX_MODE_OFST |
299 1 << MV88E61XX_OP_OFST |
300 prt << MV88E61XX_ADDR_OFST | 22));
302 if (mv88e61xx_busychk(name))
309 * Reverse Transmit polarity for Media Dependent Interface
310 * Pins (MDIP) bits in Copper Specific Control Register 3
311 * (Page 0, Reg 20 for each phy (except cpu port)
312 * Reference: Section 1.1 Switch datasheet-3
314 * This is optional settings may be needed on some boards
315 * for PHY<->magnetics h/w tuning
317 static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 prt)
319 char *name = swconfig->name;
322 if (swconfig->mdip != MV88E61XX_MDIP_REVERSE)
325 reg = 0x0f; /*Reverse MDIP/N[3:0] bits */
326 WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
327 WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
328 MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
329 1 << MV88E61XX_MODE_OFST |
330 1 << MV88E61XX_OP_OFST |
331 prt << MV88E61XX_ADDR_OFST | 20));
333 if (mv88e61xx_busychk(name))
340 * Marvell 88E61XX Switch initialization
342 int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
347 char *name = swconfig->name;
349 if (miiphy_set_current_dev(name)) {
350 printf("%s failed\n", __FUNCTION__);
354 if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) {
355 swconfig->cpuport = (1 << 5);
356 printf("Invalid cpu port config, using default port5\n");
359 RD_PHY(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, ®);
367 /* ports 2,3,4 not available */
368 swconfig->ports_enabled &= 0x023;
371 /* Port based VLANs configuration */
372 if ((swconfig->vlancfg == MV88E61XX_VLANCFG_DEFAULT)
373 || (swconfig->vlancfg == MV88E61XX_VLANCFG_ROUTER))
374 mv88e61xx_port_vlan_config(swconfig, MV88E61XX_MAX_PORTS_NUM,
377 printf("Unsupported mode %s failed\n", __FUNCTION__);
381 if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) {
383 * Enable RGMII delay on Tx and Rx for CPU port
384 * Ref: sec 9.5 of chip datasheet-02
386 WR_PHY(name, MV88E61XX_PRT_OFST + 5,
387 MV88E61XX_RGMII_TIMECTRL_REG, 0x18);
388 WR_PHY(name, MV88E61XX_PRT_OFST + 4,
389 MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
392 for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
393 if (!((1 << prt) & swconfig->cpuport)) {
395 if (mv88361xx_led_init(swconfig, prt))
397 if (mv88361xx_reverse_mdipn(swconfig, prt))
399 if (mv88361xx_powerup(swconfig, prt))
403 /*Program port state */
404 RD_PHY(name, MV88E61XX_PRT_OFST + prt,
405 MV88E61XX_PRT_CTRL_REG, ®);
406 WR_PHY(name, MV88E61XX_PRT_OFST + prt,
407 MV88E61XX_PRT_CTRL_REG,
408 reg | (swconfig->portstate & 0x03));
411 printf("%s Initialized on %s\n", idstr, name);