3 * Marvell Semiconductor <www.marvell.com>
4 * Prafulla Wadaskar <prafulla@marvell.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
30 #define MV88E61XX_CPU_PORT 0x5
32 #define MV88E61XX_PHY_TIMEOUT 100000
34 /* port dev-addr (= port + 0x10) */
35 #define MV88E61XX_PRT_OFST 0x10
37 #define MV88E61XX_PCS_CTRL_REG 0x1
38 #define MV88E61XX_PRT_CTRL_REG 0x4
39 #define MV88E61XX_PRT_VMAP_REG 0x6
40 #define MV88E61XX_PRT_VID_REG 0x7
41 #define MV88E61XX_RGMII_TIMECTRL_REG 0x1A
43 /* global registers dev-addr */
44 #define MV88E61XX_GLBREG_DEVADR 0x1B
45 /* global registers */
46 #define MV88E61XX_SGSR 0x00
47 #define MV88E61XX_SGCR 0x04
49 /* global 2 registers dev-addr */
50 #define MV88E61XX_GLB2REG_DEVADR 0x1C
51 /* global 2 registers */
52 #define MV88E61XX_PHY_CMD 0x18
53 #define MV88E61XX_PHY_DATA 0x19
54 /* global 2 phy commands */
55 #define MV88E61XX_PHY_WRITE_CMD 0x9400
56 #define MV88E61XX_PHY_READ_CMD 0x9800
58 #define MV88E61XX_BUSY_OFST 15
59 #define MV88E61XX_MODE_OFST 12
60 #define MV88E61XX_OP_OFST 10
61 #define MV88E61XX_ADDR_OFST 5
63 #ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
64 static int mv88e61xx_busychk_multic(char *name, u32 devaddr);
65 static void mv88e61xx_switch_write(char *name, u32 phy_adr,
66 u32 reg_ofs, u16 data);
67 static void mv88e61xx_switch_read(char *name, u32 phy_adr,
68 u32 reg_ofs, u16 *data);
69 #define wr_switch_reg mv88e61xx_switch_write
70 #define rd_switch_reg mv88e61xx_switch_read
72 /* switch appears a s simple PHY and can thus use miiphy */
73 #define wr_switch_reg miiphy_write
74 #define rd_switch_reg miiphy_read
75 #endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
77 #endif /* _MV88E61XX_H */