2 * rtl8169.c : U-Boot driver for the RealTek RTL8169
4 * Masami Komiya (mkomiya@sonare.it)
6 * Most part is taken from r8169.c of etherboot
10 /**************************************************************************
11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
12 * Written 2003 by Timothy Legge <tlegge@rogers.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 * Portions of this code based on:
29 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
30 * for Linux kernel 2.4.x.
32 * Written 2002 ShuChen <shuchen@realtek.com.tw>
33 * See Linux Driver for full information
35 * Linux Driver Version 1.27a, 10.02.2002
38 * Jean Chen of RealTek Semiconductor Corp. for
39 * providing the evaluation NIC used to develop
40 * this driver. RealTek's support for Etherboot
46 * v1.0 11-26-2003 timlegge Initial port of Linux driver
47 * v1.5 01-17-2004 timlegge Initial driver output cleanup
49 * Indent Options: indent -kr -i8
50 ***************************************************************************/
52 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
53 * Modified to use le32_to_cpu and cpu_to_le32 properly
62 #undef DEBUG_RTL8169_TX
63 #undef DEBUG_RTL8169_RX
65 #define drv_version "v1.5"
66 #define drv_date "01-17-2004"
70 /* Condensed operations for readability. */
71 #define currticks() get_timer(0)
75 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
77 /* MAC address length*/
78 #define MAC_ADDR_LEN 6
80 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
81 #define MAX_ETH_FRAME_SIZE 1536
83 #define TX_FIFO_THRESH 256 /* In bytes */
85 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
86 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
87 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
88 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
89 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
90 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
92 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
93 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
94 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
95 #define RX_BUF_LEN 8192
97 #define RTL_MIN_IO_SIZE 0x80
98 #define TX_TIMEOUT (6*HZ)
100 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
101 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
102 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
103 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
104 #define RTL_R8(reg) readb (ioaddr + (reg))
105 #define RTL_R16(reg) readw (ioaddr + (reg))
106 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
108 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE
109 #define ETH_ALEN MAC_ADDR_LEN
112 enum RTL8169_registers {
113 MAC0 = 0, /* Ethernet hardware address. */
114 MAR0 = 8, /* Multicast filter. */
115 TxDescStartAddrLow = 0x20,
116 TxDescStartAddrHigh = 0x24,
117 TxHDescStartAddrLow = 0x28,
118 TxHDescStartAddrHigh = 0x2c,
143 RxDescStartAddrLow = 0xE4,
144 RxDescStartAddrHigh = 0xE8,
147 FuncEventMask = 0xF4,
148 FuncPresetState = 0xF8,
149 FuncForceEvent = 0xFC,
152 enum RTL8169_register_content {
153 /*InterruptStatusBits */
157 TxDescUnavail = 0x80,
180 Cfg9346_Unlock = 0xC0,
185 AcceptBroadcast = 0x08,
186 AcceptMulticast = 0x04,
188 AcceptAllPhys = 0x01,
195 TxInterFrameGapShift = 24,
196 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
198 /*rtl8169_PHYstatus */
208 /*GIGABIT_PHY_registers */
211 PHY_AUTO_NEGO_REG = 4,
212 PHY_1000_CTRL_REG = 9,
214 /*GIGABIT_PHY_REG_BIT */
215 PHY_Restart_Auto_Nego = 0x0200,
216 PHY_Enable_Auto_Nego = 0x1000,
218 /* PHY_STAT_REG = 1; */
219 PHY_Auto_Nego_Comp = 0x0020,
221 /* PHY_AUTO_NEGO_REG = 4; */
222 PHY_Cap_10_Half = 0x0020,
223 PHY_Cap_10_Full = 0x0040,
224 PHY_Cap_100_Half = 0x0080,
225 PHY_Cap_100_Full = 0x0100,
227 /* PHY_1000_CTRL_REG = 9; */
228 PHY_Cap_1000_Full = 0x0200,
240 TBILinkOK = 0x02000000,
245 u8 version; /* depend on RTL8169 docs */
246 u32 RxConfigMask; /* should clear the bits supported by this chip */
247 } rtl_chip_info[] = {
248 {"RTL-8169", 0x00, 0xff7e1880,},
249 {"RTL-8169", 0x04, 0xff7e1880,},
250 {"RTL-8169", 0x00, 0xff7e1880,},
251 {"RTL-8169s/8110s", 0x02, 0xff7e1880,},
252 {"RTL-8169s/8110s", 0x04, 0xff7e1880,},
253 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
254 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
255 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
256 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
257 {"RTL-8101e", 0x34, 0xff7e1880,},
258 {"RTL-8100e", 0x32, 0xff7e1880,},
261 enum _DescStatusBit {
282 /* Define the TX Descriptor */
283 static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256];
284 /* __attribute__ ((aligned(256))); */
286 /* Create a static buffer of size RX_BUF_SZ for each
287 TX Descriptor. All descriptors point to a
288 part of this buffer */
289 static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE];
291 /* Define the RX Descriptor */
292 static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256];
293 /* __attribute__ ((aligned(256))); */
295 /* Create a static buffer of size RX_BUF_SZ for each
296 RX Descriptor All descriptors point to a
297 part of this buffer */
298 static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE];
300 struct rtl8169_private {
301 void *mmio_addr; /* memory map physical address */
303 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
304 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
305 unsigned long dirty_tx;
306 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */
307 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */
308 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
309 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
310 unsigned char *RxBufferRings; /* Index of Rx Buffer */
311 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
312 unsigned char *Tx_skbuff[NUM_TX_DESC];
315 static struct rtl8169_private *tpc;
317 static const u16 rtl8169_intr_mask =
318 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr |
320 static const unsigned int rtl8169_rx_config =
321 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
323 static struct pci_device_id supported[] = {
324 {PCI_VENDOR_ID_REALTEK, 0x8167},
325 {PCI_VENDOR_ID_REALTEK, 0x8169},
329 void mdio_write(int RegAddr, int value)
333 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
336 for (i = 2000; i > 0; i--) {
337 /* Check if the RTL8169 has completed writing to the specified MII register */
338 if (!(RTL_R32(PHYAR) & 0x80000000)) {
346 int mdio_read(int RegAddr)
350 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
353 for (i = 2000; i > 0; i--) {
354 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
355 if (RTL_R32(PHYAR) & 0x80000000) {
356 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
365 static int rtl8169_init_board(struct eth_device *dev)
371 printf ("%s\n", __FUNCTION__);
373 ioaddr = dev->iobase;
375 /* Soft reset the chip. */
376 RTL_W8(ChipCmd, CmdReset);
378 /* Check that the chip has finished the reset. */
379 for (i = 1000; i > 0; i--)
380 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
385 /* identify chip attached to board */
386 tmp = RTL_R32(TxConfig);
387 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
389 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
390 if (tmp == rtl_chip_info[i].version) {
396 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
397 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name);
398 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
405 /**************************************************************************
406 RECV - Receive a frame
407 ***************************************************************************/
408 static int rtl_recv(struct eth_device *dev)
410 /* return true if there's an ethernet packet ready to read */
411 /* nic->packet should contain data on return */
412 /* nic->packetlen should contain length of data */
416 #ifdef DEBUG_RTL8169_RX
417 printf ("%s\n", __FUNCTION__);
419 ioaddr = dev->iobase;
421 cur_rx = tpc->cur_rx;
422 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
423 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
424 unsigned char rxdata[RX_BUF_LEN];
425 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
426 status) & 0x00001FFF) - 4;
428 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
429 NetReceive(rxdata, length);
431 if (cur_rx == NUM_RX_DESC - 1)
432 tpc->RxDescArray[cur_rx].status =
433 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
435 tpc->RxDescArray[cur_rx].status =
436 cpu_to_le32(OWNbit + RX_BUF_SIZE);
437 tpc->RxDescArray[cur_rx].buf_addr =
438 cpu_to_le32((unsigned long)tpc->RxBufferRing[cur_rx]);
442 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
443 tpc->cur_rx = cur_rx;
447 ushort sts = RTL_R8(IntrStatus);
448 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
449 udelay(100); /* wait */
451 tpc->cur_rx = cur_rx;
452 return (0); /* initially as this is called to flush the input */
456 /**************************************************************************
457 SEND - Transmit a frame
458 ***************************************************************************/
459 static int rtl_send(struct eth_device *dev, volatile void *packet, int length)
461 /* send the packet to destination */
465 int entry = tpc->cur_tx % NUM_TX_DESC;
469 #ifdef DEBUG_RTL8169_TX
470 int stime = currticks();
471 printf ("%s\n", __FUNCTION__);
472 printf("sending %d bytes\n", len);
475 ioaddr = dev->iobase;
477 /* point to the current txb incase multiple tx_rings are used */
478 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
479 memcpy(ptxb, (char *)packet, (int)length);
481 while (len < ETH_ZLEN)
484 tpc->TxDescArray[entry].buf_Haddr = 0;
485 tpc->TxDescArray[entry].buf_addr = cpu_to_le32((unsigned long)ptxb);
486 if (entry != (NUM_TX_DESC - 1)) {
487 tpc->TxDescArray[entry].status =
488 cpu_to_le32((OWNbit | FSbit | LSbit) |
489 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
491 tpc->TxDescArray[entry].status =
492 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
493 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
495 RTL_W8(TxPoll, 0x40); /* set polling bit */
498 to = currticks() + TX_TIMEOUT;
499 while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
500 && (currticks() < to)); /* wait */
502 if (currticks() >= to) {
503 #ifdef DEBUG_RTL8169_TX
504 puts ("tx timeout/error\n");
505 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
509 #ifdef DEBUG_RTL8169_TX
514 /* Delay to make net console (nc) work properly */
519 static void rtl8169_set_rx_mode(struct eth_device *dev)
521 u32 mc_filter[2]; /* Multicast hash filter */
526 printf ("%s\n", __FUNCTION__);
530 /* Too many to filter perfectly -- accept all multicasts. */
531 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
532 mc_filter[1] = mc_filter[0] = 0xffffffff;
534 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
535 rtl_chip_info[tpc->chipset].RxConfigMask);
537 RTL_W32(RxConfig, tmp);
538 RTL_W32(MAR0 + 0, mc_filter[0]);
539 RTL_W32(MAR0 + 4, mc_filter[1]);
542 static void rtl8169_hw_start(struct eth_device *dev)
547 int stime = currticks();
548 printf ("%s\n", __FUNCTION__);
552 /* Soft reset the chip. */
553 RTL_W8(ChipCmd, CmdReset);
555 /* Check that the chip has finished the reset. */
556 for (i = 1000; i > 0; i--) {
557 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
564 RTL_W8(Cfg9346, Cfg9346_Unlock);
566 /* RTL-8169sb/8110sb or previous version */
567 if (tpc->chipset <= 5)
568 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
570 RTL_W8(EarlyTxThres, EarlyTxThld);
572 /* For gigabit rtl8169 */
573 RTL_W16(RxMaxSize, RxPacketMaxSize);
575 /* Set Rx Config register */
576 i = rtl8169_rx_config | (RTL_R32(RxConfig) &
577 rtl_chip_info[tpc->chipset].RxConfigMask);
578 RTL_W32(RxConfig, i);
580 /* Set DMA burst size and Interframe Gap Time */
581 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
582 (InterFrameGap << TxInterFrameGapShift));
587 RTL_W32(TxDescStartAddrLow, (unsigned long)tpc->TxDescArray);
588 RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
589 RTL_W32(RxDescStartAddrLow, (unsigned long)tpc->RxDescArray);
590 RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
592 /* RTL-8169sc/8110sc or later version */
593 if (tpc->chipset > 5)
594 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
596 RTL_W8(Cfg9346, Cfg9346_Lock);
599 RTL_W32(RxMissed, 0);
601 rtl8169_set_rx_mode(dev);
603 /* no early-rx interrupts */
604 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
607 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
611 static void rtl8169_init_ring(struct eth_device *dev)
616 int stime = currticks();
617 printf ("%s\n", __FUNCTION__);
623 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
624 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
626 for (i = 0; i < NUM_TX_DESC; i++) {
627 tpc->Tx_skbuff[i] = &txb[i];
630 for (i = 0; i < NUM_RX_DESC; i++) {
631 if (i == (NUM_RX_DESC - 1))
632 tpc->RxDescArray[i].status =
633 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
635 tpc->RxDescArray[i].status =
636 cpu_to_le32(OWNbit + RX_BUF_SIZE);
638 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
639 tpc->RxDescArray[i].buf_addr =
640 cpu_to_le32((unsigned long)tpc->RxBufferRing[i]);
644 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
648 /**************************************************************************
649 RESET - Finish setting up the ethernet interface
650 ***************************************************************************/
651 static int rtl_reset(struct eth_device *dev, bd_t *bis)
656 int stime = currticks();
657 printf ("%s\n", __FUNCTION__);
660 tpc->TxDescArrays = tx_ring;
661 /* Tx Desscriptor needs 256 bytes alignment; */
662 tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays +
665 tpc->RxDescArrays = rx_ring;
666 /* Rx Desscriptor needs 256 bytes alignment; */
667 tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays +
670 rtl8169_init_ring(dev);
671 rtl8169_hw_start(dev);
672 /* Construct a perfect filter frame with the mac address as first match
673 * and broadcast for all others */
674 for (i = 0; i < 192; i++)
677 txb[0] = dev->enetaddr[0];
678 txb[1] = dev->enetaddr[1];
679 txb[2] = dev->enetaddr[2];
680 txb[3] = dev->enetaddr[3];
681 txb[4] = dev->enetaddr[4];
682 txb[5] = dev->enetaddr[5];
685 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
690 /**************************************************************************
691 HALT - Turn off ethernet interface
692 ***************************************************************************/
693 static void rtl_halt(struct eth_device *dev)
698 printf ("%s\n", __FUNCTION__);
701 ioaddr = dev->iobase;
703 /* Stop the chip's Tx and Rx DMA processes. */
704 RTL_W8(ChipCmd, 0x00);
706 /* Disable interrupts by clearing the interrupt mask. */
707 RTL_W16(IntrMask, 0x0000);
709 RTL_W32(RxMissed, 0);
711 tpc->TxDescArrays = NULL;
712 tpc->RxDescArrays = NULL;
713 tpc->TxDescArray = NULL;
714 tpc->RxDescArray = NULL;
715 for (i = 0; i < NUM_RX_DESC; i++) {
716 tpc->RxBufferRing[i] = NULL;
720 /**************************************************************************
721 INIT - Look for an adapter, this routine's visible to the outside
722 ***************************************************************************/
724 #define board_found 1
726 static int rtl_init(struct eth_device *dev, bd_t *bis)
728 static int board_idx = -1;
729 static int printed_version = 0;
731 int option = -1, Cap10_100 = 0, Cap1000 = 0;
734 printf ("%s\n", __FUNCTION__);
737 ioaddr = dev->iobase;
743 /* point to private storage */
746 rc = rtl8169_init_board(dev);
750 /* Get MAC address. FIXME: read EEPROM */
751 for (i = 0; i < MAC_ADDR_LEN; i++)
752 bis->bi_enetaddr[i] = dev->enetaddr[i] = RTL_R8(MAC0 + i);
755 printf("chipset = %d\n", tpc->chipset);
756 printf("MAC Address");
757 for (i = 0; i < MAC_ADDR_LEN; i++)
758 printf(":%02x", dev->enetaddr[i]);
763 /* Print out some hardware info */
764 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr);
767 /* if TBI is not endbled */
768 if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
769 int val = mdio_read(PHY_AUTO_NEGO_REG);
771 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
772 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
775 printf("%s: Force-mode Enabled.\n", dev->name);
777 Cap10_100 = 0, Cap1000 = 0;
780 Cap10_100 = PHY_Cap_10_Half;
781 Cap1000 = PHY_Cap_Null;
784 Cap10_100 = PHY_Cap_10_Full;
785 Cap1000 = PHY_Cap_Null;
788 Cap10_100 = PHY_Cap_100_Half;
789 Cap1000 = PHY_Cap_Null;
792 Cap10_100 = PHY_Cap_100_Full;
793 Cap1000 = PHY_Cap_Null;
796 Cap10_100 = PHY_Cap_Null;
797 Cap1000 = PHY_Cap_1000_Full;
802 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
803 mdio_write(PHY_1000_CTRL_REG, Cap1000);
806 printf("%s: Auto-negotiation Enabled.\n",
809 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
810 mdio_write(PHY_AUTO_NEGO_REG,
811 PHY_Cap_10_Half | PHY_Cap_10_Full |
812 PHY_Cap_100_Half | PHY_Cap_100_Full |
815 /* enable 1000 Full Mode */
816 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
820 /* Enable auto-negotiation and restart auto-nigotiation */
821 mdio_write(PHY_CTRL_REG,
822 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
825 /* wait for auto-negotiation process */
826 for (i = 10000; i > 0; i--) {
827 /* check if auto-negotiation complete */
828 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
830 option = RTL_R8(PHYstatus);
831 if (option & _1000bpsF) {
833 printf("%s: 1000Mbps Full-duplex operation.\n",
838 printf("%s: %sMbps %s-duplex operation.\n",
840 (option & _100bps) ? "100" :
842 (option & FullDup) ? "Full" :
850 } /* end for-loop to wait for auto-negotiation process */
856 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
858 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
865 int rtl8169_initialize(bd_t *bis)
869 struct eth_device *dev;
875 if ((devno = pci_find_devices(supported, idx++)) < 0)
878 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
881 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
883 dev = (struct eth_device *)malloc(sizeof *dev);
885 sprintf (dev->name, "RTL8169#%d", card_number);
887 dev->priv = (void *) devno;
888 dev->iobase = (int)pci_mem_to_phys(devno, iobase);
890 dev->init = rtl_reset;
891 dev->halt = rtl_halt;
892 dev->send = rtl_send;
893 dev->recv = rtl_recv;