2 * rtl8169.c : U-Boot driver for the RealTek RTL8169
4 * Masami Komiya (mkomiya@sonare.it)
6 * Most part is taken from r8169.c of etherboot
10 /**************************************************************************
11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
12 * Written 2003 by Timothy Legge <tlegge@rogers.com>
14 * SPDX-License-Identifier: GPL-2.0+
16 * Portions of this code based on:
17 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
18 * for Linux kernel 2.4.x.
20 * Written 2002 ShuChen <shuchen@realtek.com.tw>
21 * See Linux Driver for full information
23 * Linux Driver Version 1.27a, 10.02.2002
26 * Jean Chen of RealTek Semiconductor Corp. for
27 * providing the evaluation NIC used to develop
28 * this driver. RealTek's support for Etherboot
34 * v1.0 11-26-2003 timlegge Initial port of Linux driver
35 * v1.5 01-17-2004 timlegge Initial driver output cleanup
37 * Indent Options: indent -kr -i8
38 ***************************************************************************/
40 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
41 * Modified to use le32_to_cpu and cpu_to_le32 properly
51 #undef DEBUG_RTL8169_TX
52 #undef DEBUG_RTL8169_RX
54 #define drv_version "v1.5"
55 #define drv_date "01-17-2004"
59 /* Condensed operations for readability. */
60 #define currticks() get_timer(0)
64 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
66 /* MAC address length*/
67 #define MAC_ADDR_LEN 6
69 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
70 #define MAX_ETH_FRAME_SIZE 1536
72 #define TX_FIFO_THRESH 256 /* In bytes */
74 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
75 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
76 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
77 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
78 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
79 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
81 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
82 #ifdef CONFIG_SYS_RX_ETH_BUFFER
83 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER
85 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
87 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
88 #define RX_BUF_LEN 8192
90 #define RTL_MIN_IO_SIZE 0x80
91 #define TX_TIMEOUT (6*HZ)
93 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
94 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97 #define RTL_R8(reg) readb (ioaddr + (reg))
98 #define RTL_R16(reg) readw (ioaddr + (reg))
99 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
101 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE
102 #define ETH_ALEN MAC_ADDR_LEN
105 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, (pci_addr_t)a)
106 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, (phys_addr_t)a)
108 enum RTL8169_registers {
109 MAC0 = 0, /* Ethernet hardware address. */
110 MAR0 = 8, /* Multicast filter. */
111 TxDescStartAddrLow = 0x20,
112 TxDescStartAddrHigh = 0x24,
113 TxHDescStartAddrLow = 0x28,
114 TxHDescStartAddrHigh = 0x2c,
139 RxDescStartAddrLow = 0xE4,
140 RxDescStartAddrHigh = 0xE8,
143 FuncEventMask = 0xF4,
144 FuncPresetState = 0xF8,
145 FuncForceEvent = 0xFC,
148 enum RTL8169_register_content {
149 /*InterruptStatusBits */
153 TxDescUnavail = 0x80,
176 Cfg9346_Unlock = 0xC0,
181 AcceptBroadcast = 0x08,
182 AcceptMulticast = 0x04,
184 AcceptAllPhys = 0x01,
191 TxInterFrameGapShift = 24,
192 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
194 /*rtl8169_PHYstatus */
204 /*GIGABIT_PHY_registers */
207 PHY_AUTO_NEGO_REG = 4,
208 PHY_1000_CTRL_REG = 9,
210 /*GIGABIT_PHY_REG_BIT */
211 PHY_Restart_Auto_Nego = 0x0200,
212 PHY_Enable_Auto_Nego = 0x1000,
214 /* PHY_STAT_REG = 1; */
215 PHY_Auto_Nego_Comp = 0x0020,
217 /* PHY_AUTO_NEGO_REG = 4; */
218 PHY_Cap_10_Half = 0x0020,
219 PHY_Cap_10_Full = 0x0040,
220 PHY_Cap_100_Half = 0x0080,
221 PHY_Cap_100_Full = 0x0100,
223 /* PHY_1000_CTRL_REG = 9; */
224 PHY_Cap_1000_Full = 0x0200,
236 TBILinkOK = 0x02000000,
241 u8 version; /* depend on RTL8169 docs */
242 u32 RxConfigMask; /* should clear the bits supported by this chip */
243 } rtl_chip_info[] = {
244 {"RTL-8169", 0x00, 0xff7e1880,},
245 {"RTL-8169", 0x04, 0xff7e1880,},
246 {"RTL-8169", 0x00, 0xff7e1880,},
247 {"RTL-8169s/8110s", 0x02, 0xff7e1880,},
248 {"RTL-8169s/8110s", 0x04, 0xff7e1880,},
249 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
250 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
251 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
252 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
253 {"RTL-8168d/8111d", 0x28, 0xff7e1880,},
254 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
255 {"RTL-8101e", 0x34, 0xff7e1880,},
256 {"RTL-8100e", 0x32, 0xff7e1880,},
259 enum _DescStatusBit {
280 /* Define the TX Descriptor */
281 static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256];
282 /* __attribute__ ((aligned(256))); */
284 /* Create a static buffer of size RX_BUF_SZ for each
285 TX Descriptor. All descriptors point to a
286 part of this buffer */
287 static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE];
289 /* Define the RX Descriptor */
290 static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256];
291 /* __attribute__ ((aligned(256))); */
293 /* Create a static buffer of size RX_BUF_SZ for each
294 RX Descriptor All descriptors point to a
295 part of this buffer */
296 static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE];
298 struct rtl8169_private {
299 void *mmio_addr; /* memory map physical address */
301 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
302 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
303 unsigned long dirty_tx;
304 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */
305 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */
306 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
307 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
308 unsigned char *RxBufferRings; /* Index of Rx Buffer */
309 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
310 unsigned char *Tx_skbuff[NUM_TX_DESC];
313 static struct rtl8169_private *tpc;
315 static const u16 rtl8169_intr_mask =
316 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr |
318 static const unsigned int rtl8169_rx_config =
319 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
321 static struct pci_device_id supported[] = {
322 {PCI_VENDOR_ID_REALTEK, 0x8167},
323 {PCI_VENDOR_ID_REALTEK, 0x8168},
324 {PCI_VENDOR_ID_REALTEK, 0x8169},
328 void mdio_write(int RegAddr, int value)
332 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
335 for (i = 2000; i > 0; i--) {
336 /* Check if the RTL8169 has completed writing to the specified MII register */
337 if (!(RTL_R32(PHYAR) & 0x80000000)) {
345 int mdio_read(int RegAddr)
349 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
352 for (i = 2000; i > 0; i--) {
353 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
354 if (RTL_R32(PHYAR) & 0x80000000) {
355 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
364 static int rtl8169_init_board(struct eth_device *dev)
370 printf ("%s\n", __FUNCTION__);
372 ioaddr = dev->iobase;
374 /* Soft reset the chip. */
375 RTL_W8(ChipCmd, CmdReset);
377 /* Check that the chip has finished the reset. */
378 for (i = 1000; i > 0; i--)
379 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
384 /* identify chip attached to board */
385 tmp = RTL_R32(TxConfig);
386 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
388 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
389 if (tmp == rtl_chip_info[i].version) {
395 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
396 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name);
397 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
405 * Cache maintenance functions. These are simple wrappers around the more
406 * general purpose flush_cache() and invalidate_dcache_range() functions.
409 static void rtl_inval_rx_desc(struct RxDesc *desc)
411 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
412 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
414 invalidate_dcache_range(start, end);
417 static void rtl_flush_rx_desc(struct RxDesc *desc)
419 flush_cache((unsigned long)desc, sizeof(*desc));
422 static void rtl_inval_tx_desc(struct TxDesc *desc)
424 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
425 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
427 invalidate_dcache_range(start, end);
430 static void rtl_flush_tx_desc(struct TxDesc *desc)
432 flush_cache((unsigned long)desc, sizeof(*desc));
435 static void rtl_inval_buffer(void *buf, size_t size)
437 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
438 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
440 invalidate_dcache_range(start, end);
443 static void rtl_flush_buffer(void *buf, size_t size)
445 flush_cache((unsigned long)buf, size);
448 /**************************************************************************
449 RECV - Receive a frame
450 ***************************************************************************/
451 static int rtl_recv(struct eth_device *dev)
453 /* return true if there's an ethernet packet ready to read */
454 /* nic->packet should contain data on return */
455 /* nic->packetlen should contain length of data */
459 #ifdef DEBUG_RTL8169_RX
460 printf ("%s\n", __FUNCTION__);
462 ioaddr = dev->iobase;
464 cur_rx = tpc->cur_rx;
466 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
468 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
469 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
470 unsigned char rxdata[RX_BUF_LEN];
471 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
472 status) & 0x00001FFF) - 4;
474 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
475 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
477 if (cur_rx == NUM_RX_DESC - 1)
478 tpc->RxDescArray[cur_rx].status =
479 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
481 tpc->RxDescArray[cur_rx].status =
482 cpu_to_le32(OWNbit + RX_BUF_SIZE);
483 tpc->RxDescArray[cur_rx].buf_addr =
484 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx]));
485 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
487 NetReceive(rxdata, length);
491 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
492 tpc->cur_rx = cur_rx;
496 ushort sts = RTL_R8(IntrStatus);
497 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
498 udelay(100); /* wait */
500 tpc->cur_rx = cur_rx;
501 return (0); /* initially as this is called to flush the input */
505 /**************************************************************************
506 SEND - Transmit a frame
507 ***************************************************************************/
508 static int rtl_send(struct eth_device *dev, void *packet, int length)
510 /* send the packet to destination */
514 int entry = tpc->cur_tx % NUM_TX_DESC;
518 #ifdef DEBUG_RTL8169_TX
519 int stime = currticks();
520 printf ("%s\n", __FUNCTION__);
521 printf("sending %d bytes\n", len);
524 ioaddr = dev->iobase;
526 /* point to the current txb incase multiple tx_rings are used */
527 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
528 memcpy(ptxb, (char *)packet, (int)length);
529 rtl_flush_buffer(ptxb, length);
531 while (len < ETH_ZLEN)
534 tpc->TxDescArray[entry].buf_Haddr = 0;
535 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(bus_to_phys(ptxb));
536 if (entry != (NUM_TX_DESC - 1)) {
537 tpc->TxDescArray[entry].status =
538 cpu_to_le32((OWNbit | FSbit | LSbit) |
539 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
541 tpc->TxDescArray[entry].status =
542 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
543 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
545 rtl_flush_tx_desc(&tpc->TxDescArray[entry]);
546 RTL_W8(TxPoll, 0x40); /* set polling bit */
549 to = currticks() + TX_TIMEOUT;
551 rtl_inval_tx_desc(&tpc->TxDescArray[entry]);
552 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
553 && (currticks() < to)); /* wait */
555 if (currticks() >= to) {
556 #ifdef DEBUG_RTL8169_TX
557 puts("tx timeout/error\n");
558 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
562 #ifdef DEBUG_RTL8169_TX
567 /* Delay to make net console (nc) work properly */
572 static void rtl8169_set_rx_mode(struct eth_device *dev)
574 u32 mc_filter[2]; /* Multicast hash filter */
579 printf ("%s\n", __FUNCTION__);
583 /* Too many to filter perfectly -- accept all multicasts. */
584 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
585 mc_filter[1] = mc_filter[0] = 0xffffffff;
587 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
588 rtl_chip_info[tpc->chipset].RxConfigMask);
590 RTL_W32(RxConfig, tmp);
591 RTL_W32(MAR0 + 0, mc_filter[0]);
592 RTL_W32(MAR0 + 4, mc_filter[1]);
595 static void rtl8169_hw_start(struct eth_device *dev)
600 int stime = currticks();
601 printf ("%s\n", __FUNCTION__);
605 /* Soft reset the chip. */
606 RTL_W8(ChipCmd, CmdReset);
608 /* Check that the chip has finished the reset. */
609 for (i = 1000; i > 0; i--) {
610 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
617 RTL_W8(Cfg9346, Cfg9346_Unlock);
619 /* RTL-8169sb/8110sb or previous version */
620 if (tpc->chipset <= 5)
621 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
623 RTL_W8(EarlyTxThres, EarlyTxThld);
625 /* For gigabit rtl8169 */
626 RTL_W16(RxMaxSize, RxPacketMaxSize);
628 /* Set Rx Config register */
629 i = rtl8169_rx_config | (RTL_R32(RxConfig) &
630 rtl_chip_info[tpc->chipset].RxConfigMask);
631 RTL_W32(RxConfig, i);
633 /* Set DMA burst size and Interframe Gap Time */
634 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
635 (InterFrameGap << TxInterFrameGapShift));
640 RTL_W32(TxDescStartAddrLow, bus_to_phys(tpc->TxDescArray));
641 RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
642 RTL_W32(RxDescStartAddrLow, bus_to_phys(tpc->RxDescArray));
643 RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
645 /* RTL-8169sc/8110sc or later version */
646 if (tpc->chipset > 5)
647 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
649 RTL_W8(Cfg9346, Cfg9346_Lock);
652 RTL_W32(RxMissed, 0);
654 rtl8169_set_rx_mode(dev);
656 /* no early-rx interrupts */
657 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
660 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
664 static void rtl8169_init_ring(struct eth_device *dev)
669 int stime = currticks();
670 printf ("%s\n", __FUNCTION__);
676 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
677 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
679 for (i = 0; i < NUM_TX_DESC; i++) {
680 tpc->Tx_skbuff[i] = &txb[i];
683 for (i = 0; i < NUM_RX_DESC; i++) {
684 if (i == (NUM_RX_DESC - 1))
685 tpc->RxDescArray[i].status =
686 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
688 tpc->RxDescArray[i].status =
689 cpu_to_le32(OWNbit + RX_BUF_SIZE);
691 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
692 tpc->RxDescArray[i].buf_addr =
693 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[i]));
694 rtl_flush_rx_desc(&tpc->RxDescArray[i]);
698 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
702 /**************************************************************************
703 RESET - Finish setting up the ethernet interface
704 ***************************************************************************/
705 static int rtl_reset(struct eth_device *dev, bd_t *bis)
710 int stime = currticks();
711 printf ("%s\n", __FUNCTION__);
714 tpc->TxDescArrays = tx_ring;
715 /* Tx Desscriptor needs 256 bytes alignment; */
716 tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays +
719 tpc->RxDescArrays = rx_ring;
720 /* Rx Desscriptor needs 256 bytes alignment; */
721 tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays +
724 rtl8169_init_ring(dev);
725 rtl8169_hw_start(dev);
726 /* Construct a perfect filter frame with the mac address as first match
727 * and broadcast for all others */
728 for (i = 0; i < 192; i++)
731 txb[0] = dev->enetaddr[0];
732 txb[1] = dev->enetaddr[1];
733 txb[2] = dev->enetaddr[2];
734 txb[3] = dev->enetaddr[3];
735 txb[4] = dev->enetaddr[4];
736 txb[5] = dev->enetaddr[5];
739 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
744 /**************************************************************************
745 HALT - Turn off ethernet interface
746 ***************************************************************************/
747 static void rtl_halt(struct eth_device *dev)
752 printf ("%s\n", __FUNCTION__);
755 ioaddr = dev->iobase;
757 /* Stop the chip's Tx and Rx DMA processes. */
758 RTL_W8(ChipCmd, 0x00);
760 /* Disable interrupts by clearing the interrupt mask. */
761 RTL_W16(IntrMask, 0x0000);
763 RTL_W32(RxMissed, 0);
765 tpc->TxDescArrays = NULL;
766 tpc->RxDescArrays = NULL;
767 tpc->TxDescArray = NULL;
768 tpc->RxDescArray = NULL;
769 for (i = 0; i < NUM_RX_DESC; i++) {
770 tpc->RxBufferRing[i] = NULL;
774 /**************************************************************************
775 INIT - Look for an adapter, this routine's visible to the outside
776 ***************************************************************************/
778 #define board_found 1
780 static int rtl_init(struct eth_device *dev, bd_t *bis)
782 static int board_idx = -1;
784 int option = -1, Cap10_100 = 0, Cap1000 = 0;
787 printf ("%s\n", __FUNCTION__);
790 ioaddr = dev->iobase;
794 /* point to private storage */
797 rc = rtl8169_init_board(dev);
801 /* Get MAC address. FIXME: read EEPROM */
802 for (i = 0; i < MAC_ADDR_LEN; i++)
803 dev->enetaddr[i] = RTL_R8(MAC0 + i);
806 printf("chipset = %d\n", tpc->chipset);
807 printf("MAC Address");
808 for (i = 0; i < MAC_ADDR_LEN; i++)
809 printf(":%02x", dev->enetaddr[i]);
814 /* Print out some hardware info */
815 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr);
818 /* if TBI is not endbled */
819 if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
820 int val = mdio_read(PHY_AUTO_NEGO_REG);
822 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
823 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
826 printf("%s: Force-mode Enabled.\n", dev->name);
828 Cap10_100 = 0, Cap1000 = 0;
831 Cap10_100 = PHY_Cap_10_Half;
832 Cap1000 = PHY_Cap_Null;
835 Cap10_100 = PHY_Cap_10_Full;
836 Cap1000 = PHY_Cap_Null;
839 Cap10_100 = PHY_Cap_100_Half;
840 Cap1000 = PHY_Cap_Null;
843 Cap10_100 = PHY_Cap_100_Full;
844 Cap1000 = PHY_Cap_Null;
847 Cap10_100 = PHY_Cap_Null;
848 Cap1000 = PHY_Cap_1000_Full;
853 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
854 mdio_write(PHY_1000_CTRL_REG, Cap1000);
857 printf("%s: Auto-negotiation Enabled.\n",
860 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
861 mdio_write(PHY_AUTO_NEGO_REG,
862 PHY_Cap_10_Half | PHY_Cap_10_Full |
863 PHY_Cap_100_Half | PHY_Cap_100_Full |
866 /* enable 1000 Full Mode */
867 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
871 /* Enable auto-negotiation and restart auto-nigotiation */
872 mdio_write(PHY_CTRL_REG,
873 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
876 /* wait for auto-negotiation process */
877 for (i = 10000; i > 0; i--) {
878 /* check if auto-negotiation complete */
879 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
881 option = RTL_R8(PHYstatus);
882 if (option & _1000bpsF) {
884 printf("%s: 1000Mbps Full-duplex operation.\n",
889 printf("%s: %sMbps %s-duplex operation.\n",
891 (option & _100bps) ? "100" :
893 (option & FullDup) ? "Full" :
901 } /* end for-loop to wait for auto-negotiation process */
907 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
909 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
916 int rtl8169_initialize(bd_t *bis)
920 struct eth_device *dev;
929 if ((devno = pci_find_devices(supported, idx++)) < 0)
932 pci_read_config_word(devno, PCI_DEVICE_ID, &device);
943 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
946 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
948 dev = (struct eth_device *)malloc(sizeof *dev);
950 printf("Can not allocate memory of rtl8169\n");
954 memset(dev, 0, sizeof(*dev));
955 sprintf (dev->name, "RTL8169#%d", card_number);
957 dev->priv = (void *) devno;
958 dev->iobase = (int)pci_mem_to_phys(devno, iobase);
960 dev->init = rtl_reset;
961 dev->halt = rtl_halt;
962 dev->send = rtl_send;
963 dev->recv = rtl_recv;