2 * sh_eth.c - Driver for Renesas SH7763's ethernet controler.
4 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
5 * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 #include <asm/errno.h>
34 #ifndef CONFIG_SH_ETHER_USE_PORT
35 # error "Please define CONFIG_SH_ETHER_USE_PORT"
37 #ifndef CONFIG_SH_ETHER_PHY_ADDR
38 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
40 #ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK
41 #define flush_cache_wback(addr, len) \
42 dcache_wback_range((u32)addr, (u32)(addr + len - 1))
44 #define flush_cache_wback(...)
47 #define TIMEOUT_CNT 1000
49 int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
51 struct sh_eth_dev *eth = dev->priv;
52 int port = eth->port, ret = 0, timeout;
53 struct sh_eth_info *port_info = ð->port_info[port];
55 if (!packet || len > 0xffff) {
56 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
61 /* packet must be a 4 byte boundary */
62 if ((int)packet & (4 - 1)) {
63 printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
68 /* Update tx descriptor */
69 flush_cache_wback(packet, len);
70 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
71 port_info->tx_desc_cur->td1 = len << 16;
72 /* Must preserve the end of descriptor list indication */
73 if (port_info->tx_desc_cur->td0 & TD_TDLE)
74 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
76 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
78 /* Restart the transmitter if disabled */
79 if (!(inl(EDTRR(port)) & EDTRR_TRNS))
80 outl(EDTRR_TRNS, EDTRR(port));
82 /* Wait until packet is transmitted */
83 timeout = TIMEOUT_CNT;
84 while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--)
88 printf(SHETHER_NAME ": transmit timeout\n");
93 port_info->tx_desc_cur++;
94 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
95 port_info->tx_desc_cur = port_info->tx_desc_base;
102 int sh_eth_recv(struct eth_device *dev)
104 struct sh_eth_dev *eth = dev->priv;
105 int port = eth->port, len = 0;
106 struct sh_eth_info *port_info = ð->port_info[port];
109 /* Check if the rx descriptor is ready */
110 if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
111 /* Check for errors */
112 if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
113 len = port_info->rx_desc_cur->rd1 & 0xffff;
114 packet = (volatile u8 *)
115 ADDR_TO_P2(port_info->rx_desc_cur->rd2);
116 NetReceive(packet, len);
119 /* Make current descriptor available again */
120 if (port_info->rx_desc_cur->rd0 & RD_RDLE)
121 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
123 port_info->rx_desc_cur->rd0 = RD_RACT;
125 /* Point to the next descriptor */
126 port_info->rx_desc_cur++;
127 if (port_info->rx_desc_cur >=
128 port_info->rx_desc_base + NUM_RX_DESC)
129 port_info->rx_desc_cur = port_info->rx_desc_base;
132 /* Restart the receiver if disabled */
133 if (!(inl(EDRRR(port)) & EDRRR_R))
134 outl(EDRRR_R, EDRRR(port));
139 static int sh_eth_reset(struct sh_eth_dev *eth)
141 int port = eth->port;
142 #if defined(CONFIG_CPU_SH7763)
145 /* Start e-dmac transmitter and receiver */
146 outl(EDSR_ENALL, EDSR(port));
148 /* Perform a software reset and wait for it to complete */
149 outl(EDMR_SRST, EDMR(port));
150 for (i = 0; i < TIMEOUT_CNT ; i++) {
151 if (!(inl(EDMR(port)) & EDMR_SRST))
156 if (i == TIMEOUT_CNT) {
157 printf(SHETHER_NAME ": Software reset timeout\n");
163 outl(inl(EDMR(port)) | EDMR_SRST, EDMR(port));
165 outl(inl(EDMR(port)) & ~EDMR_SRST, EDMR(port));
171 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
173 int port = eth->port, i, ret = 0;
175 struct sh_eth_info *port_info = ð->port_info[port];
176 struct tx_desc_s *cur_tx_desc;
179 * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
181 port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
182 sizeof(struct tx_desc_s) +
184 if (!port_info->tx_desc_malloc) {
185 printf(SHETHER_NAME ": malloc failed\n");
190 tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
191 ~(TX_DESC_SIZE - 1));
192 flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
193 /* Make sure we use a P2 address (non-cacheable) */
194 port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
195 port_info->tx_desc_cur = port_info->tx_desc_base;
197 /* Initialize all descriptors */
198 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
199 cur_tx_desc++, i++) {
200 cur_tx_desc->td0 = 0x00;
201 cur_tx_desc->td1 = 0x00;
202 cur_tx_desc->td2 = 0x00;
205 /* Mark the end of the descriptors */
207 cur_tx_desc->td0 |= TD_TDLE;
209 /* Point the controller to the tx descriptor list. Must use physical
211 outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
212 #if defined(CONFIG_CPU_SH7763)
213 outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
214 outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
215 outl(0x01, TDFFR(port));/* Last discriptor bit */
222 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
224 int port = eth->port, i , ret = 0;
225 struct sh_eth_info *port_info = ð->port_info[port];
226 struct rx_desc_s *cur_rx_desc;
231 * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
233 port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
234 sizeof(struct rx_desc_s) +
236 if (!port_info->rx_desc_malloc) {
237 printf(SHETHER_NAME ": malloc failed\n");
242 tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
243 ~(RX_DESC_SIZE - 1));
244 flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
245 /* Make sure we use a P2 address (non-cacheable) */
246 port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
248 port_info->rx_desc_cur = port_info->rx_desc_base;
251 * Allocate rx data buffers. They must be 32 bytes aligned and in
254 port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31);
255 if (!port_info->rx_buf_malloc) {
256 printf(SHETHER_NAME ": malloc failed\n");
261 tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) &
263 port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
265 /* Initialize all descriptors */
266 for (cur_rx_desc = port_info->rx_desc_base,
267 rx_buf = port_info->rx_buf_base, i = 0;
268 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
269 cur_rx_desc->rd0 = RD_RACT;
270 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
271 cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
274 /* Mark the end of the descriptors */
276 cur_rx_desc->rd0 |= RD_RDLE;
278 /* Point the controller to the rx descriptor list */
279 outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
280 #if defined(CONFIG_CPU_SH7763)
281 outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
282 outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
283 outl(RDFFR_RDLF, RDFFR(port));
289 free(port_info->rx_desc_malloc);
290 port_info->rx_desc_malloc = NULL;
296 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
298 int port = eth->port;
299 struct sh_eth_info *port_info = ð->port_info[port];
301 if (port_info->tx_desc_malloc) {
302 free(port_info->tx_desc_malloc);
303 port_info->tx_desc_malloc = NULL;
307 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
309 int port = eth->port;
310 struct sh_eth_info *port_info = ð->port_info[port];
312 if (port_info->rx_desc_malloc) {
313 free(port_info->rx_desc_malloc);
314 port_info->rx_desc_malloc = NULL;
317 if (port_info->rx_buf_malloc) {
318 free(port_info->rx_buf_malloc);
319 port_info->rx_buf_malloc = NULL;
323 static int sh_eth_desc_init(struct sh_eth_dev *eth)
327 ret = sh_eth_tx_desc_init(eth);
331 ret = sh_eth_rx_desc_init(eth);
337 sh_eth_tx_desc_free(eth);
343 static int sh_eth_phy_config(struct sh_eth_dev *eth)
345 int port = eth->port, ret = 0;
346 struct sh_eth_info *port_info = ð->port_info[port];
347 struct eth_device *dev = port_info->dev;
348 struct phy_device *phydev;
350 phydev = phy_connect(miiphy_get_dev_by_name(dev->name),
351 port_info->phy_addr, dev, PHY_INTERFACE_MODE_MII);
352 port_info->phydev = phydev;
358 static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
360 int port = eth->port, ret = 0;
362 struct sh_eth_info *port_info = ð->port_info[port];
363 struct eth_device *dev = port_info->dev;
364 struct phy_device *phy;
366 /* Configure e-dmac registers */
367 outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port));
368 outl(0, EESIPR(port));
369 outl(0, TRSCER(port));
371 outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
372 outl(RMCR_RST, RMCR(port));
373 #if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
374 outl(0, RPADIR(port));
376 outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));
378 /* Configure e-mac registers */
379 #if defined(CONFIG_CPU_SH7757)
380 outl(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP |
381 ECSIPR_MPDIP | ECSIPR_ICDIP, ECSIPR(port));
383 outl(0, ECSIPR(port));
386 /* Set Mac address */
387 val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
388 dev->enetaddr[2] << 8 | dev->enetaddr[3];
389 outl(val, MAHR(port));
391 val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
392 outl(val, MALR(port));
394 outl(RFLR_RFL_MIN, RFLR(port));
395 #if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
398 #if !defined(CONFIG_CPU_SH7724)
399 outl(APR_AP, APR(port));
400 outl(MPR_MP, MPR(port));
402 #if defined(CONFIG_CPU_SH7763)
403 outl(TPAUSER_TPAUSE, TPAUSER(port));
404 #elif defined(CONFIG_CPU_SH7757)
405 outl(TPAUSER_UNLIMITED, TPAUSER(port));
409 ret = sh_eth_phy_config(eth);
411 printf(SHETHER_NAME ": phy config timeout\n");
414 phy = port_info->phydev;
419 /* Set the transfer speed */
420 if (phy->speed == 100) {
421 printf(SHETHER_NAME ": 100Base/");
422 #ifdef CONFIG_CPU_SH7763
423 outl(GECMR_100B, GECMR(port));
424 #elif defined(CONFIG_CPU_SH7757)
425 outl(1, RTRATE(port));
426 #elif defined(CONFIG_CPU_SH7724)
429 } else if (phy->speed == 10) {
430 printf(SHETHER_NAME ": 10Base/");
431 #ifdef CONFIG_CPU_SH7763
432 outl(GECMR_10B, GECMR(port));
433 #elif defined(CONFIG_CPU_SH7757)
434 outl(0, RTRATE(port));
438 /* Check if full duplex mode is supported by the phy */
441 outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
444 outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port));
453 static void sh_eth_start(struct sh_eth_dev *eth)
456 * Enable the e-dmac receiver only. The transmitter will be enabled when
457 * we have something to transmit
459 outl(EDRRR_R, EDRRR(eth->port));
462 static void sh_eth_stop(struct sh_eth_dev *eth)
464 outl(~EDRRR_R, EDRRR(eth->port));
467 int sh_eth_init(struct eth_device *dev, bd_t *bd)
470 struct sh_eth_dev *eth = dev->priv;
472 ret = sh_eth_reset(eth);
476 ret = sh_eth_desc_init(eth);
480 ret = sh_eth_config(eth, bd);
489 sh_eth_tx_desc_free(eth);
490 sh_eth_rx_desc_free(eth);
496 void sh_eth_halt(struct eth_device *dev)
498 struct sh_eth_dev *eth = dev->priv;
502 int sh_eth_initialize(bd_t *bd)
505 struct sh_eth_dev *eth = NULL;
506 struct eth_device *dev = NULL;
508 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
510 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
515 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
517 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
521 memset(dev, 0, sizeof(struct eth_device));
522 memset(eth, 0, sizeof(struct sh_eth_dev));
524 eth->port = CONFIG_SH_ETHER_USE_PORT;
525 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
527 dev->priv = (void *)eth;
529 dev->init = sh_eth_init;
530 dev->halt = sh_eth_halt;
531 dev->send = sh_eth_send;
532 dev->recv = sh_eth_recv;
533 eth->port_info[eth->port].dev = dev;
535 sprintf(dev->name, SHETHER_NAME);
537 /* Register Device to EtherNet subsystem */
540 bb_miiphy_buses[0].priv = eth;
541 miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);
543 if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
544 puts("Please set MAC address\n");
555 printf(SHETHER_NAME ": Failed\n");
559 /******* for bb_miiphy *******/
560 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
565 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
567 struct sh_eth_dev *eth = bus->priv;
568 int port = eth->port;
570 outl(inl(PIR(port)) | PIR_MMD, PIR(port));
575 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
577 struct sh_eth_dev *eth = bus->priv;
578 int port = eth->port;
580 outl(inl(PIR(port)) & ~PIR_MMD, PIR(port));
585 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
587 struct sh_eth_dev *eth = bus->priv;
588 int port = eth->port;
591 outl(inl(PIR(port)) | PIR_MDO, PIR(port));
593 outl(inl(PIR(port)) & ~PIR_MDO, PIR(port));
598 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
600 struct sh_eth_dev *eth = bus->priv;
601 int port = eth->port;
603 *v = (inl(PIR(port)) & PIR_MDI) >> 3;
608 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
610 struct sh_eth_dev *eth = bus->priv;
611 int port = eth->port;
614 outl(inl(PIR(port)) | PIR_MDC, PIR(port));
616 outl(inl(PIR(port)) & ~PIR_MDC, PIR(port));
621 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
628 struct bb_miiphy_bus bb_miiphy_buses[] = {
631 .init = sh_eth_bb_init,
632 .mdio_active = sh_eth_bb_mdio_active,
633 .mdio_tristate = sh_eth_bb_mdio_tristate,
634 .set_mdio = sh_eth_bb_set_mdio,
635 .get_mdio = sh_eth_bb_get_mdio,
636 .set_mdc = sh_eth_bb_set_mdc,
637 .delay = sh_eth_bb_delay,
640 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);