2 * sh_eth.c - Driver for Renesas SH7763's ethernet controler.
4 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
5 * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 #include <asm/errno.h>
34 #ifndef CONFIG_SH_ETHER_USE_PORT
35 # error "Please define CONFIG_SH_ETHER_USE_PORT"
37 #ifndef CONFIG_SH_ETHER_PHY_ADDR
38 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
40 #ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK
41 #define flush_cache_wback(addr, len) \
42 dcache_wback_range((u32)addr, (u32)(addr + len - 1))
44 #define flush_cache_wback(...)
47 #define SH_ETH_PHY_DELAY 50000
49 int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
51 struct sh_eth_dev *eth = dev->priv;
52 int port = eth->port, ret = 0, timeout;
53 struct sh_eth_info *port_info = ð->port_info[port];
55 if (!packet || len > 0xffff) {
56 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
61 /* packet must be a 4 byte boundary */
62 if ((int)packet & (4 - 1)) {
63 printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
68 /* Update tx descriptor */
69 flush_cache_wback(packet, len);
70 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
71 port_info->tx_desc_cur->td1 = len << 16;
72 /* Must preserve the end of descriptor list indication */
73 if (port_info->tx_desc_cur->td0 & TD_TDLE)
74 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
76 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
78 /* Restart the transmitter if disabled */
79 if (!(inl(EDTRR(port)) & EDTRR_TRNS))
80 outl(EDTRR_TRNS, EDTRR(port));
82 /* Wait until packet is transmitted */
84 while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--)
88 printf(SHETHER_NAME ": transmit timeout\n");
93 port_info->tx_desc_cur++;
94 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
95 port_info->tx_desc_cur = port_info->tx_desc_base;
102 int sh_eth_recv(struct eth_device *dev)
104 struct sh_eth_dev *eth = dev->priv;
105 int port = eth->port, len = 0;
106 struct sh_eth_info *port_info = ð->port_info[port];
109 /* Check if the rx descriptor is ready */
110 if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
111 /* Check for errors */
112 if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
113 len = port_info->rx_desc_cur->rd1 & 0xffff;
114 packet = (volatile u8 *)
115 ADDR_TO_P2(port_info->rx_desc_cur->rd2);
116 NetReceive(packet, len);
119 /* Make current descriptor available again */
120 if (port_info->rx_desc_cur->rd0 & RD_RDLE)
121 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
123 port_info->rx_desc_cur->rd0 = RD_RACT;
125 /* Point to the next descriptor */
126 port_info->rx_desc_cur++;
127 if (port_info->rx_desc_cur >=
128 port_info->rx_desc_base + NUM_RX_DESC)
129 port_info->rx_desc_cur = port_info->rx_desc_base;
132 /* Restart the receiver if disabled */
133 if (!(inl(EDRRR(port)) & EDRRR_R))
134 outl(EDRRR_R, EDRRR(port));
139 #define EDMR_INIT_CNT 1000
140 static int sh_eth_reset(struct sh_eth_dev *eth)
142 int port = eth->port;
143 #if defined(CONFIG_CPU_SH7763)
146 /* Start e-dmac transmitter and receiver */
147 outl(EDSR_ENALL, EDSR(port));
149 /* Perform a software reset and wait for it to complete */
150 outl(EDMR_SRST, EDMR(port));
151 for (i = 0; i < EDMR_INIT_CNT; i++) {
152 if (!(inl(EDMR(port)) & EDMR_SRST))
157 if (i == EDMR_INIT_CNT) {
158 printf(SHETHER_NAME ": Software reset timeout\n");
164 outl(inl(EDMR(port)) | EDMR_SRST, EDMR(port));
166 outl(inl(EDMR(port)) & ~EDMR_SRST, EDMR(port));
172 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
174 int port = eth->port, i, ret = 0;
176 struct sh_eth_info *port_info = ð->port_info[port];
177 struct tx_desc_s *cur_tx_desc;
180 * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
182 port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
183 sizeof(struct tx_desc_s) +
185 if (!port_info->tx_desc_malloc) {
186 printf(SHETHER_NAME ": malloc failed\n");
191 tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
192 ~(TX_DESC_SIZE - 1));
193 flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
194 /* Make sure we use a P2 address (non-cacheable) */
195 port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
196 port_info->tx_desc_cur = port_info->tx_desc_base;
198 /* Initialize all descriptors */
199 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
200 cur_tx_desc++, i++) {
201 cur_tx_desc->td0 = 0x00;
202 cur_tx_desc->td1 = 0x00;
203 cur_tx_desc->td2 = 0x00;
206 /* Mark the end of the descriptors */
208 cur_tx_desc->td0 |= TD_TDLE;
210 /* Point the controller to the tx descriptor list. Must use physical
212 outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
213 #if defined(CONFIG_CPU_SH7763)
214 outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
215 outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
216 outl(0x01, TDFFR(port));/* Last discriptor bit */
223 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
225 int port = eth->port, i , ret = 0;
226 struct sh_eth_info *port_info = ð->port_info[port];
227 struct rx_desc_s *cur_rx_desc;
232 * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
234 port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
235 sizeof(struct rx_desc_s) +
237 if (!port_info->rx_desc_malloc) {
238 printf(SHETHER_NAME ": malloc failed\n");
243 tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
244 ~(RX_DESC_SIZE - 1));
245 flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
246 /* Make sure we use a P2 address (non-cacheable) */
247 port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
249 port_info->rx_desc_cur = port_info->rx_desc_base;
252 * Allocate rx data buffers. They must be 32 bytes aligned and in
255 port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31);
256 if (!port_info->rx_buf_malloc) {
257 printf(SHETHER_NAME ": malloc failed\n");
262 tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) &
264 port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
266 /* Initialize all descriptors */
267 for (cur_rx_desc = port_info->rx_desc_base,
268 rx_buf = port_info->rx_buf_base, i = 0;
269 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
270 cur_rx_desc->rd0 = RD_RACT;
271 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
272 cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
275 /* Mark the end of the descriptors */
277 cur_rx_desc->rd0 |= RD_RDLE;
279 /* Point the controller to the rx descriptor list */
280 outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
281 #if defined(CONFIG_CPU_SH7763)
282 outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
283 outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
284 outl(RDFFR_RDLF, RDFFR(port));
290 free(port_info->rx_desc_malloc);
291 port_info->rx_desc_malloc = NULL;
297 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
299 int port = eth->port;
300 struct sh_eth_info *port_info = ð->port_info[port];
302 if (port_info->tx_desc_malloc) {
303 free(port_info->tx_desc_malloc);
304 port_info->tx_desc_malloc = NULL;
308 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
310 int port = eth->port;
311 struct sh_eth_info *port_info = ð->port_info[port];
313 if (port_info->rx_desc_malloc) {
314 free(port_info->rx_desc_malloc);
315 port_info->rx_desc_malloc = NULL;
318 if (port_info->rx_buf_malloc) {
319 free(port_info->rx_buf_malloc);
320 port_info->rx_buf_malloc = NULL;
324 static int sh_eth_desc_init(struct sh_eth_dev *eth)
328 ret = sh_eth_tx_desc_init(eth);
332 ret = sh_eth_rx_desc_init(eth);
338 sh_eth_tx_desc_free(eth);
344 static int sh_eth_phy_config(struct sh_eth_dev *eth)
346 int port = eth->port, ret = 0;
347 struct sh_eth_info *port_info = ð->port_info[port];
348 struct eth_device *dev = port_info->dev;
349 struct phy_device *phydev;
351 phydev = phy_connect(miiphy_get_dev_by_name(dev->name),
352 port_info->phy_addr, dev, PHY_INTERFACE_MODE_MII);
353 port_info->phydev = phydev;
359 static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
361 int port = eth->port, ret = 0;
363 struct sh_eth_info *port_info = ð->port_info[port];
364 struct eth_device *dev = port_info->dev;
365 struct phy_device *phy;
367 /* Configure e-dmac registers */
368 outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port));
369 outl(0, EESIPR(port));
370 outl(0, TRSCER(port));
372 outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
373 outl(RMCR_RST, RMCR(port));
374 #if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
375 outl(0, RPADIR(port));
377 outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));
379 /* Configure e-mac registers */
380 #if defined(CONFIG_CPU_SH7757)
381 outl(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP |
382 ECSIPR_MPDIP | ECSIPR_ICDIP, ECSIPR(port));
384 outl(0, ECSIPR(port));
387 /* Set Mac address */
388 val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
389 dev->enetaddr[2] << 8 | dev->enetaddr[3];
390 outl(val, MAHR(port));
392 val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
393 outl(val, MALR(port));
395 outl(RFLR_RFL_MIN, RFLR(port));
396 #if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
399 #if !defined(CONFIG_CPU_SH7724)
400 outl(APR_AP, APR(port));
401 outl(MPR_MP, MPR(port));
403 #if defined(CONFIG_CPU_SH7763)
404 outl(TPAUSER_TPAUSE, TPAUSER(port));
405 #elif defined(CONFIG_CPU_SH7757)
406 outl(TPAUSER_UNLIMITED, TPAUSER(port));
410 ret = sh_eth_phy_config(eth);
412 printf(SHETHER_NAME ": phy config timeout\n");
415 phy = port_info->phydev;
420 /* Set the transfer speed */
421 if (phy->speed == 100) {
422 printf(SHETHER_NAME ": 100Base/");
423 #ifdef CONFIG_CPU_SH7763
424 outl(GECMR_100B, GECMR(port));
425 #elif defined(CONFIG_CPU_SH7757)
426 outl(1, RTRATE(port));
427 #elif defined(CONFIG_CPU_SH7724)
430 } else if (phy->speed == 10) {
431 printf(SHETHER_NAME ": 10Base/");
432 #ifdef CONFIG_CPU_SH7763
433 outl(GECMR_10B, GECMR(port));
434 #elif defined(CONFIG_CPU_SH7757)
435 outl(0, RTRATE(port));
439 /* Check if full duplex mode is supported by the phy */
442 outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
445 outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port));
454 static void sh_eth_start(struct sh_eth_dev *eth)
457 * Enable the e-dmac receiver only. The transmitter will be enabled when
458 * we have something to transmit
460 outl(EDRRR_R, EDRRR(eth->port));
463 static void sh_eth_stop(struct sh_eth_dev *eth)
465 outl(~EDRRR_R, EDRRR(eth->port));
468 int sh_eth_init(struct eth_device *dev, bd_t *bd)
471 struct sh_eth_dev *eth = dev->priv;
473 ret = sh_eth_reset(eth);
477 ret = sh_eth_desc_init(eth);
481 ret = sh_eth_config(eth, bd);
490 sh_eth_tx_desc_free(eth);
491 sh_eth_rx_desc_free(eth);
497 void sh_eth_halt(struct eth_device *dev)
499 struct sh_eth_dev *eth = dev->priv;
503 int sh_eth_initialize(bd_t *bd)
506 struct sh_eth_dev *eth = NULL;
507 struct eth_device *dev = NULL;
509 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
511 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
516 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
518 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
522 memset(dev, 0, sizeof(struct eth_device));
523 memset(eth, 0, sizeof(struct sh_eth_dev));
525 eth->port = CONFIG_SH_ETHER_USE_PORT;
526 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
528 dev->priv = (void *)eth;
530 dev->init = sh_eth_init;
531 dev->halt = sh_eth_halt;
532 dev->send = sh_eth_send;
533 dev->recv = sh_eth_recv;
534 eth->port_info[eth->port].dev = dev;
536 sprintf(dev->name, SHETHER_NAME);
538 /* Register Device to EtherNet subsystem */
541 bb_miiphy_buses[0].priv = eth;
542 miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);
544 if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
545 puts("Please set MAC address\n");
556 printf(SHETHER_NAME ": Failed\n");
560 /******* for bb_miiphy *******/
561 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
566 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
568 struct sh_eth_dev *eth = bus->priv;
569 int port = eth->port;
571 outl(inl(PIR(port)) | PIR_MMD, PIR(port));
576 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
578 struct sh_eth_dev *eth = bus->priv;
579 int port = eth->port;
581 outl(inl(PIR(port)) & ~PIR_MMD, PIR(port));
586 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
588 struct sh_eth_dev *eth = bus->priv;
589 int port = eth->port;
592 outl(inl(PIR(port)) | PIR_MDO, PIR(port));
594 outl(inl(PIR(port)) & ~PIR_MDO, PIR(port));
599 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
601 struct sh_eth_dev *eth = bus->priv;
602 int port = eth->port;
604 *v = (inl(PIR(port)) & PIR_MDI) >> 3;
609 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
611 struct sh_eth_dev *eth = bus->priv;
612 int port = eth->port;
615 outl(inl(PIR(port)) | PIR_MDC, PIR(port));
617 outl(inl(PIR(port)) & ~PIR_MDC, PIR(port));
622 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
629 struct bb_miiphy_bus bb_miiphy_buses[] = {
632 .init = sh_eth_bb_init,
633 .mdio_active = sh_eth_bb_mdio_active,
634 .mdio_tristate = sh_eth_bb_mdio_tristate,
635 .set_mdio = sh_eth_bb_set_mdio,
636 .get_mdio = sh_eth_bb_get_mdio,
637 .set_mdc = sh_eth_bb_set_mdc,
638 .delay = sh_eth_bb_delay,
641 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);