2 * sh_eth.c - Driver for Renesas ethernet controller.
4 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
5 * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
7 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
9 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/errno.h>
23 #ifndef CONFIG_SH_ETHER_USE_PORT
24 # error "Please define CONFIG_SH_ETHER_USE_PORT"
26 #ifndef CONFIG_SH_ETHER_PHY_ADDR
27 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
30 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
31 #define flush_cache_wback(addr, len) \
32 flush_dcache_range((u32)addr, \
33 (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
35 #define flush_cache_wback(...)
38 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
39 #define invalidate_cache(addr, len) \
41 u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
46 start &= ~(line_size - 1); \
47 end = ((end + line_size - 1) & ~(line_size - 1)); \
49 invalidate_dcache_range(start, end); \
52 #define invalidate_cache(...)
55 #define TIMEOUT_CNT 1000
57 static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
59 int port = eth->port, ret = 0, timeout;
60 struct sh_eth_info *port_info = ð->port_info[port];
62 if (!packet || len > 0xffff) {
63 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
68 /* packet must be a 4 byte boundary */
69 if ((int)packet & 3) {
70 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
76 /* Update tx descriptor */
77 flush_cache_wback(packet, len);
78 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
79 port_info->tx_desc_cur->td1 = len << 16;
80 /* Must preserve the end of descriptor list indication */
81 if (port_info->tx_desc_cur->td0 & TD_TDLE)
82 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
84 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
86 flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
88 /* Restart the transmitter if disabled */
89 if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
90 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
92 /* Wait until packet is transmitted */
93 timeout = TIMEOUT_CNT;
95 invalidate_cache(port_info->tx_desc_cur,
96 sizeof(struct tx_desc_s));
98 } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
101 printf(SHETHER_NAME ": transmit timeout\n");
106 port_info->tx_desc_cur++;
107 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
108 port_info->tx_desc_cur = port_info->tx_desc_base;
114 static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
116 struct sh_eth_dev *eth = dev->priv;
118 return sh_eth_send_common(eth, packet, len);
121 static int sh_eth_recv_start(struct sh_eth_dev *eth)
123 int port = eth->port, len = 0;
124 struct sh_eth_info *port_info = ð->port_info[port];
126 /* Check if the rx descriptor is ready */
127 invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
128 if (port_info->rx_desc_cur->rd0 & RD_RACT)
131 /* Check for errors */
132 if (port_info->rx_desc_cur->rd0 & RD_RFE)
135 len = port_info->rx_desc_cur->rd1 & 0xffff;
140 static void sh_eth_recv_finish(struct sh_eth_dev *eth)
142 struct sh_eth_info *port_info = ð->port_info[eth->port];
144 /* Make current descriptor available again */
145 if (port_info->rx_desc_cur->rd0 & RD_RDLE)
146 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
148 port_info->rx_desc_cur->rd0 = RD_RACT;
150 flush_cache_wback(port_info->rx_desc_cur,
151 sizeof(struct rx_desc_s));
153 /* Point to the next descriptor */
154 port_info->rx_desc_cur++;
155 if (port_info->rx_desc_cur >=
156 port_info->rx_desc_base + NUM_RX_DESC)
157 port_info->rx_desc_cur = port_info->rx_desc_base;
160 static int sh_eth_recv_common(struct sh_eth_dev *eth)
162 int port = eth->port, len = 0;
163 struct sh_eth_info *port_info = ð->port_info[port];
164 uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
166 len = sh_eth_recv_start(eth);
168 invalidate_cache(packet, len);
169 net_process_received_packet(packet, len);
170 sh_eth_recv_finish(eth);
174 /* Restart the receiver if disabled */
175 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
176 sh_eth_write(port_info, EDRRR_R, EDRRR);
181 static int sh_eth_recv_legacy(struct eth_device *dev)
183 struct sh_eth_dev *eth = dev->priv;
185 return sh_eth_recv_common(eth);
188 static int sh_eth_reset(struct sh_eth_dev *eth)
190 struct sh_eth_info *port_info = ð->port_info[eth->port];
191 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
194 /* Start e-dmac transmitter and receiver */
195 sh_eth_write(port_info, EDSR_ENALL, EDSR);
197 /* Perform a software reset and wait for it to complete */
198 sh_eth_write(port_info, EDMR_SRST, EDMR);
199 for (i = 0; i < TIMEOUT_CNT; i++) {
200 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
205 if (i == TIMEOUT_CNT) {
206 printf(SHETHER_NAME ": Software reset timeout\n");
212 sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
214 sh_eth_write(port_info,
215 sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
221 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
223 int port = eth->port, i, ret = 0;
224 u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
225 struct sh_eth_info *port_info = ð->port_info[port];
226 struct tx_desc_s *cur_tx_desc;
229 * Allocate rx descriptors. They must be aligned to size of struct
232 port_info->tx_desc_alloc =
233 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
234 if (!port_info->tx_desc_alloc) {
235 printf(SHETHER_NAME ": memalign failed\n");
240 flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
242 /* Make sure we use a P2 address (non-cacheable) */
243 port_info->tx_desc_base =
244 (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
245 port_info->tx_desc_cur = port_info->tx_desc_base;
247 /* Initialize all descriptors */
248 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
249 cur_tx_desc++, i++) {
250 cur_tx_desc->td0 = 0x00;
251 cur_tx_desc->td1 = 0x00;
252 cur_tx_desc->td2 = 0x00;
255 /* Mark the end of the descriptors */
257 cur_tx_desc->td0 |= TD_TDLE;
260 * Point the controller to the tx descriptor list. Must use physical
263 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
264 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
265 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
266 sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
267 sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
274 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
276 int port = eth->port, i, ret = 0;
277 u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
278 struct sh_eth_info *port_info = ð->port_info[port];
279 struct rx_desc_s *cur_rx_desc;
283 * Allocate rx descriptors. They must be aligned to size of struct
286 port_info->rx_desc_alloc =
287 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
288 if (!port_info->rx_desc_alloc) {
289 printf(SHETHER_NAME ": memalign failed\n");
294 flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
296 /* Make sure we use a P2 address (non-cacheable) */
297 port_info->rx_desc_base =
298 (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
300 port_info->rx_desc_cur = port_info->rx_desc_base;
303 * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
304 * aligned and in P2 area.
306 port_info->rx_buf_alloc =
307 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
308 if (!port_info->rx_buf_alloc) {
309 printf(SHETHER_NAME ": alloc failed\n");
314 port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
316 /* Initialize all descriptors */
317 for (cur_rx_desc = port_info->rx_desc_base,
318 rx_buf = port_info->rx_buf_base, i = 0;
319 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
320 cur_rx_desc->rd0 = RD_RACT;
321 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
322 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
325 /* Mark the end of the descriptors */
327 cur_rx_desc->rd0 |= RD_RDLE;
329 /* Point the controller to the rx descriptor list */
330 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
331 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
332 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
333 sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
334 sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
340 free(port_info->rx_desc_alloc);
341 port_info->rx_desc_alloc = NULL;
347 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
349 int port = eth->port;
350 struct sh_eth_info *port_info = ð->port_info[port];
352 if (port_info->tx_desc_alloc) {
353 free(port_info->tx_desc_alloc);
354 port_info->tx_desc_alloc = NULL;
358 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
360 int port = eth->port;
361 struct sh_eth_info *port_info = ð->port_info[port];
363 if (port_info->rx_desc_alloc) {
364 free(port_info->rx_desc_alloc);
365 port_info->rx_desc_alloc = NULL;
368 if (port_info->rx_buf_alloc) {
369 free(port_info->rx_buf_alloc);
370 port_info->rx_buf_alloc = NULL;
374 static int sh_eth_desc_init(struct sh_eth_dev *eth)
378 ret = sh_eth_tx_desc_init(eth);
382 ret = sh_eth_rx_desc_init(eth);
388 sh_eth_tx_desc_free(eth);
394 static int sh_eth_phy_config(struct sh_eth_dev *eth)
396 int port = eth->port, ret = 0;
397 struct sh_eth_info *port_info = ð->port_info[port];
398 struct eth_device *dev = port_info->dev;
399 struct phy_device *phydev;
401 phydev = phy_connect(
402 miiphy_get_dev_by_name(dev->name),
403 port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
404 port_info->phydev = phydev;
410 static int sh_eth_config(struct sh_eth_dev *eth)
412 int port = eth->port, ret = 0;
414 struct sh_eth_info *port_info = ð->port_info[port];
415 struct eth_device *dev = port_info->dev;
416 struct phy_device *phy;
418 /* Configure e-dmac registers */
419 sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
420 (EMDR_DESC | EDMR_EL), EDMR);
422 sh_eth_write(port_info, 0, EESIPR);
423 sh_eth_write(port_info, 0, TRSCER);
424 sh_eth_write(port_info, 0, TFTR);
425 sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
426 sh_eth_write(port_info, RMCR_RST, RMCR);
427 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
428 sh_eth_write(port_info, 0, RPADIR);
430 sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
432 /* Configure e-mac registers */
433 sh_eth_write(port_info, 0, ECSIPR);
435 /* Set Mac address */
436 val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
437 dev->enetaddr[2] << 8 | dev->enetaddr[3];
438 sh_eth_write(port_info, val, MAHR);
440 val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
441 sh_eth_write(port_info, val, MALR);
443 sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
444 #if defined(SH_ETH_TYPE_GETHER)
445 sh_eth_write(port_info, 0, PIPR);
447 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
448 sh_eth_write(port_info, APR_AP, APR);
449 sh_eth_write(port_info, MPR_MP, MPR);
450 sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
453 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
454 sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
455 #elif defined(CONFIG_RCAR_GEN2)
456 sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
459 ret = sh_eth_phy_config(eth);
461 printf(SHETHER_NAME ": phy config timeout\n");
464 phy = port_info->phydev;
465 ret = phy_startup(phy);
467 printf(SHETHER_NAME ": phy startup failure\n");
473 /* Set the transfer speed */
474 if (phy->speed == 100) {
475 printf(SHETHER_NAME ": 100Base/");
476 #if defined(SH_ETH_TYPE_GETHER)
477 sh_eth_write(port_info, GECMR_100B, GECMR);
478 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
479 sh_eth_write(port_info, 1, RTRATE);
480 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2)
483 } else if (phy->speed == 10) {
484 printf(SHETHER_NAME ": 10Base/");
485 #if defined(SH_ETH_TYPE_GETHER)
486 sh_eth_write(port_info, GECMR_10B, GECMR);
487 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
488 sh_eth_write(port_info, 0, RTRATE);
491 #if defined(SH_ETH_TYPE_GETHER)
492 else if (phy->speed == 1000) {
493 printf(SHETHER_NAME ": 1000Base/");
494 sh_eth_write(port_info, GECMR_1000B, GECMR);
498 /* Check if full duplex mode is supported by the phy */
501 sh_eth_write(port_info,
502 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
506 sh_eth_write(port_info,
507 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
517 static void sh_eth_start(struct sh_eth_dev *eth)
519 struct sh_eth_info *port_info = ð->port_info[eth->port];
522 * Enable the e-dmac receiver only. The transmitter will be enabled when
523 * we have something to transmit
525 sh_eth_write(port_info, EDRRR_R, EDRRR);
528 static void sh_eth_stop(struct sh_eth_dev *eth)
530 struct sh_eth_info *port_info = ð->port_info[eth->port];
532 sh_eth_write(port_info, ~EDRRR_R, EDRRR);
535 int sh_eth_init(struct eth_device *dev, bd_t *bd)
538 struct sh_eth_dev *eth = dev->priv;
540 ret = sh_eth_reset(eth);
544 ret = sh_eth_desc_init(eth);
548 ret = sh_eth_config(eth);
557 sh_eth_tx_desc_free(eth);
558 sh_eth_rx_desc_free(eth);
564 void sh_eth_halt(struct eth_device *dev)
566 struct sh_eth_dev *eth = dev->priv;
571 int sh_eth_initialize(bd_t *bd)
574 struct sh_eth_dev *eth = NULL;
575 struct eth_device *dev = NULL;
576 struct mii_dev *mdiodev;
578 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
580 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
585 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
587 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
591 memset(dev, 0, sizeof(struct eth_device));
592 memset(eth, 0, sizeof(struct sh_eth_dev));
594 eth->port = CONFIG_SH_ETHER_USE_PORT;
595 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
596 eth->port_info[eth->port].iobase =
597 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
599 dev->priv = (void *)eth;
601 dev->init = sh_eth_init;
602 dev->halt = sh_eth_halt;
603 dev->send = sh_eth_send_legacy;
604 dev->recv = sh_eth_recv_legacy;
605 eth->port_info[eth->port].dev = dev;
607 strcpy(dev->name, SHETHER_NAME);
609 /* Register Device to EtherNet subsystem */
612 bb_miiphy_buses[0].priv = eth;
613 mdiodev = mdio_alloc();
616 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
617 mdiodev->read = bb_miiphy_read;
618 mdiodev->write = bb_miiphy_write;
620 ret = mdio_register(mdiodev);
624 if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
625 puts("Please set MAC address\n");
636 printf(SHETHER_NAME ": Failed\n");
640 /******* for bb_miiphy *******/
641 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
646 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
648 struct sh_eth_dev *eth = bus->priv;
649 struct sh_eth_info *port_info = ð->port_info[eth->port];
651 sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
656 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
658 struct sh_eth_dev *eth = bus->priv;
659 struct sh_eth_info *port_info = ð->port_info[eth->port];
661 sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
666 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
668 struct sh_eth_dev *eth = bus->priv;
669 struct sh_eth_info *port_info = ð->port_info[eth->port];
672 sh_eth_write(port_info,
673 sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
675 sh_eth_write(port_info,
676 sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
681 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
683 struct sh_eth_dev *eth = bus->priv;
684 struct sh_eth_info *port_info = ð->port_info[eth->port];
686 *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
691 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
693 struct sh_eth_dev *eth = bus->priv;
694 struct sh_eth_info *port_info = ð->port_info[eth->port];
697 sh_eth_write(port_info,
698 sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
700 sh_eth_write(port_info,
701 sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
706 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
713 struct bb_miiphy_bus bb_miiphy_buses[] = {
716 .init = sh_eth_bb_init,
717 .mdio_active = sh_eth_bb_mdio_active,
718 .mdio_tristate = sh_eth_bb_mdio_tristate,
719 .set_mdio = sh_eth_bb_set_mdio,
720 .get_mdio = sh_eth_bb_get_mdio,
721 .set_mdc = sh_eth_bb_set_mdc,
722 .delay = sh_eth_bb_delay,
726 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);