2 * sh_eth.h - Driver for Renesas SuperH ethernet controler.
4 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
5 * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <asm/types.h>
26 #define SHETHER_NAME "sh_eth"
28 /* Malloc returns addresses in the P1 area (cacheable). However we need to
29 use area P2 (non-cacheable) */
30 #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000))
32 /* The ethernet controller needs to use physical addresses */
33 #if defined(CONFIG_SH_32BIT)
34 #define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000))
36 #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
39 /* Number of supported ports */
40 #define MAX_PORT_NUM 2
42 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx
43 buffers must be a multiple of 32 bytes */
44 #define MAX_BUF_SIZE (48 * 32)
46 /* The number of tx descriptors must be large enough to point to 5 or more
47 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
48 We use one descriptor per frame */
51 /* The size of the tx descriptor is determined by how much padding is used.
52 4, 20, or 52 bytes of padding can be used */
53 #define TX_DESC_PADDING 4
54 #define TX_DESC_SIZE (12 + TX_DESC_PADDING)
56 /* Tx descriptor. We always use 3 bytes of padding */
60 u32 td2; /* Buffer start */
64 /* There is no limitation in the number of rx descriptors */
67 /* The size of the rx descriptor is determined by how much padding is used.
68 4, 20, or 52 bytes of padding can be used */
69 #define RX_DESC_PADDING 4
70 #define RX_DESC_SIZE (12 + RX_DESC_PADDING)
72 /* Rx descriptor. We always use 4 bytes of padding */
76 u32 rd2; /* Buffer start */
81 struct tx_desc_s *tx_desc_malloc;
82 struct tx_desc_s *tx_desc_base;
83 struct tx_desc_s *tx_desc_cur;
84 struct rx_desc_s *rx_desc_malloc;
85 struct rx_desc_s *rx_desc_base;
86 struct rx_desc_s *rx_desc_cur;
91 struct eth_device *dev;
92 struct phy_device *phydev;
97 struct sh_eth_info port_info[MAX_PORT_NUM];
100 /* Register Address */
101 #ifdef CONFIG_CPU_SH7763
102 #define BASE_IO_ADDR 0xfee00000
104 #define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000)
106 #define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010)
107 #define TDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0014)
108 #define TDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018)
109 #define TDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x001c)
111 #define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030)
112 #define RDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0034)
113 #define RDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038)
114 #define RDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x003c)
116 #define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0400)
117 #define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0408)
118 #define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0410)
119 #define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0428)
120 #define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0430)
121 #define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0438)
122 #define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0448)
123 #define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0450)
124 #define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0458)
125 #define RPADIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0460)
126 #define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0468)
127 #define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0500)
128 #define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0508)
129 #define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0518)
130 #define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0520)
131 #define PIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x052c)
132 #define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0554)
133 #define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0558)
134 #define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0564)
135 #define GECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05b0)
136 #define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c8)
137 #define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0)
139 #elif defined(CONFIG_CPU_SH7757)
140 #define BASE_IO_ADDR 0xfef00000
142 #define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018)
143 #define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0020)
145 #define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000)
146 #define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0008)
147 #define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010)
148 #define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0028)
149 #define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030)
150 #define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038)
151 #define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0048)
152 #define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0050)
153 #define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0058)
154 #define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0070)
155 #define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0100)
156 #define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0108)
157 #define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0118)
158 #define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0120)
159 #define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0154)
160 #define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0158)
161 #define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0164)
162 #define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c0)
163 #define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c8)
164 #define RTRATE(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01fc)
166 #elif defined(CONFIG_CPU_SH7724)
167 #define BASE_IO_ADDR 0xA4600000
169 #define TDLAR(port) (BASE_IO_ADDR + 0x0018)
170 #define RDLAR(port) (BASE_IO_ADDR + 0x0020)
172 #define EDMR(port) (BASE_IO_ADDR + 0x0000)
173 #define EDTRR(port) (BASE_IO_ADDR + 0x0008)
174 #define EDRRR(port) (BASE_IO_ADDR + 0x0010)
175 #define EESR(port) (BASE_IO_ADDR + 0x0028)
176 #define EESIPR(port) (BASE_IO_ADDR + 0x0030)
177 #define TRSCER(port) (BASE_IO_ADDR + 0x0038)
178 #define TFTR(port) (BASE_IO_ADDR + 0x0048)
179 #define FDR(port) (BASE_IO_ADDR + 0x0050)
180 #define RMCR(port) (BASE_IO_ADDR + 0x0058)
181 #define FCFTR(port) (BASE_IO_ADDR + 0x0070)
182 #define ECMR(port) (BASE_IO_ADDR + 0x0100)
183 #define RFLR(port) (BASE_IO_ADDR + 0x0108)
184 #define ECSIPR(port) (BASE_IO_ADDR + 0x0118)
185 #define PIR(port) (BASE_IO_ADDR + 0x0120)
186 #define APR(port) (BASE_IO_ADDR + 0x0154)
187 #define MPR(port) (BASE_IO_ADDR + 0x0158)
188 #define TPAUSER(port) (BASE_IO_ADDR + 0x0164)
189 #define MAHR(port) (BASE_IO_ADDR + 0x01c0)
190 #define MALR(port) (BASE_IO_ADDR + 0x01c8)
192 #elif defined(CONFIG_CPU_SH7734)
193 #define BASE_IO_ADDR 0xFEE00000
195 #define EDSR(port) (BASE_IO_ADDR)
197 #define TDLAR(port) (BASE_IO_ADDR + 0x0010)
198 #define TDFAR(port) (BASE_IO_ADDR + 0x0014)
199 #define TDFXR(port) (BASE_IO_ADDR + 0x0018)
200 #define TDFFR(port) (BASE_IO_ADDR + 0x001c)
201 #define RDLAR(port) (BASE_IO_ADDR + 0x0030)
202 #define RDFAR(port) (BASE_IO_ADDR + 0x0034)
203 #define RDFXR(port) (BASE_IO_ADDR + 0x0038)
204 #define RDFFR(port) (BASE_IO_ADDR + 0x003c)
206 #define EDMR(port) (BASE_IO_ADDR + 0x0400)
207 #define EDTRR(port) (BASE_IO_ADDR + 0x0408)
208 #define EDRRR(port) (BASE_IO_ADDR + 0x0410)
209 #define EESR(port) (BASE_IO_ADDR + 0x0428)
210 #define EESIPR(port) (BASE_IO_ADDR + 0x0430)
211 #define TRSCER(port) (BASE_IO_ADDR + 0x0438)
212 #define TFTR(port) (BASE_IO_ADDR + 0x0448)
213 #define FDR(port) (BASE_IO_ADDR + 0x0450)
214 #define RMCR(port) (BASE_IO_ADDR + 0x0458)
215 #define RPADIR(port) (BASE_IO_ADDR + 0x0460)
216 #define FCFTR(port) (BASE_IO_ADDR + 0x0468)
217 #define ECMR(port) (BASE_IO_ADDR + 0x0500)
218 #define RFLR(port) (BASE_IO_ADDR + 0x0508)
219 #define ECSIPR(port) (BASE_IO_ADDR + 0x0518)
220 #define PIR(port) (BASE_IO_ADDR + 0x0520)
221 #define PIPR(port) (BASE_IO_ADDR + 0x052c)
222 #define APR(port) (BASE_IO_ADDR + 0x0554)
223 #define MPR(port) (BASE_IO_ADDR + 0x0558)
224 #define TPAUSER(port) (BASE_IO_ADDR + 0x0564)
225 #define GECMR(port) (BASE_IO_ADDR + 0x05b0)
226 #define MAHR(port) (BASE_IO_ADDR + 0x05C0)
227 #define MALR(port) (BASE_IO_ADDR + 0x05C8)
228 #define RMII_MII(port) (BASE_IO_ADDR + 0x0790)
234 * Copy from Linux driver source code
236 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
239 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
241 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
246 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
247 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
248 EDMR_SRST = 0x03, /* Receive/Send reset */
249 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
250 EDMR_EL = 0x40, /* Litte endian */
251 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7724)
253 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
254 EDMR_EL = 0x40, /* Litte endian */
255 #else /* CONFIG_CPU_SH7763 */
261 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
265 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
274 GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
284 TPAUSER_TPAUSE = 0x0000ffff,
285 TPAUSER_UNLIMITED = 0,
290 BCFR_RPAUSE = 0x0000ffff,
296 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
300 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
305 #if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
306 EESR_TWB = 0x40000000,
308 EESR_TWB = 0xC0000000,
309 EESR_TC1 = 0x20000000,
310 EESR_TUC = 0x10000000,
311 EESR_ROC = 0x80000000,
313 EESR_TABT = 0x04000000,
314 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
315 #if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
316 EESR_ADE = 0x00800000,
318 EESR_ECI = 0x00400000,
319 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
320 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
321 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
322 #if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
323 EESR_CND = 0x00000800,
325 EESR_DLC = 0x00000400,
326 EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
327 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
328 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
329 rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
330 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
334 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
335 # define TX_CHECK (EESR_TC1 | EESR_FTC)
336 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
337 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
338 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
341 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
342 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
343 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
344 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
349 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
350 DMAC_M_RABT = 0x02000000,
351 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
352 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
353 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
354 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
355 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
356 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
357 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
358 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
359 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
360 DMAC_M_RINT1 = 0x00000001,
363 /* Receive descriptor bit */
365 RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
366 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
367 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
368 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
369 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
370 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
371 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
372 RD_RFS1 = 0x00000001,
374 #define RDF1ST RD_RFP1
375 #define RDFEND RD_RFP0
376 #define RD_RFP (RD_RFP1|RD_RFP0)
385 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
386 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
387 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
389 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
390 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
392 /* Transfer descriptor bit */
394 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) \
395 || defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7734)
396 TD_TACT = 0x80000000,
398 TD_TACT = 0x7fffffff,
400 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
401 TD_TFP0 = 0x10000000,
403 #define TDF1ST TD_TFP1
404 #define TDFEND TD_TFP0
405 #define TD_TFP (TD_TFP1|TD_TFP0)
408 enum RECV_RST_BIT { RMCR_RST = 0x01, };
410 enum FELIC_MODE_BIT {
411 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
412 ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
413 ECMR_RZPF = 0x00100000,
415 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
416 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
417 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
418 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
419 ECMR_PRM = 0x00000001,
420 #ifdef CONFIG_CPU_SH7724
421 ECMR_RTM = 0x00000010,
426 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
427 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
429 #elif CONFIG_CPU_SH7724 || CONFIG_CPU_SH7757
430 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
432 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
436 enum ECSR_STATUS_BIT {
437 #if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
438 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
441 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
444 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
445 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
447 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
448 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
452 enum ECSIPR_STATUS_MASK_BIT {
453 #if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
454 ECSIPR_BRCRXIP = 0x20,
455 ECSIPR_PSRTOIP = 0x10,
456 #elif defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
457 ECSIPR_PSRTOIP = 0x10,
460 ECSIPR_LCHNGIP = 0x04,
465 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
466 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
468 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
469 ECSIPR_ICDIP | ECSIPR_MPDIP)
484 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
485 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
486 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
487 DESC_I_RINT1 = 0x0001,
492 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
493 RPADIR_PADR = 0x0003f,
496 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
497 # define RPADIR_INIT (0x00)
499 # define RPADIR_INIT (RPADIR_PADS1)
504 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,