2 * Freescale Three Speed Ethernet Controller driver
4 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
5 * (C) Copyright 2003, Motorola, Inc.
8 * SPDX-License-Identifier: GPL-2.0+
19 #include <linux/errno.h>
20 #include <asm/processor.h>
23 DECLARE_GLOBAL_DATA_PTR;
26 /* Default initializations for TSEC controllers. */
28 static struct tsec_info_struct tsec_info[] = {
30 STD_TSEC_INFO(1), /* TSEC1 */
33 STD_TSEC_INFO(2), /* TSEC2 */
35 #ifdef CONFIG_MPC85XX_FEC
37 .regs = TSEC_GET_REGS(2, 0x2000),
38 .devname = CONFIG_MPC85XX_FEC_NAME,
39 .phyaddr = FEC_PHY_ADDR,
41 .mii_devname = DEFAULT_MII_NAME
45 STD_TSEC_INFO(3), /* TSEC3 */
48 STD_TSEC_INFO(4), /* TSEC4 */
51 #endif /* CONFIG_DM_ETH */
53 #define TBIANA_SETTINGS ( \
54 TBIANA_ASYMMETRIC_PAUSE \
55 | TBIANA_SYMMETRIC_PAUSE \
56 | TBIANA_FULL_DUPLEX \
59 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
60 #ifndef CONFIG_TSEC_TBICR_SETTINGS
61 #define CONFIG_TSEC_TBICR_SETTINGS ( \
67 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
69 /* Configure the TBI for SGMII operation */
70 static void tsec_configure_serdes(struct tsec_private *priv)
73 * Access TBI PHY registers at given TSEC register offset as opposed
74 * to the register offset used for external PHY accesses
76 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
77 0, TBI_ANA, TBIANA_SETTINGS);
78 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
79 0, TBI_TBICON, TBICON_CLK_SELECT);
80 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
81 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
84 #ifdef CONFIG_MCAST_TFTP
86 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
88 /* Set the appropriate hash bit for the given addr */
91 * The algorithm works like so:
92 * 1) Take the Destination Address (ie the multicast address), and
93 * do a CRC on it (little endian), and reverse the bits of the
95 * 2) Use the 8 most significant bits as a hash into a 256-entry
96 * table. The table is controlled through 8 32-bit registers:
97 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
98 * 255. This means that the 3 most significant bits in the
99 * hash index which gaddr register to use, and the 5 other bits
100 * indicate which bit (assuming an IBM numbering scheme, which
101 * for PowerPC (tm) is usually the case) in the register holds
104 #ifndef CONFIG_DM_ETH
105 static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
107 static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int set)
110 struct tsec_private *priv = (struct tsec_private *)dev->priv;
111 struct tsec __iomem *regs = priv->regs;
113 u8 whichbit, whichreg;
115 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
116 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
117 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
119 value = BIT(31 - whichbit);
122 setbits_be32(®s->hash.gaddr0 + whichreg, value);
124 clrbits_be32(®s->hash.gaddr0 + whichreg, value);
128 #endif /* Multicast TFTP ? */
131 * Initialized required registers to appropriate values, zeroing
132 * those we don't care about (unless zero is bad, in which case,
133 * choose a more appropriate value)
135 static void init_registers(struct tsec __iomem *regs)
138 out_be32(®s->ievent, IEVENT_INIT_CLEAR);
140 out_be32(®s->imask, IMASK_INIT_CLEAR);
142 out_be32(®s->hash.iaddr0, 0);
143 out_be32(®s->hash.iaddr1, 0);
144 out_be32(®s->hash.iaddr2, 0);
145 out_be32(®s->hash.iaddr3, 0);
146 out_be32(®s->hash.iaddr4, 0);
147 out_be32(®s->hash.iaddr5, 0);
148 out_be32(®s->hash.iaddr6, 0);
149 out_be32(®s->hash.iaddr7, 0);
151 out_be32(®s->hash.gaddr0, 0);
152 out_be32(®s->hash.gaddr1, 0);
153 out_be32(®s->hash.gaddr2, 0);
154 out_be32(®s->hash.gaddr3, 0);
155 out_be32(®s->hash.gaddr4, 0);
156 out_be32(®s->hash.gaddr5, 0);
157 out_be32(®s->hash.gaddr6, 0);
158 out_be32(®s->hash.gaddr7, 0);
160 out_be32(®s->rctrl, 0x00000000);
162 /* Init RMON mib registers */
163 memset((void *)®s->rmon, 0, sizeof(regs->rmon));
165 out_be32(®s->rmon.cam1, 0xffffffff);
166 out_be32(®s->rmon.cam2, 0xffffffff);
168 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
170 out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
172 out_be32(®s->attr, ATTR_INIT_SETTINGS);
173 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
177 * Configure maccfg2 based on negotiated speed and duplex
178 * reported by PHY handling code
180 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
182 struct tsec __iomem *regs = priv->regs;
186 printf("%s: No link.\n", phydev->dev->name);
190 /* clear all bits relative with interface mode */
191 ecntrl = in_be32(®s->ecntrl);
192 ecntrl &= ~ECNTRL_R100;
194 maccfg2 = in_be32(®s->maccfg2);
195 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
198 maccfg2 |= MACCFG2_FULL_DUPLEX;
200 switch (phydev->speed) {
202 maccfg2 |= MACCFG2_GMII;
206 maccfg2 |= MACCFG2_MII;
209 * Set R100 bit in all modes although
210 * it is only used in RGMII mode
212 if (phydev->speed == 100)
213 ecntrl |= ECNTRL_R100;
216 printf("%s: Speed was bad\n", phydev->dev->name);
220 out_be32(®s->ecntrl, ecntrl);
221 out_be32(®s->maccfg2, maccfg2);
223 printf("Speed: %d, %s duplex%s\n", phydev->speed,
224 (phydev->duplex) ? "full" : "half",
225 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
229 * This returns the status bits of the device. The return value
230 * is never checked, and this is what the 8260 driver did, so we
231 * do the same. Presumably, this would be zero if there were no
234 #ifndef CONFIG_DM_ETH
235 static int tsec_send(struct eth_device *dev, void *packet, int length)
237 static int tsec_send(struct udevice *dev, void *packet, int length)
240 struct tsec_private *priv = (struct tsec_private *)dev->priv;
241 struct tsec __iomem *regs = priv->regs;
246 /* Find an empty buffer descriptor */
248 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
250 if (i >= TOUT_LOOP) {
251 debug("%s: tsec: tx buffers full\n", dev->name);
256 out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
257 out_be16(&priv->txbd[priv->tx_idx].length, length);
258 status = in_be16(&priv->txbd[priv->tx_idx].status);
259 out_be16(&priv->txbd[priv->tx_idx].status, status |
260 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
262 /* Tell the DMA to go */
263 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
265 /* Wait for buffer to be transmitted */
267 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
269 if (i >= TOUT_LOOP) {
270 debug("%s: tsec: tx error\n", dev->name);
275 priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
276 result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
281 #ifndef CONFIG_DM_ETH
282 static int tsec_recv(struct eth_device *dev)
284 struct tsec_private *priv = (struct tsec_private *)dev->priv;
285 struct tsec __iomem *regs = priv->regs;
287 while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
288 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
289 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
290 uchar *packet = net_rx_packets[priv->rx_idx];
292 /* Send the packet up if there were no errors */
293 if (!(status & RXBD_STATS))
294 net_process_received_packet(packet, length - 4);
296 printf("Got error %x\n", (status & RXBD_STATS));
298 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
301 /* Set the wrap bit if this is the last element in the list */
302 if ((priv->rx_idx + 1) == PKTBUFSRX)
304 out_be16(&priv->rxbd[priv->rx_idx].status, status);
306 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
309 if (in_be32(®s->ievent) & IEVENT_BSY) {
310 out_be32(®s->ievent, IEVENT_BSY);
311 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
317 static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
319 struct tsec_private *priv = (struct tsec_private *)dev->priv;
320 struct tsec __iomem *regs = priv->regs;
323 if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
324 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
325 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
328 /* Send the packet up if there were no errors */
329 if (!(status & RXBD_STATS)) {
330 buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
331 *packetp = (uchar *)buf;
334 printf("Got error %x\n", (status & RXBD_STATS));
338 if (in_be32(®s->ievent) & IEVENT_BSY) {
339 out_be32(®s->ievent, IEVENT_BSY);
340 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
346 static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
348 struct tsec_private *priv = (struct tsec_private *)dev->priv;
351 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
354 /* Set the wrap bit if this is the last element in the list */
355 if ((priv->rx_idx + 1) == PKTBUFSRX)
357 out_be16(&priv->rxbd[priv->rx_idx].status, status);
359 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
365 /* Stop the interface */
366 #ifndef CONFIG_DM_ETH
367 static void tsec_halt(struct eth_device *dev)
369 static void tsec_halt(struct udevice *dev)
372 struct tsec_private *priv = (struct tsec_private *)dev->priv;
373 struct tsec __iomem *regs = priv->regs;
375 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
376 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
378 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
379 != (IEVENT_GRSC | IEVENT_GTSC))
382 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
384 /* Shut down the PHY, as needed */
385 phy_shutdown(priv->phydev);
388 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
390 * When MACCFG1[Rx_EN] is enabled during system boot as part
391 * of the eTSEC port initialization sequence,
392 * the eTSEC Rx logic may not be properly initialized.
394 void redundant_init(struct tsec_private *priv)
396 struct tsec __iomem *regs = priv->regs;
399 static const u8 pkt[] = {
400 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
401 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
402 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
403 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
404 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
405 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
406 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
407 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
408 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
409 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
410 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
411 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
412 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
415 /* Enable promiscuous mode */
416 setbits_be32(®s->rctrl, 0x8);
417 /* Enable loopback mode */
418 setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
419 /* Enable transmit and receive */
420 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
422 /* Tell the DMA it is clear to go */
423 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
424 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
425 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
426 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
431 tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
433 /* Wait for buffer to be received */
435 in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
437 if (t >= 10 * TOUT_LOOP) {
438 printf("%s: tsec: rx error\n", priv->dev->name);
443 if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
446 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
448 if ((priv->rx_idx + 1) == PKTBUFSRX)
450 out_be16(&priv->rxbd[priv->rx_idx].status, status);
451 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
453 if (in_be32(®s->ievent) & IEVENT_BSY) {
454 out_be32(®s->ievent, IEVENT_BSY);
455 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
458 printf("loopback recv packet error!\n");
459 clrbits_be32(®s->maccfg1, MACCFG1_RX_EN);
461 setbits_be32(®s->maccfg1, MACCFG1_RX_EN);
463 } while ((count++ < 4) && (fail == 1));
466 panic("eTSEC init fail!\n");
467 /* Disable promiscuous mode */
468 clrbits_be32(®s->rctrl, 0x8);
469 /* Disable loopback mode */
470 clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
475 * Set up the buffers and their descriptors, and bring up the
478 static void startup_tsec(struct tsec_private *priv)
480 struct tsec __iomem *regs = priv->regs;
484 /* reset the indices to zero */
487 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
491 /* Point to the buffer descriptors */
492 out_be32(®s->tbase, (u32)&priv->txbd[0]);
493 out_be32(®s->rbase, (u32)&priv->rxbd[0]);
495 /* Initialize the Rx Buffer descriptors */
496 for (i = 0; i < PKTBUFSRX; i++) {
497 out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
498 out_be16(&priv->rxbd[i].length, 0);
499 out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
501 status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
502 out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
504 /* Initialize the TX Buffer Descriptors */
505 for (i = 0; i < TX_BUF_CNT; i++) {
506 out_be16(&priv->txbd[i].status, 0);
507 out_be16(&priv->txbd[i].length, 0);
508 out_be32(&priv->txbd[i].bufptr, 0);
510 status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
511 out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
513 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
515 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
516 redundant_init(priv);
518 /* Enable Transmit and Receive */
519 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
521 /* Tell the DMA it is clear to go */
522 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
523 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
524 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
525 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
529 * Initializes data structures and registers for the controller,
530 * and brings the interface up. Returns the link status, meaning
531 * that it returns success if the link is up, failure otherwise.
532 * This allows U-Boot to find the first active controller.
534 #ifndef CONFIG_DM_ETH
535 static int tsec_init(struct eth_device *dev, bd_t *bd)
537 static int tsec_init(struct udevice *dev)
540 struct tsec_private *priv = (struct tsec_private *)dev->priv;
542 struct eth_pdata *pdata = dev_get_platdata(dev);
544 struct tsec __iomem *regs = priv->regs;
548 /* Make sure the controller is stopped */
551 /* Init MACCFG2. Defaults to GMII */
552 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
555 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
558 * Copy the station address into the address registers.
559 * For a station address of 0x12345678ABCD in transmission
560 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
561 * MACnADDR2 is set to 0x34120000.
563 #ifndef CONFIG_DM_ETH
564 tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
565 (dev->enetaddr[3] << 8) | dev->enetaddr[2];
567 tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
568 (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
571 out_be32(®s->macstnaddr1, tempval);
573 #ifndef CONFIG_DM_ETH
574 tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
576 tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
579 out_be32(®s->macstnaddr2, tempval);
581 /* Clear out (for the most part) the other registers */
582 init_registers(regs);
584 /* Ready the device for tx/rx */
587 /* Start up the PHY */
588 ret = phy_startup(priv->phydev);
590 printf("Could not initialize PHY %s\n",
591 priv->phydev->dev->name);
595 adjust_link(priv, priv->phydev);
597 /* If there's no link, fail */
598 return priv->phydev->link ? 0 : -1;
601 static phy_interface_t tsec_get_interface(struct tsec_private *priv)
603 struct tsec __iomem *regs = priv->regs;
606 ecntrl = in_be32(®s->ecntrl);
608 if (ecntrl & ECNTRL_SGMII_MODE)
609 return PHY_INTERFACE_MODE_SGMII;
611 if (ecntrl & ECNTRL_TBI_MODE) {
612 if (ecntrl & ECNTRL_REDUCED_MODE)
613 return PHY_INTERFACE_MODE_RTBI;
615 return PHY_INTERFACE_MODE_TBI;
618 if (ecntrl & ECNTRL_REDUCED_MODE) {
619 phy_interface_t interface;
621 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
622 return PHY_INTERFACE_MODE_RMII;
624 interface = priv->interface;
627 * This isn't autodetected, so it must
628 * be set by the platform code.
630 if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
631 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
632 interface == PHY_INTERFACE_MODE_RGMII_RXID)
635 return PHY_INTERFACE_MODE_RGMII;
638 if (priv->flags & TSEC_GIGABIT)
639 return PHY_INTERFACE_MODE_GMII;
641 return PHY_INTERFACE_MODE_MII;
645 * Discover which PHY is attached to the device, and configure it
646 * properly. If the PHY is not recognized, then return 0
647 * (failure). Otherwise, return 1
649 static int init_phy(struct tsec_private *priv)
651 struct phy_device *phydev;
652 struct tsec __iomem *regs = priv->regs;
653 u32 supported = (SUPPORTED_10baseT_Half |
654 SUPPORTED_10baseT_Full |
655 SUPPORTED_100baseT_Half |
656 SUPPORTED_100baseT_Full);
658 if (priv->flags & TSEC_GIGABIT)
659 supported |= SUPPORTED_1000baseT_Full;
661 /* Assign a Physical address to the TBI */
662 out_be32(®s->tbipa, priv->tbiaddr);
664 priv->interface = tsec_get_interface(priv);
666 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
667 tsec_configure_serdes(priv);
669 phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
674 phydev->supported &= supported;
675 phydev->advertising = phydev->supported;
677 priv->phydev = phydev;
684 #ifndef CONFIG_DM_ETH
686 * Initialize device structure. Returns success if PHY
687 * initialization succeeded (i.e. if it recognizes the PHY)
689 static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
691 struct eth_device *dev;
693 struct tsec_private *priv;
695 dev = (struct eth_device *)malloc(sizeof(*dev));
700 memset(dev, 0, sizeof(*dev));
702 priv = (struct tsec_private *)malloc(sizeof(*priv));
707 priv->regs = tsec_info->regs;
708 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
710 priv->phyaddr = tsec_info->phyaddr;
711 priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
712 priv->flags = tsec_info->flags;
714 strcpy(dev->name, tsec_info->devname);
715 priv->interface = tsec_info->interface;
716 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
720 dev->init = tsec_init;
721 dev->halt = tsec_halt;
722 dev->send = tsec_send;
723 dev->recv = tsec_recv;
724 #ifdef CONFIG_MCAST_TFTP
725 dev->mcast = tsec_mcast_addr;
728 /* Tell U-Boot to get the addr from the env */
729 for (i = 0; i < 6; i++)
730 dev->enetaddr[i] = 0;
735 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
736 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
737 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
739 /* Try to initialize PHY here, and return */
740 return init_phy(priv);
744 * Initialize all the TSEC devices
746 * Returns the number of TSEC devices that were initialized
748 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
753 for (i = 0; i < num; i++) {
754 int ret = tsec_initialize(bis, &tsecs[i]);
763 int tsec_standard_init(bd_t *bis)
765 struct fsl_pq_mdio_info info;
767 info.regs = TSEC_GET_MDIO_REGS_BASE(1);
768 info.name = DEFAULT_MII_NAME;
770 fsl_pq_mdio_init(bis, &info);
772 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
774 #else /* CONFIG_DM_ETH */
775 int tsec_probe(struct udevice *dev)
777 struct tsec_private *priv = dev_get_priv(dev);
778 struct eth_pdata *pdata = dev_get_platdata(dev);
779 struct fsl_pq_mdio_info mdio_info;
782 const char *phy_mode;
785 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
786 priv->regs = (struct tsec *)pdata->iobase;
788 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
791 reg = fdtdec_get_int(gd->fdt_blob, offset, "reg", 0);
794 debug("phy-handle does not exist under tsec %s\n", dev->name);
798 offset = fdt_parent_offset(gd->fdt_blob, offset);
800 reg = fdtdec_get_int(gd->fdt_blob, offset, "reg", 0);
801 priv->phyregs_sgmii = (struct tsec_mii_mng *)(reg + 0x520);
803 debug("No parent node for PHY?\n");
807 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
810 reg = fdtdec_get_int(gd->fdt_blob, offset, "reg",
811 CONFIG_SYS_TBIPA_VALUE);
814 priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
817 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
818 "phy-connection-type", NULL);
820 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
821 if (pdata->phy_interface == -1) {
822 debug("Invalid PHY interface '%s'\n", phy_mode);
825 priv->interface = pdata->phy_interface;
827 /* Initialize flags */
828 priv->flags = TSEC_GIGABIT;
829 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
830 priv->flags |= TSEC_SGMII;
832 mdio_info.regs = priv->phyregs_sgmii;
833 mdio_info.name = (char *)dev->name;
834 ret = fsl_pq_mdio_init(NULL, &mdio_info);
839 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
840 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
841 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
844 priv->bus = miiphy_get_dev_by_name(dev->name);
846 /* Try to initialize PHY here, and return */
847 return !init_phy(priv);
850 int tsec_remove(struct udevice *dev)
852 struct tsec_private *priv = dev->priv;
855 mdio_unregister(priv->bus);
856 mdio_free(priv->bus);
861 static const struct eth_ops tsec_ops = {
865 .free_pkt = tsec_free_pkt,
867 #ifdef CONFIG_MCAST_TFTP
868 .mcast = tsec_mcast_addr,
872 static const struct udevice_id tsec_ids[] = {
873 { .compatible = "fsl,tsec" },
877 U_BOOT_DRIVER(eth_tsec) = {
880 .of_match = tsec_ids,
882 .remove = tsec_remove,
884 .priv_auto_alloc_size = sizeof(struct tsec_private),
885 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
886 .flags = DM_FLAG_ALLOC_PRIV_DMA,
888 #endif /* CONFIG_DM_ETH */