4 * Driver for the Motorola Triple Speed Ethernet Controller
6 * This software may be used and distributed according to the
7 * terms of the GNU Public License, Version 2, incorporated
10 * Copyright 2004, 2007 Freescale Semiconductor, Inc.
11 * (C) Copyright 2003, Motorola, Inc.
12 * maintained by Xianghua Xiao (x.xiao@motorola.com)
23 #ifndef CFG_TSEC1_OFFSET
24 #define CFG_TSEC1_OFFSET (0x24000)
27 #define TSEC_SIZE 0x01000
29 /* FIXME: Should these be pushed back to 83xx and 85xx config files? */
30 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
31 #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET)
32 #elif defined(CONFIG_MPC83XX)
33 #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET)
37 #define MAC_ADDR_LEN 6
39 /* #define TSEC_TIMEOUT 1000000 */
40 #define TSEC_TIMEOUT 1000
41 #define TOUT_LOOP 1000000
43 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
45 /* MAC register bits */
46 #define MACCFG1_SOFT_RESET 0x80000000
47 #define MACCFG1_RESET_RX_MC 0x00080000
48 #define MACCFG1_RESET_TX_MC 0x00040000
49 #define MACCFG1_RESET_RX_FUN 0x00020000
50 #define MACCFG1_RESET_TX_FUN 0x00010000
51 #define MACCFG1_LOOPBACK 0x00000100
52 #define MACCFG1_RX_FLOW 0x00000020
53 #define MACCFG1_TX_FLOW 0x00000010
54 #define MACCFG1_SYNCD_RX_EN 0x00000008
55 #define MACCFG1_RX_EN 0x00000004
56 #define MACCFG1_SYNCD_TX_EN 0x00000002
57 #define MACCFG1_TX_EN 0x00000001
59 #define MACCFG2_INIT_SETTINGS 0x00007205
60 #define MACCFG2_FULL_DUPLEX 0x00000001
61 #define MACCFG2_IF 0x00000300
62 #define MACCFG2_GMII 0x00000200
63 #define MACCFG2_MII 0x00000100
65 #define ECNTRL_INIT_SETTINGS 0x00001000
66 #define ECNTRL_TBI_MODE 0x00000020
67 #define ECNTRL_R100 0x00000008
68 #define ECNTRL_SGMII_MODE 0x00000002
73 #ifndef CFG_TBIPA_VALUE
74 #define CFG_TBIPA_VALUE 0x1f
76 #define MIIMCFG_INIT_VALUE 0x00000003
77 #define MIIMCFG_RESET 0x80000000
79 #define MIIMIND_BUSY 0x00000001
80 #define MIIMIND_NOTVALID 0x00000004
82 #define MIIM_CONTROL 0x00
83 #define MIIM_CONTROL_RESET 0x00009140
84 #define MIIM_CONTROL_INIT 0x00001140
85 #define MIIM_CONTROL_RESTART 0x00001340
86 #define MIIM_ANEN 0x00001000
89 #define MIIM_CR_RST 0x00008000
90 #define MIIM_CR_INIT 0x00001000
92 #define MIIM_STATUS 0x1
93 #define MIIM_STATUS_AN_DONE 0x00000020
94 #define MIIM_STATUS_LINK 0x0004
95 #define PHY_BMSR_AUTN_ABLE 0x0008
96 #define PHY_BMSR_AUTN_COMP 0x0020
98 #define MIIM_PHYIR1 0x2
99 #define MIIM_PHYIR2 0x3
101 #define MIIM_ANAR 0x4
102 #define MIIM_ANAR_INIT 0x1e1
104 #define MIIM_TBI_ANLPBPA 0x5
105 #define MIIM_TBI_ANLPBPA_HALF 0x00000040
106 #define MIIM_TBI_ANLPBPA_FULL 0x00000020
108 #define MIIM_TBI_ANEX 0x6
109 #define MIIM_TBI_ANEX_NP 0x00000004
110 #define MIIM_TBI_ANEX_PRX 0x00000002
112 #define MIIM_GBIT_CONTROL 0x9
113 #define MIIM_GBIT_CONTROL_INIT 0xe00
115 /* Broadcom BCM54xx -- taken from linux sungem_phy */
116 #define MIIM_BCM54xx_AUXSTATUS 0x19
117 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700
118 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8
120 /* Cicada Auxiliary Control/Status Register */
121 #define MIIM_CIS8201_AUX_CONSTAT 0x1c
122 #define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004
123 #define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020
124 #define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018
125 #define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010
126 #define MIIM_CIS8201_AUXCONSTAT_100 0x0008
128 /* Cicada Extended Control Register 1 */
129 #define MIIM_CIS8201_EXT_CON1 0x17
130 #define MIIM_CIS8201_EXTCON1_INIT 0x0000
132 /* Cicada 8204 Extended PHY Control Register 1 */
133 #define MIIM_CIS8204_EPHY_CON 0x17
134 #define MIIM_CIS8204_EPHYCON_INIT 0x0006
135 #define MIIM_CIS8204_EPHYCON_RGMII 0x1100
137 /* Cicada 8204 Serial LED Control Register */
138 #define MIIM_CIS8204_SLED_CON 0x1b
139 #define MIIM_CIS8204_SLEDCON_INIT 0x1115
141 #define MIIM_GBIT_CON 0x09
142 #define MIIM_GBIT_CON_ADVERT 0x0e00
144 /* Entry for Vitesse VSC8244 regs starts here */
145 /* Vitesse VSC8244 Auxiliary Control/Status Register */
146 #define MIIM_VSC8244_AUX_CONSTAT 0x1c
147 #define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000
148 #define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020
149 #define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018
150 #define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010
151 #define MIIM_VSC8244_AUXCONSTAT_100 0x0008
152 #define MIIM_CONTROL_INIT_LOOPBACK 0x4000
154 /* Vitesse VSC8244 Extended PHY Control Register 1 */
155 #define MIIM_VSC8244_EPHY_CON 0x17
156 #define MIIM_VSC8244_EPHYCON_INIT 0x0006
158 /* Vitesse VSC8244 Serial LED Control Register */
159 #define MIIM_VSC8244_LED_CON 0x1b
160 #define MIIM_VSC8244_LEDCON_INIT 0xF011
162 /* Entry for Vitesse VSC8601 regs starts here (Not complete) */
163 /* Vitesse VSC8601 Extended PHY Control Register 1 */
164 #define MIIM_VSC8601_EPHY_CON 0x17
165 #define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
167 /* 88E1011 PHY Status Register */
168 #define MIIM_88E1011_PHY_STATUS 0x11
169 #define MIIM_88E1011_PHYSTAT_SPEED 0xc000
170 #define MIIM_88E1011_PHYSTAT_GBIT 0x8000
171 #define MIIM_88E1011_PHYSTAT_100 0x4000
172 #define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000
173 #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
174 #define MIIM_88E1011_PHYSTAT_LINK 0x0400
176 #define MIIM_88E1011_PHY_SCR 0x10
177 #define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
179 /* 88E1111 PHY LED Control Register */
180 #define MIIM_88E1111_PHY_LED_CONTROL 24
181 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100
182 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C
184 /* 88E1145 Extended PHY Specific Control Register */
185 #define MIIM_88E1145_PHY_EXT_CR 20
186 #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
187 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
189 #define MIIM_88E1145_PHY_PAGE 29
190 #define MIIM_88E1145_PHY_CAL_OV 30
192 /* RTL8211B PHY Status Register */
193 #define MIIM_RTL8211B_PHY_STATUS 0x11
194 #define MIIM_RTL8211B_PHYSTAT_SPEED 0xc000
195 #define MIIM_RTL8211B_PHYSTAT_GBIT 0x8000
196 #define MIIM_RTL8211B_PHYSTAT_100 0x4000
197 #define MIIM_RTL8211B_PHYSTAT_DUPLEX 0x2000
198 #define MIIM_RTL8211B_PHYSTAT_SPDDONE 0x0800
199 #define MIIM_RTL8211B_PHYSTAT_LINK 0x0400
201 /* DM9161 Control register values */
202 #define MIIM_DM9161_CR_STOP 0x0400
203 #define MIIM_DM9161_CR_RSTAN 0x1200
205 #define MIIM_DM9161_SCR 0x10
206 #define MIIM_DM9161_SCR_INIT 0x0610
208 /* DM9161 Specified Configuration and Status Register */
209 #define MIIM_DM9161_SCSR 0x11
210 #define MIIM_DM9161_SCSR_100F 0x8000
211 #define MIIM_DM9161_SCSR_100H 0x4000
212 #define MIIM_DM9161_SCSR_10F 0x2000
213 #define MIIM_DM9161_SCSR_10H 0x1000
215 /* DM9161 10BT Configuration/Status */
216 #define MIIM_DM9161_10BTCSR 0x12
217 #define MIIM_DM9161_10BTCSR_INIT 0x7800
219 /* LXT971 Status 2 registers */
220 #define MIIM_LXT971_SR2 0x11 /* Status Register 2 */
221 #define MIIM_LXT971_SR2_SPEED_MASK 0x4200
222 #define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */
223 #define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */
224 #define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
225 #define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */
227 /* DP83865 Control register values */
228 #define MIIM_DP83865_CR_INIT 0x9200
230 /* DP83865 Link and Auto-Neg Status Register */
231 #define MIIM_DP83865_LANR 0x11
232 #define MIIM_DP83865_SPD_MASK 0x0018
233 #define MIIM_DP83865_SPD_1000 0x0010
234 #define MIIM_DP83865_SPD_100 0x0008
235 #define MIIM_DP83865_DPX_FULL 0x0002
237 #define MIIM_READ_COMMAND 0x00000001
239 #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
241 #define MINFLR_INIT_SETTINGS 0x00000040
243 #define DMACTRL_INIT_SETTINGS 0x000000c3
244 #define DMACTRL_GRS 0x00000010
245 #define DMACTRL_GTS 0x00000008
247 #define TSTAT_CLEAR_THALT 0x80000000
248 #define RSTAT_CLEAR_RHALT 0x00800000
251 #define IEVENT_INIT_CLEAR 0xffffffff
252 #define IEVENT_BABR 0x80000000
253 #define IEVENT_RXC 0x40000000
254 #define IEVENT_BSY 0x20000000
255 #define IEVENT_EBERR 0x10000000
256 #define IEVENT_MSRO 0x04000000
257 #define IEVENT_GTSC 0x02000000
258 #define IEVENT_BABT 0x01000000
259 #define IEVENT_TXC 0x00800000
260 #define IEVENT_TXE 0x00400000
261 #define IEVENT_TXB 0x00200000
262 #define IEVENT_TXF 0x00100000
263 #define IEVENT_IE 0x00080000
264 #define IEVENT_LC 0x00040000
265 #define IEVENT_CRL 0x00020000
266 #define IEVENT_XFUN 0x00010000
267 #define IEVENT_RXB0 0x00008000
268 #define IEVENT_GRSC 0x00000100
269 #define IEVENT_RXF0 0x00000080
271 #define IMASK_INIT_CLEAR 0x00000000
272 #define IMASK_TXEEN 0x00400000
273 #define IMASK_TXBEN 0x00200000
274 #define IMASK_TXFEN 0x00100000
275 #define IMASK_RXFEN0 0x00000080
278 /* Default Attribute fields */
279 #define ATTR_INIT_SETTINGS 0x000000c0
280 #define ATTRELI_INIT_SETTINGS 0x00000000
283 /* TxBD status field bits */
284 #define TXBD_READY 0x8000
285 #define TXBD_PADCRC 0x4000
286 #define TXBD_WRAP 0x2000
287 #define TXBD_INTERRUPT 0x1000
288 #define TXBD_LAST 0x0800
289 #define TXBD_CRC 0x0400
290 #define TXBD_DEF 0x0200
291 #define TXBD_HUGEFRAME 0x0080
292 #define TXBD_LATECOLLISION 0x0080
293 #define TXBD_RETRYLIMIT 0x0040
294 #define TXBD_RETRYCOUNTMASK 0x003c
295 #define TXBD_UNDERRUN 0x0002
296 #define TXBD_STATS 0x03ff
298 /* RxBD status field bits */
299 #define RXBD_EMPTY 0x8000
300 #define RXBD_RO1 0x4000
301 #define RXBD_WRAP 0x2000
302 #define RXBD_INTERRUPT 0x1000
303 #define RXBD_LAST 0x0800
304 #define RXBD_FIRST 0x0400
305 #define RXBD_MISS 0x0100
306 #define RXBD_BROADCAST 0x0080
307 #define RXBD_MULTICAST 0x0040
308 #define RXBD_LARGE 0x0020
309 #define RXBD_NONOCTET 0x0010
310 #define RXBD_SHORT 0x0008
311 #define RXBD_CRCERR 0x0004
312 #define RXBD_OVERRUN 0x0002
313 #define RXBD_TRUNCATED 0x0001
314 #define RXBD_STATS 0x003f
318 ushort status; /* Status Fields */
319 ushort length; /* Buffer length */
320 uint bufPtr; /* Buffer Pointer */
325 ushort status; /* Status Fields */
326 ushort length; /* Buffer Length */
327 uint bufPtr; /* Buffer Pointer */
330 typedef struct rmon_mib
332 /* Transmit and Receive Counters */
333 uint tr64; /* Transmit and Receive 64-byte Frame Counter */
334 uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */
335 uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */
336 uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */
337 uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */
338 uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */
339 uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
340 /* Receive Counters */
341 uint rbyt; /* Receive Byte Counter */
342 uint rpkt; /* Receive Packet Counter */
343 uint rfcs; /* Receive FCS Error Counter */
344 uint rmca; /* Receive Multicast Packet (Counter) */
345 uint rbca; /* Receive Broadcast Packet */
346 uint rxcf; /* Receive Control Frame Packet */
347 uint rxpf; /* Receive Pause Frame Packet */
348 uint rxuo; /* Receive Unknown OP Code */
349 uint raln; /* Receive Alignment Error */
350 uint rflr; /* Receive Frame Length Error */
351 uint rcde; /* Receive Code Error */
352 uint rcse; /* Receive Carrier Sense Error */
353 uint rund; /* Receive Undersize Packet */
354 uint rovr; /* Receive Oversize Packet */
355 uint rfrg; /* Receive Fragments */
356 uint rjbr; /* Receive Jabber */
357 uint rdrp; /* Receive Drop */
358 /* Transmit Counters */
359 uint tbyt; /* Transmit Byte Counter */
360 uint tpkt; /* Transmit Packet */
361 uint tmca; /* Transmit Multicast Packet */
362 uint tbca; /* Transmit Broadcast Packet */
363 uint txpf; /* Transmit Pause Control Frame */
364 uint tdfr; /* Transmit Deferral Packet */
365 uint tedf; /* Transmit Excessive Deferral Packet */
366 uint tscl; /* Transmit Single Collision Packet */
368 uint tmcl; /* Transmit Multiple Collision Packet */
369 uint tlcl; /* Transmit Late Collision Packet */
370 uint txcl; /* Transmit Excessive Collision Packet */
371 uint tncl; /* Transmit Total Collision */
375 uint tdrp; /* Transmit Drop Frame */
376 uint tjbr; /* Transmit Jabber Frame */
377 uint tfcs; /* Transmit FCS Error */
378 uint txcf; /* Transmit Control Frame */
379 uint tovr; /* Transmit Oversize Frame */
380 uint tund; /* Transmit Undersize Frame */
381 uint tfrg; /* Transmit Fragments Frame */
382 /* General Registers */
383 uint car1; /* Carry Register One */
384 uint car2; /* Carry Register Two */
385 uint cam1; /* Carry Register One Mask */
386 uint cam2; /* Carry Register Two Mask */
389 typedef struct tsec_hash_regs
391 uint iaddr0; /* Individual Address Register 0 */
392 uint iaddr1; /* Individual Address Register 1 */
393 uint iaddr2; /* Individual Address Register 2 */
394 uint iaddr3; /* Individual Address Register 3 */
395 uint iaddr4; /* Individual Address Register 4 */
396 uint iaddr5; /* Individual Address Register 5 */
397 uint iaddr6; /* Individual Address Register 6 */
398 uint iaddr7; /* Individual Address Register 7 */
400 uint gaddr0; /* Group Address Register 0 */
401 uint gaddr1; /* Group Address Register 1 */
402 uint gaddr2; /* Group Address Register 2 */
403 uint gaddr3; /* Group Address Register 3 */
404 uint gaddr4; /* Group Address Register 4 */
405 uint gaddr5; /* Group Address Register 5 */
406 uint gaddr6; /* Group Address Register 6 */
407 uint gaddr7; /* Group Address Register 7 */
413 /* General Control and Status Registers (0x2_n000) */
416 uint ievent; /* Interrupt Event */
417 uint imask; /* Interrupt Mask */
418 uint edis; /* Error Disabled */
420 uint ecntrl; /* Ethernet Control */
421 uint minflr; /* Minimum Frame Length */
422 uint ptv; /* Pause Time Value */
423 uint dmactrl; /* DMA Control */
424 uint tbipa; /* TBI PHY Address */
429 /* Transmit Control and Status Registers (0x2_n100) */
430 uint tctrl; /* Transmit Control */
431 uint tstat; /* Transmit Status */
433 uint tbdlen; /* Tx BD Data Length */
435 uint ctbptr; /* Current TxBD Pointer */
437 uint tbptr; /* TxBD Pointer */
441 uint tbase; /* TxBD Base Address */
443 uint ostbd; /* Out of Sequence TxBD */
444 uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
447 /* Receive Control and Status Registers (0x2_n300) */
448 uint rctrl; /* Receive Control */
449 uint rstat; /* Receive Status */
451 uint rbdlen; /* RxBD Data Length */
454 uint crbptr; /* Current Receive Buffer Pointer */
456 uint mrblr; /* Maximum Receive Buffer Length */
458 uint rbptr; /* RxBD Pointer */
462 uint rbase; /* RxBD Base Address */
465 /* MAC Registers (0x2_n500) */
466 uint maccfg1; /* MAC Configuration #1 */
467 uint maccfg2; /* MAC Configuration #2 */
468 uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */
469 uint hafdup; /* Half-duplex */
470 uint maxfrm; /* Maximum Frame */
476 uint miimcfg; /* MII Management: Configuration */
477 uint miimcom; /* MII Management: Command */
478 uint miimadd; /* MII Management: Address */
479 uint miimcon; /* MII Management: Control */
480 uint miimstat; /* MII Management: Status */
481 uint miimind; /* MII Management: Indicators */
485 uint ifstat; /* Interface Status */
486 uint macstnaddr1; /* Station Address, part 1 */
487 uint macstnaddr2; /* Station Address, part 2 */
493 /* RMON MIB Registers (0x2_n680-0x2_n73c) */
497 /* Hash Function Registers (0x2_n800) */
502 /* Pattern Registers (0x2_nb00) */
504 uint attr; /* Default Attribute Register */
505 uint attreli; /* Default Attribute Extract Length and Index */
507 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
511 #define TSEC_GIGABIT (1)
513 /* This flag currently only has
514 * meaning if we're using the eTSEC */
515 #define TSEC_REDUCED (1 << 1)
517 struct tsec_private {
518 volatile tsec_t *regs;
519 volatile tsec_t *phyregs;
520 struct phy_info *phyinfo;
530 * struct phy_cmd: A command for reading or writing a PHY register
532 * mii_reg: The register to read or write
534 * mii_data: For writes, the value to put in the register.
535 * A value of -1 indicates this is a read.
537 * funct: A function pointer which is invoked for each command.
538 * For reads, this function will be passed the value read
539 * from the PHY, and process it.
540 * For writes, the result of this function will be written
541 * to the PHY register
546 uint (*funct) (uint mii_reg, struct tsec_private* priv);
549 /* struct phy_info: a structure which defines attributes for a PHY
551 * id will contain a number which represents the PHY. During
552 * startup, the driver will poll the PHY to find out what its
553 * UID--as defined by registers 2 and 3--is. The 32-bit result
554 * gotten from the PHY will be shifted right by "shift" bits to
555 * discard any bits which may change based on revision numbers
556 * unimportant to functionality
558 * The struct phy_cmd entries represent pointers to an arrays of
559 * commands which tell the driver what to do to the PHY.
565 /* Called to configure the PHY, and modify the controller
566 * based on the results */
567 struct phy_cmd *config;
569 /* Called when starting up the controller */
570 struct phy_cmd *startup;
572 /* Called when bringing down the controller */
573 struct phy_cmd *shutdown;
576 #endif /* __TSEC_H */