2 * (C) Copyright 2011 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * Based on Xilinx gmac driver:
7 * (C) Copyright 2011 Xilinx
9 * SPDX-License-Identifier: GPL-2.0+
22 #include <asm/arch/hardware.h>
23 #include <asm/arch/sys_proto.h>
25 #if !defined(CONFIG_PHYLIB)
26 # error XILINX_GEM_ETHERNET requires PHYLIB
29 /* Bit/mask specification */
30 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
31 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
32 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
33 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
34 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
36 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
37 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
38 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
40 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
41 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
42 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
44 /* Wrap bit, last descriptor */
45 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
46 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
48 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
49 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
50 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
51 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
53 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
54 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
55 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
56 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
57 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
58 #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
60 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN | \
61 ZYNQ_GEM_NWCFG_FSREM | \
62 ZYNQ_GEM_NWCFG_MDCCLKDIV)
64 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
66 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
67 /* Use full configured addressable space (8 Kb) */
68 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
69 /* Use full configured addressable space (4 Kb) */
70 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
71 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
72 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
74 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
75 ZYNQ_GEM_DMACR_RXSIZE | \
76 ZYNQ_GEM_DMACR_TXSIZE | \
79 /* Use MII register 1 (MII status register) to detect PHY */
80 #define PHY_DETECT_REG 1
82 /* Mask used to verify certain PHY features (or register contents)
83 * in the register above:
84 * 0x1000: 10Mbps full duplex support
85 * 0x0800: 10Mbps half duplex support
86 * 0x0008: Auto-negotiation support
88 #define PHY_DETECT_MASK 0x1808
90 /* TX BD status masks */
91 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
92 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
93 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
95 /* Clock frequencies for different speeds */
96 #define ZYNQ_GEM_FREQUENCY_10 2500000UL
97 #define ZYNQ_GEM_FREQUENCY_100 25000000UL
98 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
100 /* Device registers */
101 struct zynq_gem_regs {
102 u32 nwctrl; /* Network Control reg */
103 u32 nwcfg; /* Network Config reg */
104 u32 nwsr; /* Network Status reg */
106 u32 dmacr; /* DMA Control reg */
107 u32 txsr; /* TX Status reg */
108 u32 rxqbase; /* RX Q Base address reg */
109 u32 txqbase; /* TX Q Base address reg */
110 u32 rxsr; /* RX Status reg */
112 u32 idr; /* Interrupt Disable reg */
114 u32 phymntnc; /* Phy Maintaince reg */
116 u32 hashl; /* Hash Low address reg */
117 u32 hashh; /* Hash High address reg */
120 u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */
121 u32 match[4]; /* Type ID1 Match reg */
123 u32 stat[44]; /* Octects transmitted Low reg - stat start */
128 u32 addr; /* Next descriptor pointer */
133 /* Page table entries are set to 1MB, or multiples of 1MB
134 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
136 #define BD_SPACE 0x100000
137 /* BD separation space */
138 #define BD_SEPRN_SPACE 64
140 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
141 struct zynq_gem_priv {
142 struct emac_bd *tx_bd;
143 struct emac_bd *rx_bd;
150 struct phy_device *phydev;
154 static inline int mdio_wait(struct eth_device *dev)
156 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
159 /* Wait till MDIO interface is ready to accept a new transaction. */
161 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
167 printf("%s: Timeout\n", __func__);
174 static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
178 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
183 /* Construct mgtcr mask for the operation */
184 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
185 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
186 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
188 /* Write mgtcr and wait for completion */
189 writel(mgtcr, ®s->phymntnc);
194 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
195 *data = readl(®s->phymntnc);
200 static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
202 return phy_setup_op(dev, phy_addr, regnum,
203 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
206 static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
208 return phy_setup_op(dev, phy_addr, regnum,
209 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
212 static void phy_detection(struct eth_device *dev)
216 struct zynq_gem_priv *priv = dev->priv;
218 if (priv->phyaddr != -1) {
219 phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
220 if ((phyreg != 0xFFFF) &&
221 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
222 /* Found a valid PHY address */
223 debug("Default phy address %d is valid\n",
227 debug("PHY address is not setup correctly %d\n",
233 debug("detecting phy address\n");
234 if (priv->phyaddr == -1) {
235 /* detect the PHY address */
236 for (i = 31; i >= 0; i--) {
237 phyread(dev, i, PHY_DETECT_REG, &phyreg);
238 if ((phyreg != 0xFFFF) &&
239 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
240 /* Found a valid PHY address */
242 debug("Found valid phy address, %d\n", i);
247 printf("PHY is not detected\n");
250 static int zynq_gem_setup_mac(struct eth_device *dev)
252 u32 i, macaddrlow, macaddrhigh;
253 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
255 /* Set the MAC bits [31:0] in BOT */
256 macaddrlow = dev->enetaddr[0];
257 macaddrlow |= dev->enetaddr[1] << 8;
258 macaddrlow |= dev->enetaddr[2] << 16;
259 macaddrlow |= dev->enetaddr[3] << 24;
261 /* Set MAC bits [47:32] in TOP */
262 macaddrhigh = dev->enetaddr[4];
263 macaddrhigh |= dev->enetaddr[5] << 8;
265 for (i = 0; i < 4; i++) {
266 writel(0, ®s->laddr[i][LADDR_LOW]);
267 writel(0, ®s->laddr[i][LADDR_HIGH]);
268 /* Do not use MATCHx register */
269 writel(0, ®s->match[i]);
272 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
273 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
278 static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
281 unsigned long clk_rate = 0;
282 struct phy_device *phydev;
283 const u32 stat_size = (sizeof(struct zynq_gem_regs) -
284 offsetof(struct zynq_gem_regs, stat)) / 4;
285 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
286 struct zynq_gem_priv *priv = dev->priv;
287 const u32 supported = SUPPORTED_10baseT_Half |
288 SUPPORTED_10baseT_Full |
289 SUPPORTED_100baseT_Half |
290 SUPPORTED_100baseT_Full |
291 SUPPORTED_1000baseT_Half |
292 SUPPORTED_1000baseT_Full;
295 /* Disable all interrupts */
296 writel(0xFFFFFFFF, ®s->idr);
298 /* Disable the receiver & transmitter */
299 writel(0, ®s->nwctrl);
300 writel(0, ®s->txsr);
301 writel(0, ®s->rxsr);
302 writel(0, ®s->phymntnc);
304 /* Clear the Hash registers for the mac address
305 * pointed by AddressPtr
307 writel(0x0, ®s->hashl);
308 /* Write bits [63:32] in TOP */
309 writel(0x0, ®s->hashh);
311 /* Clear all counters */
312 for (i = 0; i <= stat_size; i++)
313 readl(®s->stat[i]);
315 /* Setup RxBD space */
316 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
318 for (i = 0; i < RX_BUF; i++) {
319 priv->rx_bd[i].status = 0xF0000000;
320 priv->rx_bd[i].addr =
321 ((u32)(priv->rxbuffers) +
322 (i * PKTSIZE_ALIGN));
324 /* WRAP bit to last BD */
325 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
326 /* Write RxBDs to IP */
327 writel((u32)priv->rx_bd, ®s->rxqbase);
329 /* Setup for DMA Configuration register */
330 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
332 /* Setup for Network Control register, MDIO, Rx and Tx enable */
333 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
340 /* interface - look at tsec */
341 phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
343 phydev->supported = supported | ADVERTISED_Pause |
344 ADVERTISED_Asym_Pause;
345 phydev->advertising = phydev->supported;
346 priv->phydev = phydev;
351 printf("%s: No link.\n", phydev->dev->name);
355 switch (phydev->speed) {
357 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
359 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
362 clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
363 ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
364 clk_rate = ZYNQ_GEM_FREQUENCY_100;
367 clk_rate = ZYNQ_GEM_FREQUENCY_10;
371 /* Change the rclk and clk only not using EMIO interface */
373 zynq_slcr_gem_clk_setup(dev->iobase !=
374 ZYNQ_GEM_BASEADDR0, clk_rate);
376 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
377 ZYNQ_GEM_NWCTRL_TXEN_MASK);
382 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
385 struct zynq_gem_priv *priv = dev->priv;
386 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
389 writel((u32)priv->tx_bd, ®s->txqbase);
392 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
394 priv->tx_bd->addr = (u32)ptr;
395 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
396 ZYNQ_GEM_TXBUF_LAST_MASK;
399 addr &= ~(ARCH_DMA_MINALIGN - 1);
400 size = roundup(len, ARCH_DMA_MINALIGN);
401 flush_dcache_range(addr, addr + size);
405 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
407 /* Read TX BD status */
408 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN)
409 printf("TX underrun\n");
410 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
411 printf("TX buffers exhausted in mid frame\n");
416 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
417 static int zynq_gem_recv(struct eth_device *dev)
420 struct zynq_gem_priv *priv = dev->priv;
421 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
422 struct emac_bd *first_bd;
424 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
427 if (!(current_bd->status &
428 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
429 printf("GEM: SOF or EOF not set for last buffer received!\n");
433 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
435 u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
436 addr &= ~(ARCH_DMA_MINALIGN - 1);
437 u32 size = roundup(frame_len, ARCH_DMA_MINALIGN);
438 invalidate_dcache_range(addr, addr + size);
440 NetReceive((u8 *)addr, frame_len);
442 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
443 priv->rx_first_buf = priv->rxbd_current;
445 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
446 current_bd->status = 0xF0000000; /* FIXME */
449 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
450 first_bd = &priv->rx_bd[priv->rx_first_buf];
451 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
452 first_bd->status = 0xF0000000;
455 if ((++priv->rxbd_current) >= RX_BUF)
456 priv->rxbd_current = 0;
462 static void zynq_gem_halt(struct eth_device *dev)
464 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
466 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
467 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
470 static int zynq_gem_miiphyread(const char *devname, uchar addr,
471 uchar reg, ushort *val)
473 struct eth_device *dev = eth_get_dev();
476 ret = phyread(dev, addr, reg, val);
477 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
481 static int zynq_gem_miiphy_write(const char *devname, uchar addr,
482 uchar reg, ushort val)
484 struct eth_device *dev = eth_get_dev();
486 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
487 return phywrite(dev, addr, reg, val);
490 int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio)
492 struct eth_device *dev;
493 struct zynq_gem_priv *priv;
496 dev = calloc(1, sizeof(*dev));
500 dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
501 if (dev->priv == NULL) {
507 /* Align rxbuffers to ARCH_DMA_MINALIGN */
508 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
509 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
511 /* Align bd_space to 1MB */
512 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
513 mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF);
515 /* Initialize the bd spaces for tx and rx bd's */
516 priv->tx_bd = (struct emac_bd *)bd_space;
517 priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE);
519 priv->phyaddr = phy_addr;
522 sprintf(dev->name, "Gem.%x", base_addr);
524 dev->iobase = base_addr;
526 dev->init = zynq_gem_init;
527 dev->halt = zynq_gem_halt;
528 dev->send = zynq_gem_send;
529 dev->recv = zynq_gem_recv;
530 dev->write_hwaddr = zynq_gem_setup_mac;
534 miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
535 priv->bus = miiphy_get_dev_by_name(dev->name);
540 #ifdef CONFIG_OF_CONTROL
541 int zynq_gem_of_init(const void *blob)
547 debug("ZYNQ GEM: Initialization\n");
550 offset = fdt_node_offset_by_compatible(blob, offset,
551 "xlnx,ps7-ethernet-1.00.a");
553 reg = fdtdec_get_addr(blob, offset, "reg");
554 if (reg != FDT_ADDR_T_NONE) {
555 offset = fdtdec_lookup_phandle(blob, offset,
558 phy_reg = fdtdec_get_addr(blob, offset,
563 debug("ZYNQ GEM: addr %x, phyaddr %x\n",
566 ret |= zynq_gem_initialize(NULL, reg,
570 debug("ZYNQ GEM: Can't get base address\n");
574 } while (offset != -1);