2 * (C) Copyright 2011 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * Based on Xilinx gmac driver:
7 * (C) Copyright 2011 Xilinx
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <asm/arch/sys_proto.h>
38 #if !defined(CONFIG_PHYLIB)
39 # error XILINX_GEM_ETHERNET requires PHYLIB
42 /* Bit/mask specification */
43 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
44 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
45 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
46 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
47 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
49 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
50 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
51 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
53 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
54 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
55 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
57 /* Wrap bit, last descriptor */
58 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
59 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
61 #define ZYNQ_GEM_TXSR_HRESPNOK_MASK 0x00000100 /* Transmit hresp not OK */
62 #define ZYNQ_GEM_TXSR_URUN_MASK 0x00000040 /* Transmit underrun */
63 /* Transmit buffs exhausted mid frame */
64 #define ZYNQ_GEM_TXSR_BUFEXH_MASK 0x00000010
66 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
67 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
68 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
69 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
71 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
72 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
73 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
74 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
75 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
76 #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
78 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN | \
79 ZYNQ_GEM_NWCFG_FSREM | \
80 ZYNQ_GEM_NWCFG_MDCCLKDIV)
82 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
84 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
85 /* Use full configured addressable space (8 Kb) */
86 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
87 /* Use full configured addressable space (4 Kb) */
88 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
89 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
90 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
92 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
93 ZYNQ_GEM_DMACR_RXSIZE | \
94 ZYNQ_GEM_DMACR_TXSIZE | \
97 /* Device registers */
98 struct zynq_gem_regs {
99 u32 nwctrl; /* Network Control reg */
100 u32 nwcfg; /* Network Config reg */
101 u32 nwsr; /* Network Status reg */
103 u32 dmacr; /* DMA Control reg */
104 u32 txsr; /* TX Status reg */
105 u32 rxqbase; /* RX Q Base address reg */
106 u32 txqbase; /* TX Q Base address reg */
107 u32 rxsr; /* RX Status reg */
109 u32 idr; /* Interrupt Disable reg */
111 u32 phymntnc; /* Phy Maintaince reg */
113 u32 hashl; /* Hash Low address reg */
114 u32 hashh; /* Hash High address reg */
117 u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */
118 u32 match[4]; /* Type ID1 Match reg */
120 u32 stat[44]; /* Octects transmitted Low reg - stat start */
125 u32 addr; /* Next descriptor pointer */
131 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
132 struct zynq_gem_priv {
133 struct emac_bd tx_bd;
134 struct emac_bd rx_bd[RX_BUF];
135 char rxbuffers[RX_BUF * PKTSIZE_ALIGN];
140 struct phy_device *phydev;
144 static inline int mdio_wait(struct eth_device *dev)
146 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
149 /* Wait till MDIO interface is ready to accept a new transaction. */
151 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
157 printf("%s: Timeout\n", __func__);
164 static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
168 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
173 /* Construct mgtcr mask for the operation */
174 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
175 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
176 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
178 /* Write mgtcr and wait for completion */
179 writel(mgtcr, ®s->phymntnc);
184 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
185 *data = readl(®s->phymntnc);
190 static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
192 return phy_setup_op(dev, phy_addr, regnum,
193 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
196 static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
198 return phy_setup_op(dev, phy_addr, regnum,
199 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
202 static int zynq_gem_setup_mac(struct eth_device *dev)
204 u32 i, macaddrlow, macaddrhigh;
205 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
207 /* Set the MAC bits [31:0] in BOT */
208 macaddrlow = dev->enetaddr[0];
209 macaddrlow |= dev->enetaddr[1] << 8;
210 macaddrlow |= dev->enetaddr[2] << 16;
211 macaddrlow |= dev->enetaddr[3] << 24;
213 /* Set MAC bits [47:32] in TOP */
214 macaddrhigh = dev->enetaddr[4];
215 macaddrhigh |= dev->enetaddr[5] << 8;
217 for (i = 0; i < 4; i++) {
218 writel(0, ®s->laddr[i][LADDR_LOW]);
219 writel(0, ®s->laddr[i][LADDR_HIGH]);
220 /* Do not use MATCHx register */
221 writel(0, ®s->match[i]);
224 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
225 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
230 static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
232 u32 i, rclk, clk = 0;
233 struct phy_device *phydev;
234 const u32 stat_size = (sizeof(struct zynq_gem_regs) -
235 offsetof(struct zynq_gem_regs, stat)) / 4;
236 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
237 struct zynq_gem_priv *priv = dev->priv;
238 const u32 supported = SUPPORTED_10baseT_Half |
239 SUPPORTED_10baseT_Full |
240 SUPPORTED_100baseT_Half |
241 SUPPORTED_100baseT_Full |
242 SUPPORTED_1000baseT_Half |
243 SUPPORTED_1000baseT_Full;
246 /* Disable all interrupts */
247 writel(0xFFFFFFFF, ®s->idr);
249 /* Disable the receiver & transmitter */
250 writel(0, ®s->nwctrl);
251 writel(0, ®s->txsr);
252 writel(0, ®s->rxsr);
253 writel(0, ®s->phymntnc);
255 /* Clear the Hash registers for the mac address
256 * pointed by AddressPtr
258 writel(0x0, ®s->hashl);
259 /* Write bits [63:32] in TOP */
260 writel(0x0, ®s->hashh);
262 /* Clear all counters */
263 for (i = 0; i <= stat_size; i++)
264 readl(®s->stat[i]);
266 /* Setup RxBD space */
267 memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd));
268 /* Create the RxBD ring */
269 memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers));
271 for (i = 0; i < RX_BUF; i++) {
272 priv->rx_bd[i].status = 0xF0000000;
273 priv->rx_bd[i].addr =
274 (u32)((char *)&(priv->rxbuffers) +
275 (i * PKTSIZE_ALIGN));
277 /* WRAP bit to last BD */
278 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
279 /* Write RxBDs to IP */
280 writel((u32)&(priv->rx_bd), ®s->rxqbase);
282 /* Setup for DMA Configuration register */
283 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
285 /* Setup for Network Control register, MDIO, Rx and Tx enable */
286 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
291 /* interface - look at tsec */
292 phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
294 phydev->supported = supported | ADVERTISED_Pause |
295 ADVERTISED_Asym_Pause;
296 phydev->advertising = phydev->supported;
297 priv->phydev = phydev;
301 switch (phydev->speed) {
303 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
305 rclk = (0 << 4) | (1 << 0);
306 clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
309 clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
310 ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
312 clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
317 clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
320 /* FIXME maybe better to define gem address in hardware.h */
321 zynq_slcr_gem_clk_setup(dev->iobase != 0xE000B000, rclk, clk);
323 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
324 ZYNQ_GEM_NWCTRL_TXEN_MASK);
329 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
332 struct zynq_gem_priv *priv = dev->priv;
333 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
334 const u32 mask = ZYNQ_GEM_TXSR_HRESPNOK_MASK | \
335 ZYNQ_GEM_TXSR_URUN_MASK | ZYNQ_GEM_TXSR_BUFEXH_MASK;
338 writel((u32)&(priv->tx_bd), ®s->txqbase);
341 memset((void *)&(priv->tx_bd), 0, sizeof(struct emac_bd));
343 priv->tx_bd.addr = (u32)ptr;
344 priv->tx_bd.status = len | ZYNQ_GEM_TXBUF_LAST_MASK;
347 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
349 /* Read the stat register to know if the packet has been transmitted */
350 status = readl(®s->txsr);
352 printf("Something has gone wrong here!? Status is 0x%x.\n",
355 /* Clear Tx status register before leaving . */
356 writel(status, ®s->txsr);
360 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
361 static int zynq_gem_recv(struct eth_device *dev)
364 struct zynq_gem_priv *priv = dev->priv;
365 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
366 struct emac_bd *first_bd;
368 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
371 if (!(current_bd->status &
372 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
373 printf("GEM: SOF or EOF not set for last buffer received!\n");
377 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
379 NetReceive((u8 *) (current_bd->addr &
380 ZYNQ_GEM_RXBUF_ADD_MASK), frame_len);
382 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
383 priv->rx_first_buf = priv->rxbd_current;
385 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
386 current_bd->status = 0xF0000000; /* FIXME */
389 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
390 first_bd = &priv->rx_bd[priv->rx_first_buf];
391 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
392 first_bd->status = 0xF0000000;
395 if ((++priv->rxbd_current) >= RX_BUF)
396 priv->rxbd_current = 0;
402 static void zynq_gem_halt(struct eth_device *dev)
404 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
406 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
407 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
410 static int zynq_gem_miiphyread(const char *devname, uchar addr,
411 uchar reg, ushort *val)
413 struct eth_device *dev = eth_get_dev();
416 ret = phyread(dev, addr, reg, val);
417 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
421 static int zynq_gem_miiphy_write(const char *devname, uchar addr,
422 uchar reg, ushort val)
424 struct eth_device *dev = eth_get_dev();
426 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
427 return phywrite(dev, addr, reg, val);
430 int zynq_gem_initialize(bd_t *bis, int base_addr)
432 struct eth_device *dev;
433 struct zynq_gem_priv *priv;
435 dev = calloc(1, sizeof(*dev));
439 dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
440 if (dev->priv == NULL) {
446 #ifdef CONFIG_PHY_ADDR
447 priv->phyaddr = CONFIG_PHY_ADDR;
452 sprintf(dev->name, "Gem.%x", base_addr);
454 dev->iobase = base_addr;
456 dev->init = zynq_gem_init;
457 dev->halt = zynq_gem_halt;
458 dev->send = zynq_gem_send;
459 dev->recv = zynq_gem_recv;
460 dev->write_hwaddr = zynq_gem_setup_mac;
464 miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
465 priv->bus = miiphy_get_dev_by_name(dev->name);