2 * (C) Copyright 2011 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * Based on Xilinx gmac driver:
7 * (C) Copyright 2011 Xilinx
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #if !defined(CONFIG_PHYLIB)
38 # error XILINX_GEM_ETHERNET requires PHYLIB
41 /* Bit/mask specification */
42 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
43 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
44 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
45 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
46 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
48 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
49 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
50 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
52 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
53 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
54 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
56 /* Wrap bit, last descriptor */
57 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
58 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
60 #define ZYNQ_GEM_TXSR_HRESPNOK_MASK 0x00000100 /* Transmit hresp not OK */
61 #define ZYNQ_GEM_TXSR_URUN_MASK 0x00000040 /* Transmit underrun */
62 /* Transmit buffs exhausted mid frame */
63 #define ZYNQ_GEM_TXSR_BUFEXH_MASK 0x00000010
65 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
66 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
67 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
68 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
70 #define ZYNQ_GEM_NWCFG_SPEED 0x00000001 /* 100 Mbps operation */
71 #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
72 #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
73 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
75 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_SPEED | \
76 ZYNQ_GEM_NWCFG_FDEN | \
77 ZYNQ_GEM_NWCFG_FSREM | \
78 ZYNQ_GEM_NWCFG_MDCCLKDIV)
80 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
82 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
83 /* Use full configured addressable space (8 Kb) */
84 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
85 /* Use full configured addressable space (4 Kb) */
86 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
87 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
88 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
90 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
91 ZYNQ_GEM_DMACR_RXSIZE | \
92 ZYNQ_GEM_DMACR_TXSIZE | \
95 /* Device registers */
96 struct zynq_gem_regs {
97 u32 nwctrl; /* Network Control reg */
98 u32 nwcfg; /* Network Config reg */
99 u32 nwsr; /* Network Status reg */
101 u32 dmacr; /* DMA Control reg */
102 u32 txsr; /* TX Status reg */
103 u32 rxqbase; /* RX Q Base address reg */
104 u32 txqbase; /* TX Q Base address reg */
105 u32 rxsr; /* RX Status reg */
107 u32 idr; /* Interrupt Disable reg */
109 u32 phymntnc; /* Phy Maintaince reg */
111 u32 hashl; /* Hash Low address reg */
112 u32 hashh; /* Hash High address reg */
115 u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */
116 u32 match[4]; /* Type ID1 Match reg */
118 u32 stat[44]; /* Octects transmitted Low reg - stat start */
123 u32 addr; /* Next descriptor pointer */
129 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
130 struct zynq_gem_priv {
131 struct emac_bd tx_bd;
132 struct emac_bd rx_bd[RX_BUF];
133 char rxbuffers[RX_BUF * PKTSIZE_ALIGN];
138 struct phy_device *phydev;
142 static inline int mdio_wait(struct eth_device *dev)
144 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
147 /* Wait till MDIO interface is ready to accept a new transaction. */
149 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
155 printf("%s: Timeout\n", __func__);
162 static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
166 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
171 /* Construct mgtcr mask for the operation */
172 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
173 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
174 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
176 /* Write mgtcr and wait for completion */
177 writel(mgtcr, ®s->phymntnc);
182 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
183 *data = readl(®s->phymntnc);
188 static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
190 return phy_setup_op(dev, phy_addr, regnum,
191 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
194 static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
196 return phy_setup_op(dev, phy_addr, regnum,
197 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
200 static int zynq_gem_setup_mac(struct eth_device *dev)
202 u32 i, macaddrlow, macaddrhigh;
203 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
205 /* Set the MAC bits [31:0] in BOT */
206 macaddrlow = dev->enetaddr[0];
207 macaddrlow |= dev->enetaddr[1] << 8;
208 macaddrlow |= dev->enetaddr[2] << 16;
209 macaddrlow |= dev->enetaddr[3] << 24;
211 /* Set MAC bits [47:32] in TOP */
212 macaddrhigh = dev->enetaddr[4];
213 macaddrhigh |= dev->enetaddr[5] << 8;
215 for (i = 0; i < 4; i++) {
216 writel(0, ®s->laddr[i][LADDR_LOW]);
217 writel(0, ®s->laddr[i][LADDR_HIGH]);
218 /* Do not use MATCHx register */
219 writel(0, ®s->match[i]);
222 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
223 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
228 static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
231 struct phy_device *phydev;
232 const u32 stat_size = (sizeof(struct zynq_gem_regs) -
233 offsetof(struct zynq_gem_regs, stat)) / 4;
234 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
235 struct zynq_gem_priv *priv = dev->priv;
236 const u32 supported = SUPPORTED_10baseT_Half |
237 SUPPORTED_10baseT_Full |
238 SUPPORTED_100baseT_Half |
239 SUPPORTED_100baseT_Full |
240 SUPPORTED_1000baseT_Half |
241 SUPPORTED_1000baseT_Full;
244 /* Disable all interrupts */
245 writel(0xFFFFFFFF, ®s->idr);
247 /* Disable the receiver & transmitter */
248 writel(0, ®s->nwctrl);
249 writel(0, ®s->txsr);
250 writel(0, ®s->rxsr);
251 writel(0, ®s->phymntnc);
253 /* Clear the Hash registers for the mac address
254 * pointed by AddressPtr
256 writel(0x0, ®s->hashl);
257 /* Write bits [63:32] in TOP */
258 writel(0x0, ®s->hashh);
260 /* Clear all counters */
261 for (i = 0; i <= stat_size; i++)
262 readl(®s->stat[i]);
264 /* Setup RxBD space */
265 memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd));
266 /* Create the RxBD ring */
267 memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers));
269 for (i = 0; i < RX_BUF; i++) {
270 priv->rx_bd[i].status = 0xF0000000;
271 priv->rx_bd[i].addr =
272 (u32)((char *)&(priv->rxbuffers) +
273 (i * PKTSIZE_ALIGN));
275 /* WRAP bit to last BD */
276 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
277 /* Write RxBDs to IP */
278 writel((u32)&(priv->rx_bd), ®s->rxqbase);
281 /* Setup Network Configuration register */
282 writel(ZYNQ_GEM_NWCFG_INIT, ®s->nwcfg);
284 /* Setup for DMA Configuration register */
285 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
287 /* Setup for Network Control register, MDIO, Rx and Tx enable */
288 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK |
289 ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK);
294 /* interface - look at tsec */
295 phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
297 phydev->supported &= supported;
298 phydev->advertising = phydev->supported;
299 priv->phydev = phydev;
306 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
309 struct zynq_gem_priv *priv = dev->priv;
310 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
311 const u32 mask = ZYNQ_GEM_TXSR_HRESPNOK_MASK | \
312 ZYNQ_GEM_TXSR_URUN_MASK | ZYNQ_GEM_TXSR_BUFEXH_MASK;
315 writel((u32)&(priv->tx_bd), ®s->txqbase);
318 memset((void *)&(priv->tx_bd), 0, sizeof(struct emac_bd));
320 priv->tx_bd.addr = (u32)ptr;
321 priv->tx_bd.status = len | ZYNQ_GEM_TXBUF_LAST_MASK;
324 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
326 /* Read the stat register to know if the packet has been transmitted */
327 status = readl(®s->txsr);
329 printf("Something has gone wrong here!? Status is 0x%x.\n",
332 /* Clear Tx status register before leaving . */
333 writel(status, ®s->txsr);
337 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
338 static int zynq_gem_recv(struct eth_device *dev)
341 struct zynq_gem_priv *priv = dev->priv;
342 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
343 struct emac_bd *first_bd;
345 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
348 if (!(current_bd->status &
349 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
350 printf("GEM: SOF or EOF not set for last buffer received!\n");
354 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
356 NetReceive((u8 *) (current_bd->addr &
357 ZYNQ_GEM_RXBUF_ADD_MASK), frame_len);
359 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
360 priv->rx_first_buf = priv->rxbd_current;
362 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
363 current_bd->status = 0xF0000000; /* FIXME */
366 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
367 first_bd = &priv->rx_bd[priv->rx_first_buf];
368 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
369 first_bd->status = 0xF0000000;
372 if ((++priv->rxbd_current) >= RX_BUF)
373 priv->rxbd_current = 0;
379 static void zynq_gem_halt(struct eth_device *dev)
381 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
383 /* Disable the receiver & transmitter */
384 writel(0, ®s->nwctrl);
387 static int zynq_gem_miiphyread(const char *devname, uchar addr,
388 uchar reg, ushort *val)
390 struct eth_device *dev = eth_get_dev();
393 ret = phyread(dev, addr, reg, val);
394 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
398 static int zynq_gem_miiphy_write(const char *devname, uchar addr,
399 uchar reg, ushort val)
401 struct eth_device *dev = eth_get_dev();
403 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
404 return phywrite(dev, addr, reg, val);
407 int zynq_gem_initialize(bd_t *bis, int base_addr)
409 struct eth_device *dev;
410 struct zynq_gem_priv *priv;
412 dev = calloc(1, sizeof(*dev));
416 dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
417 if (dev->priv == NULL) {
423 #ifdef CONFIG_PHY_ADDR
424 priv->phyaddr = CONFIG_PHY_ADDR;
429 sprintf(dev->name, "Gem.%x", base_addr);
431 dev->iobase = base_addr;
433 dev->init = zynq_gem_init;
434 dev->halt = zynq_gem_halt;
435 dev->send = zynq_gem_send;
436 dev->recv = zynq_gem_recv;
437 dev->write_hwaddr = zynq_gem_setup_mac;
441 miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
442 priv->bus = miiphy_get_dev_by_name(dev->name);