2 * (C) Copyright 2011 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * Based on Xilinx gmac driver:
7 * (C) Copyright 2011 Xilinx
9 * SPDX-License-Identifier: GPL-2.0+
24 #include <asm/system.h>
25 #include <asm/arch/hardware.h>
26 #include <asm/arch/sys_proto.h>
27 #include <linux/errno.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 /* Bit/mask specification */
32 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
33 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
34 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
35 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
36 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
38 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
39 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
40 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
42 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
43 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
44 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
46 /* Wrap bit, last descriptor */
47 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
48 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
49 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
51 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
52 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
53 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
54 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
56 #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
57 #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
58 #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
59 #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
60 #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
61 #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
63 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
65 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
69 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
71 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
74 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
75 ZYNQ_GEM_NWCFG_FDEN | \
76 ZYNQ_GEM_NWCFG_FSREM | \
77 ZYNQ_GEM_NWCFG_MDCCLKDIV)
79 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
81 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
82 /* Use full configured addressable space (8 Kb) */
83 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
84 /* Use full configured addressable space (4 Kb) */
85 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
86 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
87 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
89 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
90 ZYNQ_GEM_DMACR_RXSIZE | \
91 ZYNQ_GEM_DMACR_TXSIZE | \
94 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
96 #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
98 /* Use MII register 1 (MII status register) to detect PHY */
99 #define PHY_DETECT_REG 1
101 /* Mask used to verify certain PHY features (or register contents)
102 * in the register above:
103 * 0x1000: 10Mbps full duplex support
104 * 0x0800: 10Mbps half duplex support
105 * 0x0008: Auto-negotiation support
107 #define PHY_DETECT_MASK 0x1808
109 /* TX BD status masks */
110 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
111 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
112 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
114 /* Clock frequencies for different speeds */
115 #define ZYNQ_GEM_FREQUENCY_10 2500000UL
116 #define ZYNQ_GEM_FREQUENCY_100 25000000UL
117 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
119 /* Device registers */
120 struct zynq_gem_regs {
121 u32 nwctrl; /* 0x0 - Network Control reg */
122 u32 nwcfg; /* 0x4 - Network Config reg */
123 u32 nwsr; /* 0x8 - Network Status reg */
125 u32 dmacr; /* 0x10 - DMA Control reg */
126 u32 txsr; /* 0x14 - TX Status reg */
127 u32 rxqbase; /* 0x18 - RX Q Base address reg */
128 u32 txqbase; /* 0x1c - TX Q Base address reg */
129 u32 rxsr; /* 0x20 - RX Status reg */
131 u32 idr; /* 0x2c - Interrupt Disable reg */
133 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
135 u32 hashl; /* 0x80 - Hash Low address reg */
136 u32 hashh; /* 0x84 - Hash High address reg */
139 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
140 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
143 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
147 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
149 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
154 u32 addr; /* Next descriptor pointer */
159 /* Page table entries are set to 1MB, or multiples of 1MB
160 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
162 #define BD_SPACE 0x100000
163 /* BD separation space */
164 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
166 /* Setup the first free TX descriptor */
167 #define TX_FREE_DESC 2
169 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
170 struct zynq_gem_priv {
171 struct emac_bd *tx_bd;
172 struct emac_bd *rx_bd;
179 struct zynq_gem_regs *iobase;
180 phy_interface_t interface;
181 struct phy_device *phydev;
186 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
190 struct zynq_gem_regs *regs = priv->iobase;
193 err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
198 /* Construct mgtcr mask for the operation */
199 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
200 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
201 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
203 /* Write mgtcr and wait for completion */
204 writel(mgtcr, ®s->phymntnc);
206 err = wait_for_bit(__func__, ®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
211 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
212 *data = readl(®s->phymntnc);
217 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
218 u32 regnum, u16 *val)
222 ret = phy_setup_op(priv, phy_addr, regnum,
223 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
226 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
227 phy_addr, regnum, *val);
232 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
233 u32 regnum, u16 data)
235 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
238 return phy_setup_op(priv, phy_addr, regnum,
239 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
242 static int phy_detection(struct udevice *dev)
246 struct zynq_gem_priv *priv = dev->priv;
248 if (priv->phyaddr != -1) {
249 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
250 if ((phyreg != 0xFFFF) &&
251 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
252 /* Found a valid PHY address */
253 debug("Default phy address %d is valid\n",
257 debug("PHY address is not setup correctly %d\n",
263 debug("detecting phy address\n");
264 if (priv->phyaddr == -1) {
265 /* detect the PHY address */
266 for (i = 31; i >= 0; i--) {
267 phyread(priv, i, PHY_DETECT_REG, &phyreg);
268 if ((phyreg != 0xFFFF) &&
269 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
270 /* Found a valid PHY address */
272 debug("Found valid phy address, %d\n", i);
277 printf("PHY is not detected\n");
281 static int zynq_gem_setup_mac(struct udevice *dev)
283 u32 i, macaddrlow, macaddrhigh;
284 struct eth_pdata *pdata = dev_get_platdata(dev);
285 struct zynq_gem_priv *priv = dev_get_priv(dev);
286 struct zynq_gem_regs *regs = priv->iobase;
288 /* Set the MAC bits [31:0] in BOT */
289 macaddrlow = pdata->enetaddr[0];
290 macaddrlow |= pdata->enetaddr[1] << 8;
291 macaddrlow |= pdata->enetaddr[2] << 16;
292 macaddrlow |= pdata->enetaddr[3] << 24;
294 /* Set MAC bits [47:32] in TOP */
295 macaddrhigh = pdata->enetaddr[4];
296 macaddrhigh |= pdata->enetaddr[5] << 8;
298 for (i = 0; i < 4; i++) {
299 writel(0, ®s->laddr[i][LADDR_LOW]);
300 writel(0, ®s->laddr[i][LADDR_HIGH]);
301 /* Do not use MATCHx register */
302 writel(0, ®s->match[i]);
305 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
306 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
311 static int zynq_phy_init(struct udevice *dev)
314 struct zynq_gem_priv *priv = dev_get_priv(dev);
315 struct zynq_gem_regs *regs = priv->iobase;
316 const u32 supported = SUPPORTED_10baseT_Half |
317 SUPPORTED_10baseT_Full |
318 SUPPORTED_100baseT_Half |
319 SUPPORTED_100baseT_Full |
320 SUPPORTED_1000baseT_Half |
321 SUPPORTED_1000baseT_Full;
323 /* Enable only MDIO bus */
324 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl);
326 if (priv->interface != PHY_INTERFACE_MODE_SGMII) {
327 ret = phy_detection(dev);
329 printf("GEM PHY init failed\n");
334 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
339 priv->phydev->supported = supported | ADVERTISED_Pause |
340 ADVERTISED_Asym_Pause;
341 priv->phydev->advertising = priv->phydev->supported;
343 if (priv->phy_of_handle > 0)
344 priv->phydev->dev->of_offset = priv->phy_of_handle;
346 return phy_config(priv->phydev);
349 static int zynq_gem_init(struct udevice *dev)
353 unsigned long clk_rate = 0;
354 struct zynq_gem_priv *priv = dev_get_priv(dev);
355 struct zynq_gem_regs *regs = priv->iobase;
356 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
357 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
360 /* Disable all interrupts */
361 writel(0xFFFFFFFF, ®s->idr);
363 /* Disable the receiver & transmitter */
364 writel(0, ®s->nwctrl);
365 writel(0, ®s->txsr);
366 writel(0, ®s->rxsr);
367 writel(0, ®s->phymntnc);
369 /* Clear the Hash registers for the mac address
370 * pointed by AddressPtr
372 writel(0x0, ®s->hashl);
373 /* Write bits [63:32] in TOP */
374 writel(0x0, ®s->hashh);
376 /* Clear all counters */
377 for (i = 0; i < STAT_SIZE; i++)
378 readl(®s->stat[i]);
380 /* Setup RxBD space */
381 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
383 for (i = 0; i < RX_BUF; i++) {
384 priv->rx_bd[i].status = 0xF0000000;
385 priv->rx_bd[i].addr =
386 ((ulong)(priv->rxbuffers) +
387 (i * PKTSIZE_ALIGN));
389 /* WRAP bit to last BD */
390 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
391 /* Write RxBDs to IP */
392 writel((ulong)priv->rx_bd, ®s->rxqbase);
394 /* Setup for DMA Configuration register */
395 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
397 /* Setup for Network Control register, MDIO, Rx and Tx enable */
398 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
400 /* Disable the second priority queue */
401 dummy_tx_bd->addr = 0;
402 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
403 ZYNQ_GEM_TXBUF_LAST_MASK|
404 ZYNQ_GEM_TXBUF_USED_MASK;
406 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
407 ZYNQ_GEM_RXBUF_NEW_MASK;
408 dummy_rx_bd->status = 0;
409 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd +
410 sizeof(dummy_tx_bd));
411 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd +
412 sizeof(dummy_rx_bd));
414 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr);
415 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr);
420 ret = phy_startup(priv->phydev);
424 if (!priv->phydev->link) {
425 printf("%s: No link.\n", priv->phydev->dev->name);
429 nwconfig = ZYNQ_GEM_NWCFG_INIT;
431 if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
432 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
433 ZYNQ_GEM_NWCFG_PCS_SEL;
435 writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
440 switch (priv->phydev->speed) {
442 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
444 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
447 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
449 clk_rate = ZYNQ_GEM_FREQUENCY_100;
452 clk_rate = ZYNQ_GEM_FREQUENCY_10;
456 /* Change the rclk and clk only not using EMIO interface */
458 zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
459 ZYNQ_GEM_BASEADDR0, clk_rate);
461 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
462 ZYNQ_GEM_NWCTRL_TXEN_MASK);
467 static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
470 struct zynq_gem_priv *priv = dev_get_priv(dev);
471 struct zynq_gem_regs *regs = priv->iobase;
472 struct emac_bd *current_bd = &priv->tx_bd[1];
475 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
477 priv->tx_bd->addr = (ulong)ptr;
478 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
479 ZYNQ_GEM_TXBUF_LAST_MASK;
480 /* Dummy descriptor to mark it as the last in descriptor chain */
481 current_bd->addr = 0x0;
482 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
483 ZYNQ_GEM_TXBUF_LAST_MASK|
484 ZYNQ_GEM_TXBUF_USED_MASK;
487 writel((ulong)priv->tx_bd, ®s->txqbase);
490 addr &= ~(ARCH_DMA_MINALIGN - 1);
491 size = roundup(len, ARCH_DMA_MINALIGN);
492 flush_dcache_range(addr, addr + size);
494 addr = (ulong)priv->rxbuffers;
495 addr &= ~(ARCH_DMA_MINALIGN - 1);
496 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
497 flush_dcache_range(addr, addr + size);
501 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
503 /* Read TX BD status */
504 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
505 printf("TX buffers exhausted in mid frame\n");
507 return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE,
511 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
512 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
516 struct zynq_gem_priv *priv = dev_get_priv(dev);
517 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
519 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
522 if (!(current_bd->status &
523 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
524 printf("GEM: SOF or EOF not set for last buffer received!\n");
528 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
530 printf("%s: Zero size packet?\n", __func__);
534 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
535 addr &= ~(ARCH_DMA_MINALIGN - 1);
536 *packetp = (uchar *)(uintptr_t)addr;
541 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
543 struct zynq_gem_priv *priv = dev_get_priv(dev);
544 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
545 struct emac_bd *first_bd;
547 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
548 priv->rx_first_buf = priv->rxbd_current;
550 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
551 current_bd->status = 0xF0000000; /* FIXME */
554 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
555 first_bd = &priv->rx_bd[priv->rx_first_buf];
556 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
557 first_bd->status = 0xF0000000;
560 if ((++priv->rxbd_current) >= RX_BUF)
561 priv->rxbd_current = 0;
566 static void zynq_gem_halt(struct udevice *dev)
568 struct zynq_gem_priv *priv = dev_get_priv(dev);
569 struct zynq_gem_regs *regs = priv->iobase;
571 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
572 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
575 __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
580 static int zynq_gem_read_rom_mac(struct udevice *dev)
583 struct eth_pdata *pdata = dev_get_platdata(dev);
585 retval = zynq_board_read_rom_ethaddr(pdata->enetaddr);
586 if (retval == -ENOSYS)
592 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
595 struct zynq_gem_priv *priv = bus->priv;
599 ret = phyread(priv, addr, reg, &val);
600 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
604 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
607 struct zynq_gem_priv *priv = bus->priv;
609 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
610 return phywrite(priv, addr, reg, value);
613 static int zynq_gem_probe(struct udevice *dev)
616 struct zynq_gem_priv *priv = dev_get_priv(dev);
619 /* Align rxbuffers to ARCH_DMA_MINALIGN */
620 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
621 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
623 /* Align bd_space to MMU_SECTION_SHIFT */
624 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
625 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
626 BD_SPACE, DCACHE_OFF);
628 /* Initialize the bd spaces for tx and rx bd's */
629 priv->tx_bd = (struct emac_bd *)bd_space;
630 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
632 priv->bus = mdio_alloc();
633 priv->bus->read = zynq_gem_miiphy_read;
634 priv->bus->write = zynq_gem_miiphy_write;
635 priv->bus->priv = priv;
637 ret = mdio_register_seq(priv->bus, dev->seq);
641 return zynq_phy_init(dev);
644 static int zynq_gem_remove(struct udevice *dev)
646 struct zynq_gem_priv *priv = dev_get_priv(dev);
649 mdio_unregister(priv->bus);
650 mdio_free(priv->bus);
655 static const struct eth_ops zynq_gem_ops = {
656 .start = zynq_gem_init,
657 .send = zynq_gem_send,
658 .recv = zynq_gem_recv,
659 .free_pkt = zynq_gem_free_pkt,
660 .stop = zynq_gem_halt,
661 .write_hwaddr = zynq_gem_setup_mac,
662 .read_rom_hwaddr = zynq_gem_read_rom_mac,
665 static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
667 struct eth_pdata *pdata = dev_get_platdata(dev);
668 struct zynq_gem_priv *priv = dev_get_priv(dev);
669 const char *phy_mode;
671 pdata->iobase = (phys_addr_t)dev_get_addr(dev);
672 priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
673 /* Hardcode for now */
677 priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob,
678 dev->of_offset, "phy-handle");
679 if (priv->phy_of_handle > 0)
680 priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
681 priv->phy_of_handle, "reg", -1);
683 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
685 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
686 if (pdata->phy_interface == -1) {
687 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
690 priv->interface = pdata->phy_interface;
692 priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio");
694 printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
695 priv->phyaddr, phy_string_for_interface(priv->interface));
700 static const struct udevice_id zynq_gem_ids[] = {
701 { .compatible = "cdns,zynqmp-gem" },
702 { .compatible = "cdns,zynq-gem" },
703 { .compatible = "cdns,gem" },
707 U_BOOT_DRIVER(zynq_gem) = {
710 .of_match = zynq_gem_ids,
711 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
712 .probe = zynq_gem_probe,
713 .remove = zynq_gem_remove,
714 .ops = &zynq_gem_ops,
715 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
716 .platdata_auto_alloc_size = sizeof(struct eth_pdata),