2 * (C) Copyright 2011 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * Based on Xilinx gmac driver:
7 * (C) Copyright 2011 Xilinx
9 * SPDX-License-Identifier: GPL-2.0+
23 #include <asm/arch/hardware.h>
24 #include <asm/arch/sys_proto.h>
26 #if !defined(CONFIG_PHYLIB)
27 # error XILINX_GEM_ETHERNET requires PHYLIB
30 /* Bit/mask specification */
31 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
32 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
33 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
34 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
35 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
37 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
38 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
39 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
41 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
42 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
43 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
45 /* Wrap bit, last descriptor */
46 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
47 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
49 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
50 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
51 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
52 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
54 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
55 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
56 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
57 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
58 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
59 #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
62 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
64 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
67 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
68 ZYNQ_GEM_NWCFG_FDEN | \
69 ZYNQ_GEM_NWCFG_FSREM | \
70 ZYNQ_GEM_NWCFG_MDCCLKDIV)
72 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
74 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
75 /* Use full configured addressable space (8 Kb) */
76 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
77 /* Use full configured addressable space (4 Kb) */
78 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
79 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
80 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
82 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
83 ZYNQ_GEM_DMACR_RXSIZE | \
84 ZYNQ_GEM_DMACR_TXSIZE | \
87 /* Use MII register 1 (MII status register) to detect PHY */
88 #define PHY_DETECT_REG 1
90 /* Mask used to verify certain PHY features (or register contents)
91 * in the register above:
92 * 0x1000: 10Mbps full duplex support
93 * 0x0800: 10Mbps half duplex support
94 * 0x0008: Auto-negotiation support
96 #define PHY_DETECT_MASK 0x1808
98 /* TX BD status masks */
99 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
100 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
101 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
103 /* Clock frequencies for different speeds */
104 #define ZYNQ_GEM_FREQUENCY_10 2500000UL
105 #define ZYNQ_GEM_FREQUENCY_100 25000000UL
106 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
108 /* Device registers */
109 struct zynq_gem_regs {
110 u32 nwctrl; /* Network Control reg */
111 u32 nwcfg; /* Network Config reg */
112 u32 nwsr; /* Network Status reg */
114 u32 dmacr; /* DMA Control reg */
115 u32 txsr; /* TX Status reg */
116 u32 rxqbase; /* RX Q Base address reg */
117 u32 txqbase; /* TX Q Base address reg */
118 u32 rxsr; /* RX Status reg */
120 u32 idr; /* Interrupt Disable reg */
122 u32 phymntnc; /* Phy Maintaince reg */
124 u32 hashl; /* Hash Low address reg */
125 u32 hashh; /* Hash High address reg */
128 u32 laddr[4][LADDR_HIGH + 1]; /* Specific1 addr low/high reg */
129 u32 match[4]; /* Type ID1 Match reg */
131 u32 stat[44]; /* Octects transmitted Low reg - stat start */
136 u32 addr; /* Next descriptor pointer */
141 /* Page table entries are set to 1MB, or multiples of 1MB
142 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
144 #define BD_SPACE 0x100000
145 /* BD separation space */
146 #define BD_SEPRN_SPACE 64
148 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
149 struct zynq_gem_priv {
150 struct emac_bd *tx_bd;
151 struct emac_bd *rx_bd;
158 struct phy_device *phydev;
162 static inline int mdio_wait(struct eth_device *dev)
164 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
167 /* Wait till MDIO interface is ready to accept a new transaction. */
169 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
175 printf("%s: Timeout\n", __func__);
182 static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
186 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
191 /* Construct mgtcr mask for the operation */
192 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
193 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
194 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
196 /* Write mgtcr and wait for completion */
197 writel(mgtcr, ®s->phymntnc);
202 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
203 *data = readl(®s->phymntnc);
208 static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
210 return phy_setup_op(dev, phy_addr, regnum,
211 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
214 static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
216 return phy_setup_op(dev, phy_addr, regnum,
217 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
220 static void phy_detection(struct eth_device *dev)
224 struct zynq_gem_priv *priv = dev->priv;
226 if (priv->phyaddr != -1) {
227 phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
228 if ((phyreg != 0xFFFF) &&
229 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
230 /* Found a valid PHY address */
231 debug("Default phy address %d is valid\n",
235 debug("PHY address is not setup correctly %d\n",
241 debug("detecting phy address\n");
242 if (priv->phyaddr == -1) {
243 /* detect the PHY address */
244 for (i = 31; i >= 0; i--) {
245 phyread(dev, i, PHY_DETECT_REG, &phyreg);
246 if ((phyreg != 0xFFFF) &&
247 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
248 /* Found a valid PHY address */
250 debug("Found valid phy address, %d\n", i);
255 printf("PHY is not detected\n");
258 static int zynq_gem_setup_mac(struct eth_device *dev)
260 u32 i, macaddrlow, macaddrhigh;
261 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
263 /* Set the MAC bits [31:0] in BOT */
264 macaddrlow = dev->enetaddr[0];
265 macaddrlow |= dev->enetaddr[1] << 8;
266 macaddrlow |= dev->enetaddr[2] << 16;
267 macaddrlow |= dev->enetaddr[3] << 24;
269 /* Set MAC bits [47:32] in TOP */
270 macaddrhigh = dev->enetaddr[4];
271 macaddrhigh |= dev->enetaddr[5] << 8;
273 for (i = 0; i < 4; i++) {
274 writel(0, ®s->laddr[i][LADDR_LOW]);
275 writel(0, ®s->laddr[i][LADDR_HIGH]);
276 /* Do not use MATCHx register */
277 writel(0, ®s->match[i]);
280 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
281 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
286 static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
289 unsigned long clk_rate = 0;
290 struct phy_device *phydev;
291 const u32 stat_size = (sizeof(struct zynq_gem_regs) -
292 offsetof(struct zynq_gem_regs, stat)) / 4;
293 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
294 struct zynq_gem_priv *priv = dev->priv;
295 const u32 supported = SUPPORTED_10baseT_Half |
296 SUPPORTED_10baseT_Full |
297 SUPPORTED_100baseT_Half |
298 SUPPORTED_100baseT_Full |
299 SUPPORTED_1000baseT_Half |
300 SUPPORTED_1000baseT_Full;
303 /* Disable all interrupts */
304 writel(0xFFFFFFFF, ®s->idr);
306 /* Disable the receiver & transmitter */
307 writel(0, ®s->nwctrl);
308 writel(0, ®s->txsr);
309 writel(0, ®s->rxsr);
310 writel(0, ®s->phymntnc);
312 /* Clear the Hash registers for the mac address
313 * pointed by AddressPtr
315 writel(0x0, ®s->hashl);
316 /* Write bits [63:32] in TOP */
317 writel(0x0, ®s->hashh);
319 /* Clear all counters */
320 for (i = 0; i <= stat_size; i++)
321 readl(®s->stat[i]);
323 /* Setup RxBD space */
324 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
326 for (i = 0; i < RX_BUF; i++) {
327 priv->rx_bd[i].status = 0xF0000000;
328 priv->rx_bd[i].addr =
329 ((u32)(priv->rxbuffers) +
330 (i * PKTSIZE_ALIGN));
332 /* WRAP bit to last BD */
333 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
334 /* Write RxBDs to IP */
335 writel((u32)priv->rx_bd, ®s->rxqbase);
337 /* Setup for DMA Configuration register */
338 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
340 /* Setup for Network Control register, MDIO, Rx and Tx enable */
341 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
348 /* interface - look at tsec */
349 phydev = phy_connect(priv->bus, priv->phyaddr, dev,
350 PHY_INTERFACE_MODE_MII);
352 phydev->supported = supported | ADVERTISED_Pause |
353 ADVERTISED_Asym_Pause;
354 phydev->advertising = phydev->supported;
355 priv->phydev = phydev;
360 printf("%s: No link.\n", phydev->dev->name);
364 switch (phydev->speed) {
366 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
368 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
371 clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
372 ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
373 clk_rate = ZYNQ_GEM_FREQUENCY_100;
376 clk_rate = ZYNQ_GEM_FREQUENCY_10;
380 /* Change the rclk and clk only not using EMIO interface */
382 zynq_slcr_gem_clk_setup(dev->iobase !=
383 ZYNQ_GEM_BASEADDR0, clk_rate);
385 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
386 ZYNQ_GEM_NWCTRL_TXEN_MASK);
391 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
394 struct zynq_gem_priv *priv = dev->priv;
395 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
398 writel((u32)priv->tx_bd, ®s->txqbase);
401 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
403 priv->tx_bd->addr = (u32)ptr;
404 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
405 ZYNQ_GEM_TXBUF_LAST_MASK;
408 addr &= ~(ARCH_DMA_MINALIGN - 1);
409 size = roundup(len, ARCH_DMA_MINALIGN);
410 flush_dcache_range(addr, addr + size);
414 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
416 /* Read TX BD status */
417 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN)
418 printf("TX underrun\n");
419 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
420 printf("TX buffers exhausted in mid frame\n");
425 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
426 static int zynq_gem_recv(struct eth_device *dev)
429 struct zynq_gem_priv *priv = dev->priv;
430 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
431 struct emac_bd *first_bd;
433 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
436 if (!(current_bd->status &
437 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
438 printf("GEM: SOF or EOF not set for last buffer received!\n");
442 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
444 u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
445 addr &= ~(ARCH_DMA_MINALIGN - 1);
446 u32 size = roundup(frame_len, ARCH_DMA_MINALIGN);
447 invalidate_dcache_range(addr, addr + size);
449 net_process_received_packet((u8 *)addr, frame_len);
451 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
452 priv->rx_first_buf = priv->rxbd_current;
454 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
455 current_bd->status = 0xF0000000; /* FIXME */
458 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
459 first_bd = &priv->rx_bd[priv->rx_first_buf];
460 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
461 first_bd->status = 0xF0000000;
464 if ((++priv->rxbd_current) >= RX_BUF)
465 priv->rxbd_current = 0;
471 static void zynq_gem_halt(struct eth_device *dev)
473 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
475 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
476 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
479 static int zynq_gem_miiphyread(const char *devname, uchar addr,
480 uchar reg, ushort *val)
482 struct eth_device *dev = eth_get_dev();
485 ret = phyread(dev, addr, reg, val);
486 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
490 static int zynq_gem_miiphy_write(const char *devname, uchar addr,
491 uchar reg, ushort val)
493 struct eth_device *dev = eth_get_dev();
495 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
496 return phywrite(dev, addr, reg, val);
499 int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
500 int phy_addr, u32 emio)
502 struct eth_device *dev;
503 struct zynq_gem_priv *priv;
506 dev = calloc(1, sizeof(*dev));
510 dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
511 if (dev->priv == NULL) {
517 /* Align rxbuffers to ARCH_DMA_MINALIGN */
518 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
519 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
521 /* Align bd_space to 1MB */
522 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
523 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
524 BD_SPACE, DCACHE_OFF);
526 /* Initialize the bd spaces for tx and rx bd's */
527 priv->tx_bd = (struct emac_bd *)bd_space;
528 priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE);
530 priv->phyaddr = phy_addr;
533 sprintf(dev->name, "Gem.%lx", base_addr);
535 dev->iobase = base_addr;
537 dev->init = zynq_gem_init;
538 dev->halt = zynq_gem_halt;
539 dev->send = zynq_gem_send;
540 dev->recv = zynq_gem_recv;
541 dev->write_hwaddr = zynq_gem_setup_mac;
545 miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
546 priv->bus = miiphy_get_dev_by_name(dev->name);
551 #ifdef CONFIG_OF_CONTROL
552 int zynq_gem_of_init(const void *blob)
558 debug("ZYNQ GEM: Initialization\n");
561 offset = fdt_node_offset_by_compatible(blob, offset,
562 "xlnx,ps7-ethernet-1.00.a");
564 reg = fdtdec_get_addr(blob, offset, "reg");
565 if (reg != FDT_ADDR_T_NONE) {
566 offset = fdtdec_lookup_phandle(blob, offset,
569 phy_reg = fdtdec_get_addr(blob, offset,
574 debug("ZYNQ GEM: addr %x, phyaddr %x\n",
577 ret |= zynq_gem_initialize(NULL, reg,
581 debug("ZYNQ GEM: Can't get base address\n");
585 } while (offset != -1);