2 * Copyright (C) 2014 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
11 #define BIOS_CTRL 0xd8
13 static int pch7_get_sbase(struct udevice *dev, ulong *sbasep)
17 dm_pci_read_config32(dev, PCH_RCBA, &rcba);
18 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
19 rcba = rcba & 0xffffc000;
20 *sbasep = rcba + 0x3020;
25 static enum pch_version pch7_get_version(struct udevice *dev)
30 static int pch7_set_spi_protect(struct udevice *dev, bool protect)
34 /* Adjust the BIOS write protect to dis/allow write commands */
35 dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
37 bios_cntl &= ~BIOS_CTRL_BIOSWE;
39 bios_cntl |= BIOS_CTRL_BIOSWE;
40 dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
45 static const struct pch_ops pch7_ops = {
46 .get_sbase = pch7_get_sbase,
47 .get_version = pch7_get_version,
48 .set_spi_protect = pch7_set_spi_protect,
51 static const struct udevice_id pch7_ids[] = {
52 { .compatible = "intel,pch7" },
56 U_BOOT_DRIVER(pch7_drv) = {