2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
24 * Initialize controller and call the common driver/pci pci_hose_scan to
25 * scan for bridges and devices.
27 * Hose fields which need to be pre-initialized by board specific code:
36 #include <asm/immap_fsl_pci.h>
38 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
39 pci_dev_t dev, int sub_bus);
40 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
41 pci_dev_t dev, int sub_bus);
43 void pciauto_config_init(struct pci_controller *hose);
45 fsl_pci_init(struct pci_controller *hose)
49 int busno = hose->first_busno;
56 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr;
57 pci_dev_t dev = PCI_BDF(busno,0,0);
59 /* Initialize ATMU registers based on hose regions and flags */
60 volatile pot_t *po = &pci->pot[1]; /* skip 0 */
61 volatile pit_t *pi = &pci->pit[0]; /* ranges from: 3 to 1 */
67 for (r=0; r<hose->region_count; r++) {
68 if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */
69 pi->pitar = (hose->regions[r].bus_start >> 12) & 0x000fffff;
70 pi->piwbar = (hose->regions[r].phys_start >> 12) & 0x000fffff;
72 pi->piwar = PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
73 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP |
74 (__ilog2(hose->regions[r].size) - 1);
76 inbound = hose->regions[r].size > 0;
77 } else { /* Outbound */
78 po->powbar = (hose->regions[r].phys_start >> 12) & 0x000fffff;
79 po->potar = (hose->regions[r].bus_start >> 12) & 0x000fffff;
81 if (hose->regions[r].flags & PCI_REGION_IO)
82 po->powar = POWAR_EN | POWAR_IO_READ | POWAR_IO_WRITE |
83 (__ilog2(hose->regions[r].size) - 1);
85 po->powar = POWAR_EN | POWAR_MEM_READ | POWAR_MEM_WRITE |
86 (__ilog2(hose->regions[r].size) - 1);
91 pci_register_hose(hose);
92 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
93 hose->current_busno = hose->first_busno;
95 pci->pedr = 0xffffffff; /* Clear any errors */
96 pci->peer = ~0x20140; /* Enable All Error Interupts except
97 * - Master abort (pci)
101 pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32);
102 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
103 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
105 pci_hose_read_config_byte (hose, dev, PCI_HEADER_TYPE, &temp8);
106 bridge = temp8 & PCI_HEADER_TYPE_BRIDGE; /* Bridge, such as pcie */
110 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
111 enabled = ltssm >= PCI_LTSSM_L0;
113 #ifdef CONFIG_FSL_PCIE_RESET
116 debug("....PCIe link error. "
117 "LTSSM=0x%02x.", ltssm);
118 pci->pdb_stat |= 0x08000000; /* assert PCIe reset */
119 temp32 = pci->pdb_stat;
121 debug(" Asserting PCIe reset @%x = %x\n",
122 &pci->pdb_stat, pci->pdb_stat);
123 pci->pdb_stat &= ~0x08000000; /* clear reset */
125 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
126 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
129 debug("....PCIe link error. "
130 "LTSSM=0x%02x.\n", ltssm);
132 enabled = ltssm >= PCI_LTSSM_L0;
137 debug("....PCIE link error. Skipping scan."
138 "LTSSM=0x%02x\n", ltssm);
139 hose->last_busno = hose->first_busno;
143 pci->pme_msg_det = 0xffffffff;
144 pci->pme_msg_int_en = 0xffffffff;
146 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
147 neg_link_w = (temp16 & 0x3f0 ) >> 4;
148 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
151 hose->current_busno++; /* Start scan with secondary */
152 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
156 /* Use generic setup_device to initialize standard pci regs,
157 * but do not allocate any windows since any BAR found (such
158 * as PCSRBAR) is not in this cpu's memory space.
161 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
162 hose->pci_prefetch, hose->pci_io);
165 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
166 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
167 temp16 | PCI_COMMAND_MEMORY);
170 #ifndef CONFIG_PCI_NOSCAN
171 printf (" Scanning PCI bus %02x\n", hose->current_busno);
172 hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno);
174 if ( bridge ) { /* update limit regs and subordinate busno */
175 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
178 hose->last_busno = hose->current_busno;
181 /* Clear all error indications */
184 pci->pme_msg_det = 0xffffffff;
185 pci->pedr = 0xffffffff;
187 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
189 pci_hose_write_config_word(hose, dev,
193 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
195 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);