2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 DECLARE_GLOBAL_DATA_PTR;
24 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
26 * Initialize controller and call the common driver/pci pci_hose_scan to
27 * scan for bridges and devices.
29 * Hose fields which need to be pre-initialized by board specific code:
39 #include <asm/fsl_pci.h>
41 /* Freescale-specific PCI config registers */
42 #define FSL_PCI_PBFR 0x44
43 #define FSL_PCIE_CAP_ID 0x4c
44 #define FSL_PCIE_CFG_RDY 0x4b0
46 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
47 pci_dev_t dev, int sub_bus);
48 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
49 pci_dev_t dev, int sub_bus);
50 void pciauto_config_init(struct pci_controller *hose);
52 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
53 #define CONFIG_SYS_PCI_MEMORY_BUS 0
56 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
57 #define CONFIG_SYS_PCI_MEMORY_PHYS 0
60 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
61 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
64 /* Setup one inbound ATMU window.
66 * We let the caller decide what the window size should be
68 static void set_inbound_window(volatile pit_t *pi,
72 u32 sz = (__ilog2_u64(size) - 1);
73 u32 flag = PIWAR_EN | PIWAR_LOCAL |
74 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
76 out_be32(&pi->pitar, r->phys_start >> 12);
77 out_be32(&pi->piwbar, r->bus_start >> 12);
78 #ifdef CONFIG_SYS_PCI_64BIT
79 out_be32(&pi->piwbear, r->bus_start >> 44);
81 out_be32(&pi->piwbear, 0);
83 if (r->flags & PCI_REGION_PREFETCH)
85 out_be32(&pi->piwar, flag | sz);
88 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
89 u64 out_lo, u8 pcie_cap,
92 struct pci_region *r = hose->regions + hose->region_count;
93 u64 sz = min((u64)gd->ram_size, (1ull << 32));
95 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
96 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
99 /* we have no space available for inbound memory mapping */
100 if (bus_start > out_lo) {
101 printf ("no space for inbound mapping of memory\n");
106 if ((bus_start + sz) > out_lo) {
107 sz = out_lo - bus_start;
108 debug ("limiting size to %llx\n", sz);
111 pci_sz = 1ull << __ilog2_u64(sz);
113 * we can overlap inbound/outbound windows on PCI-E since RX & TX
116 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
117 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
118 (u64)bus_start, (u64)phys_start, (u64)sz);
119 pci_set_region(r, bus_start, phys_start, sz,
120 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
121 PCI_REGION_PREFETCH);
123 /* if we aren't an exact power of two match, pci_sz is smaller
124 * round it up to the next power of two. We report the actual
125 * size to pci region tracking.
128 sz = 2ull << __ilog2_u64(sz);
130 set_inbound_window(pi--, r++, sz);
131 sz = 0; /* make sure we dont set the R2 window */
133 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
134 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
135 pci_set_region(r, bus_start, phys_start, pci_sz,
136 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
137 PCI_REGION_PREFETCH);
138 set_inbound_window(pi--, r++, pci_sz);
142 phys_start += pci_sz;
144 pci_sz = 1ull << __ilog2_u64(sz);
146 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
147 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
148 pci_set_region(r, bus_start, phys_start, pci_sz,
149 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
150 PCI_REGION_PREFETCH);
151 set_inbound_window(pi--, r++, pci_sz);
154 phys_start += pci_sz;
158 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
160 * On 64-bit capable systems, set up a mapping for all of DRAM
161 * in high pci address space.
163 pci_sz = 1ull << __ilog2_u64(gd->ram_size);
164 /* round up to the next largest power of two */
165 if (gd->ram_size > pci_sz)
166 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
167 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
168 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
169 (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
172 CONFIG_SYS_PCI64_MEMORY_BUS,
173 CONFIG_SYS_PCI_MEMORY_PHYS,
175 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
176 PCI_REGION_PREFETCH);
177 set_inbound_window(pi--, r++, pci_sz);
179 pci_sz = 1ull << __ilog2_u64(sz);
181 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
182 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
183 pci_set_region(r, bus_start, phys_start, pci_sz,
184 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
185 PCI_REGION_PREFETCH);
188 phys_start += pci_sz;
189 set_inbound_window(pi--, r++, pci_sz);
193 #ifdef CONFIG_PHYS_64BIT
194 if (sz && (((u64)gd->ram_size) < (1ull << 32)))
195 printf("Was not able to map all of memory via "
196 "inbound windows -- %lld remaining\n", sz);
199 hose->region_count = r - hose->regions;
204 void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
208 int enabled, r, inbound = 0;
211 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
212 struct pci_region *reg = hose->regions + hose->region_count;
213 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
215 /* Initialize ATMU registers based on hose regions and flags */
216 volatile pot_t *po = &pci->pot[1]; /* skip 0 */
217 volatile pit_t *pi = &pci->pit[2]; /* ranges from: 3 to 1 */
219 u64 out_hi = 0, out_lo = -1ULL;
220 u32 pcicsrbar, pcicsrbar_sz;
226 pci_setup_indirect(hose, cfg_addr, cfg_data);
228 /* Handle setup of outbound windows first */
229 for (r = 0; r < hose->region_count; r++) {
230 unsigned long flags = hose->regions[r].flags;
231 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
233 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
234 if (flags != PCI_REGION_SYS_MEMORY) {
235 u64 start = hose->regions[r].bus_start;
236 u64 end = start + hose->regions[r].size;
238 out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
239 out_be32(&po->potar, start >> 12);
240 #ifdef CONFIG_SYS_PCI_64BIT
241 out_be32(&po->potear, start >> 44);
243 out_be32(&po->potear, 0);
245 if (hose->regions[r].flags & PCI_REGION_IO) {
246 out_be32(&po->powar, POWAR_EN | sz |
247 POWAR_IO_READ | POWAR_IO_WRITE);
249 out_be32(&po->powar, POWAR_EN | sz |
250 POWAR_MEM_READ | POWAR_MEM_WRITE);
251 out_lo = min(start, out_lo);
252 out_hi = max(end, out_hi);
257 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
259 /* setup PCSRBAR/PEXCSRBAR */
260 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
261 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
262 pcicsrbar_sz = ~pcicsrbar_sz + 1;
264 if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
265 (out_lo > 0x100000000ull))
266 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
268 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
269 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
271 out_lo = min(out_lo, (u64)pcicsrbar);
273 debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
275 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
276 pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
277 hose->region_count++;
279 /* see if we are a PCIe or PCI controller */
280 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
283 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
285 for (r = 0; r < hose->region_count; r++)
286 debug("PCI reg:%d %016llx:%016llx %016llx %08x\n", r,
287 (u64)hose->regions[r].phys_start,
288 hose->regions[r].bus_start,
289 hose->regions[r].size,
290 hose->regions[r].flags);
292 pci_register_hose(hose);
293 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
294 hose->current_busno = hose->first_busno;
296 out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
297 out_be32(&pci->peer, ~0x20140); /* Enable All Error Interupts except
298 * - Master abort (pci)
299 * - Master PERR (pci)
302 pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32);
303 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
304 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
306 if (pcie_cap == PCI_CAP_ID_EXP) {
307 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
308 enabled = ltssm >= PCI_LTSSM_L0;
310 #ifdef CONFIG_FSL_PCIE_RESET
313 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
314 /* assert PCIe reset */
315 setbits_be32(&pci->pdb_stat, 0x08000000);
316 (void) in_be32(&pci->pdb_stat);
318 debug(" Asserting PCIe reset @%x = %x\n",
319 &pci->pdb_stat, in_be32(&pci->pdb_stat));
320 /* clear PCIe reset */
321 clrbits_be32(&pci->pdb_stat, 0x08000000);
323 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
324 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
327 debug("....PCIe link error. "
328 "LTSSM=0x%02x.\n", ltssm);
330 enabled = ltssm >= PCI_LTSSM_L0;
332 /* we need to re-write the bar0 since a reset will
335 pci_hose_write_config_dword(hose, dev,
336 PCI_BASE_ADDRESS_0, pcicsrbar);
341 debug("....PCIE link error. Skipping scan."
342 "LTSSM=0x%02x\n", ltssm);
343 hose->last_busno = hose->first_busno;
347 out_be32(&pci->pme_msg_det, 0xffffffff);
348 out_be32(&pci->pme_msg_int_en, 0xffffffff);
350 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
351 neg_link_w = (temp16 & 0x3f0 ) >> 4;
352 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
355 hose->current_busno++; /* Start scan with secondary */
356 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
359 /* Use generic setup_device to initialize standard pci regs,
360 * but do not allocate any windows since any BAR found (such
361 * as PCSRBAR) is not in this cpu's memory space.
363 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
364 hose->pci_prefetch, hose->pci_io);
367 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
368 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
369 temp16 | PCI_COMMAND_MEMORY);
372 #ifndef CONFIG_PCI_NOSCAN
373 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
375 /* Programming Interface (PCI_CLASS_PROG)
376 * 0 == pci host or pcie root-complex,
377 * 1 == pci agent or pcie end-point
380 printf(" Scanning PCI bus %02x\n",
381 hose->current_busno);
382 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
384 debug(" Not scanning PCI bus %02x. PI=%x\n",
385 hose->current_busno, temp8);
386 hose->last_busno = hose->current_busno;
389 /* if we are PCIe - update limit regs and subordinate busno
390 * for the virtual P2P bridge
392 if (pcie_cap == PCI_CAP_ID_EXP) {
393 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
396 hose->last_busno = hose->current_busno;
399 /* Clear all error indications */
400 if (pcie_cap == PCI_CAP_ID_EXP)
401 out_be32(&pci->pme_msg_det, 0xffffffff);
402 out_be32(&pci->pedr, 0xffffffff);
404 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
406 pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff);
409 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
411 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
415 /* Enable inbound PCI config cycles for agent/endpoint interface */
416 void fsl_pci_config_unlock(struct pci_controller *hose)
418 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
423 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent);
427 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
428 if (pcie_cap != 0x0) {
429 /* PCIe - set CFG_READY bit of Configuration Ready Register */
430 pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
432 /* PCI - clear ACL bit of PBFR */
433 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
435 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
439 #ifdef CONFIG_OF_BOARD_SETUP
441 #include <fdt_support.h>
443 void ft_fsl_pci_setup(void *blob, const char *pci_alias,
444 struct pci_controller *hose)
446 int off = fdt_path_offset(blob, pci_alias);
452 bus_range[1] = hose->last_busno - hose->first_busno;
453 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
454 fdt_pci_dma_ranges(blob, off, hose);