2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <dm/device-internal.h>
17 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
18 #include <asm/fsp/fsp_support.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 static int pci_get_bus(int busnum, struct udevice **busp)
27 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
29 /* Since buses may not be numbered yet try a little harder with bus 0 */
31 ret = uclass_first_device(UCLASS_PCI, busp);
36 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
42 struct pci_controller *pci_bus_to_hose(int busnum)
47 ret = pci_get_bus(busnum, &bus);
49 debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret);
53 return dev_get_uclass_priv(bus);
56 struct udevice *pci_get_controller(struct udevice *dev)
58 while (device_is_on_pci_bus(dev))
64 pci_dev_t dm_pci_get_bdf(struct udevice *dev)
66 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
67 struct udevice *bus = dev->parent;
69 return PCI_ADD_BUS(bus->seq, pplat->devfn);
73 * pci_get_bus_max() - returns the bus number of the last active bus
75 * @return last bus number, or -1 if no active buses
77 static int pci_get_bus_max(void)
83 ret = uclass_get(UCLASS_PCI, &uc);
84 uclass_foreach_dev(bus, uc) {
89 debug("%s: ret=%d\n", __func__, ret);
94 int pci_last_busno(void)
96 return pci_get_bus_max();
99 int pci_get_ff(enum pci_size_t size)
111 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
112 struct udevice **devp)
116 for (device_find_first_child(bus, &dev);
118 device_find_next_child(&dev)) {
119 struct pci_child_platdata *pplat;
121 pplat = dev_get_parent_platdata(dev);
122 if (pplat && pplat->devfn == find_devfn) {
131 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
136 ret = pci_get_bus(PCI_BUS(bdf), &bus);
139 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
142 static int pci_device_matches_ids(struct udevice *dev,
143 struct pci_device_id *ids)
145 struct pci_child_platdata *pplat;
148 pplat = dev_get_parent_platdata(dev);
151 for (i = 0; ids[i].vendor != 0; i++) {
152 if (pplat->vendor == ids[i].vendor &&
153 pplat->device == ids[i].device)
160 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
161 int *indexp, struct udevice **devp)
165 /* Scan all devices on this bus */
166 for (device_find_first_child(bus, &dev);
168 device_find_next_child(&dev)) {
169 if (pci_device_matches_ids(dev, ids) >= 0) {
170 if ((*indexp)-- <= 0) {
180 int pci_find_device_id(struct pci_device_id *ids, int index,
181 struct udevice **devp)
185 /* Scan all known buses */
186 for (uclass_first_device(UCLASS_PCI, &bus);
188 uclass_next_device(&bus)) {
189 if (!pci_bus_find_devices(bus, ids, &index, devp))
197 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
198 unsigned long value, enum pci_size_t size)
200 struct dm_pci_ops *ops;
202 ops = pci_get_ops(bus);
203 if (!ops->write_config)
205 return ops->write_config(bus, bdf, offset, value, size);
208 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
209 enum pci_size_t size)
214 ret = pci_get_bus(PCI_BUS(bdf), &bus);
218 return pci_bus_write_config(bus, bdf, offset, value, size);
221 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
222 enum pci_size_t size)
226 for (bus = dev; device_is_on_pci_bus(bus);)
228 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
233 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
235 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
238 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
240 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
243 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
245 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
248 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
250 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
253 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
255 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
258 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
260 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
263 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
264 unsigned long *valuep, enum pci_size_t size)
266 struct dm_pci_ops *ops;
268 ops = pci_get_ops(bus);
269 if (!ops->read_config)
271 return ops->read_config(bus, bdf, offset, valuep, size);
274 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
275 enum pci_size_t size)
280 ret = pci_get_bus(PCI_BUS(bdf), &bus);
284 return pci_bus_read_config(bus, bdf, offset, valuep, size);
287 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
288 enum pci_size_t size)
292 for (bus = dev; device_is_on_pci_bus(bus);)
294 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
298 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
303 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
311 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
316 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
324 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
329 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
337 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
342 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
350 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
355 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
363 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
368 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
376 static void set_vga_bridge_bits(struct udevice *dev)
378 struct udevice *parent = dev->parent;
381 while (parent->seq != 0) {
382 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
383 bc |= PCI_BRIDGE_CTL_VGA;
384 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
385 parent = parent->parent;
389 int pci_auto_config_devices(struct udevice *bus)
391 struct pci_controller *hose = bus->uclass_priv;
392 struct pci_child_platdata *pplat;
393 unsigned int sub_bus;
398 debug("%s: start\n", __func__);
399 pciauto_config_init(hose);
400 for (ret = device_find_first_child(bus, &dev);
402 ret = device_find_next_child(&dev)) {
403 unsigned int max_bus;
406 debug("%s: device %s\n", __func__, dev->name);
407 ret = pciauto_config_device(hose, dm_pci_get_bdf(dev));
411 sub_bus = max(sub_bus, max_bus);
413 pplat = dev_get_parent_platdata(dev);
414 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
415 set_vga_bridge_bits(dev);
417 debug("%s: done\n", __func__);
422 int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf)
424 struct udevice *parent, *bus;
428 debug("%s\n", __func__);
431 /* Find the bus within the parent */
432 ret = pci_bus_find_devfn(parent, PCI_MASK_BUS(bdf), &bus);
434 debug("%s: Cannot find device %x on bus %s: %d\n", __func__,
435 bdf, parent->name, ret);
439 sub_bus = pci_get_bus_max() + 1;
440 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
441 pciauto_prescan_setup_bridge(hose, bdf, sub_bus);
443 ret = device_probe(bus);
445 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
449 if (sub_bus != bus->seq) {
450 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
451 __func__, bus->name, bus->seq, sub_bus);
454 sub_bus = pci_get_bus_max();
455 pciauto_postscan_setup_bridge(hose, bdf, sub_bus);
461 * pci_match_one_device - Tell if a PCI device structure has a matching
462 * PCI device id structure
463 * @id: single PCI device id structure to match
464 * @dev: the PCI device structure to match against
466 * Returns the matching pci_device_id structure or %NULL if there is no match.
468 static bool pci_match_one_id(const struct pci_device_id *id,
469 const struct pci_device_id *find)
471 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
472 (id->device == PCI_ANY_ID || id->device == find->device) &&
473 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
474 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
475 !((id->class ^ find->class) & id->class_mask))
482 * pci_find_and_bind_driver() - Find and bind the right PCI driver
484 * This only looks at certain fields in the descriptor.
486 * @parent: Parent bus
487 * @find_id: Specification of the driver to find
488 * @bdf: Bus/device/function addreess - see PCI_BDF()
489 * @devp: Returns a pointer to the device created
490 * @return 0 if OK, -EPERM if the device is not needed before relocation and
491 * therefore was not created, other -ve value on error
493 static int pci_find_and_bind_driver(struct udevice *parent,
494 struct pci_device_id *find_id,
495 pci_dev_t bdf, struct udevice **devp)
497 struct pci_driver_entry *start, *entry;
506 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
507 find_id->vendor, find_id->device);
508 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
509 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
510 for (entry = start; entry != start + n_ents; entry++) {
511 const struct pci_device_id *id;
513 const struct driver *drv;
515 for (id = entry->match;
516 id->vendor || id->subvendor || id->class_mask;
518 if (!pci_match_one_id(id, find_id))
524 * In the pre-relocation phase, we only bind devices
525 * whose driver has the DM_FLAG_PRE_RELOC set, to save
526 * precious memory space as on some platforms as that
527 * space is pretty limited (ie: using Cache As RAM).
529 if (!(gd->flags & GD_FLG_RELOC) &&
530 !(drv->flags & DM_FLAG_PRE_RELOC))
534 * We could pass the descriptor to the driver as
535 * platdata (instead of NULL) and allow its bind()
536 * method to return -ENOENT if it doesn't support this
537 * device. That way we could continue the search to
538 * find another driver. For now this doesn't seem
539 * necesssary, so just bind the first match.
541 ret = device_bind(parent, drv, drv->name, NULL, -1,
545 debug("%s: Match found: %s\n", __func__, drv->name);
546 dev->driver_data = find_id->driver_data;
552 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
554 * In the pre-relocation phase, we only bind bridge devices to save
555 * precious memory space as on some platforms as that space is pretty
556 * limited (ie: using Cache As RAM).
558 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
561 /* Bind a generic driver so that the device can be used */
562 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
567 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
569 ret = device_bind_driver(parent, drv, str, devp);
571 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
574 debug("%s: No match found: bound generic driver instead\n", __func__);
579 debug("%s: No match found: error %d\n", __func__, ret);
583 int pci_bind_bus_devices(struct udevice *bus)
585 ulong vendor, device;
592 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
593 PCI_MAX_PCI_FUNCTIONS - 1);
594 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end;
595 bdf += PCI_BDF(0, 0, 1)) {
596 struct pci_child_platdata *pplat;
600 if (PCI_FUNC(bdf) && !found_multi)
602 /* Check only the first access, we don't expect problems */
603 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
604 &header_type, PCI_SIZE_8);
607 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
609 if (vendor == 0xffff || vendor == 0x0000)
613 found_multi = header_type & 0x80;
615 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
616 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
617 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
619 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
623 /* Find this device in the device tree */
624 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
626 /* Search for a driver */
628 /* If nothing in the device tree, bind a generic device */
629 if (ret == -ENODEV) {
630 struct pci_device_id find_id;
633 memset(&find_id, '\0', sizeof(find_id));
634 find_id.vendor = vendor;
635 find_id.device = device;
636 find_id.class = class;
637 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
638 pci_bus_read_config(bus, bdf,
639 PCI_SUBSYSTEM_VENDOR_ID,
641 find_id.subvendor = val & 0xffff;
642 find_id.subdevice = val >> 16;
644 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
652 /* Update the platform data */
653 pplat = dev_get_parent_platdata(dev);
654 pplat->devfn = PCI_MASK_BUS(bdf);
655 pplat->vendor = vendor;
656 pplat->device = device;
657 pplat->class = class;
662 printf("Cannot read bus configuration: %d\n", ret);
667 static int pci_uclass_post_bind(struct udevice *bus)
670 * If there is no pci device listed in the device tree,
671 * don't bother scanning the device tree.
673 if (bus->of_offset == -1)
677 * Scan the device tree for devices. This does not probe the PCI bus,
678 * as this is not permitted while binding. It just finds devices
679 * mentioned in the device tree.
681 * Before relocation, only bind devices marked for pre-relocation
684 return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
685 gd->flags & GD_FLG_RELOC ? false : true);
688 static int decode_regions(struct pci_controller *hose, const void *blob,
689 int parent_node, int node)
691 int pci_addr_cells, addr_cells, size_cells;
692 phys_addr_t base = 0, size;
693 int cells_per_record;
698 prop = fdt_getprop(blob, node, "ranges", &len);
701 pci_addr_cells = fdt_address_cells(blob, node);
702 addr_cells = fdt_address_cells(blob, parent_node);
703 size_cells = fdt_size_cells(blob, node);
705 /* PCI addresses are always 3-cells */
707 cells_per_record = pci_addr_cells + addr_cells + size_cells;
708 hose->region_count = 0;
709 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
711 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
712 u64 pci_addr, addr, size;
718 if (len < cells_per_record)
720 flags = fdt32_to_cpu(prop[0]);
721 space_code = (flags >> 24) & 3;
722 pci_addr = fdtdec_get_number(prop + 1, 2);
723 prop += pci_addr_cells;
724 addr = fdtdec_get_number(prop, addr_cells);
726 size = fdtdec_get_number(prop, size_cells);
728 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
729 ", size=%" PRIx64 ", space_code=%d\n", __func__,
730 hose->region_count, pci_addr, addr, size, space_code);
731 if (space_code & 2) {
732 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
734 } else if (space_code & 1) {
735 type = PCI_REGION_IO;
740 for (i = 0; i < hose->region_count; i++) {
741 if (hose->regions[i].flags == type)
745 pos = hose->region_count++;
746 debug(" - type=%d, pos=%d\n", type, pos);
747 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
750 /* Add a region for our local memory */
752 #ifdef CONFIG_SYS_SDRAM_BASE
753 base = CONFIG_SYS_SDRAM_BASE;
755 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
756 size = gd->pci_ram_top - base;
757 pci_set_region(hose->regions + hose->region_count++, base, base,
758 size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
763 static int pci_uclass_pre_probe(struct udevice *bus)
765 struct pci_controller *hose;
768 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
770 hose = bus->uclass_priv;
772 /* For bridges, use the top-level PCI controller */
773 if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
775 ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
778 debug("%s: Cannot decode regions\n", __func__);
782 struct pci_controller *parent_hose;
784 parent_hose = dev_get_uclass_priv(bus->parent);
785 hose->ctlr = parent_hose->bus;
788 hose->first_busno = bus->seq;
789 hose->last_busno = bus->seq;
794 static int pci_uclass_post_probe(struct udevice *bus)
798 debug("%s: probing bus %d\n", __func__, bus->seq);
799 ret = pci_bind_bus_devices(bus);
803 #ifdef CONFIG_PCI_PNP
804 ret = pci_auto_config_devices(bus);
809 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
811 * Per Intel FSP specification, we should call FSP notify API to
812 * inform FSP that PCI enumeration has been done so that FSP will
813 * do any necessary initialization as required by the chipset's
814 * BIOS Writer's Guide (BWG).
816 * Unfortunately we have to put this call here as with driver model,
817 * the enumeration is all done on a lazy basis as needed, so until
818 * something is touched on PCI it won't happen.
820 * Note we only call this 1) after U-Boot is relocated, and 2)
821 * root bus has finished probing.
823 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
824 ret = fsp_init_phase_pci();
833 static int pci_uclass_child_post_bind(struct udevice *dev)
835 struct pci_child_platdata *pplat;
836 struct fdt_pci_addr addr;
839 if (dev->of_offset == -1)
843 * We could read vendor, device, class if available. But for now we
844 * just check the address.
846 pplat = dev_get_parent_platdata(dev);
847 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
848 FDT_PCI_SPACE_CONFIG, "reg", &addr);
854 /* extract the devfn from fdt_pci_addr */
855 pplat->devfn = addr.phys_hi & 0xff00;
861 static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
862 uint offset, ulong *valuep,
863 enum pci_size_t size)
865 struct pci_controller *hose = bus->uclass_priv;
867 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
870 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
871 uint offset, ulong value,
872 enum pci_size_t size)
874 struct pci_controller *hose = bus->uclass_priv;
876 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
879 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
885 * Scan through all the PCI controllers. On x86 there will only be one
886 * but that is not necessarily true on other hardware.
889 device_find_first_child(bus, &dev);
894 ret = uclass_next_device(&bus);
902 int pci_find_next_device(struct udevice **devp)
904 struct udevice *child = *devp;
905 struct udevice *bus = child->parent;
908 /* First try all the siblings */
911 device_find_next_child(&child);
918 /* We ran out of siblings. Try the next bus */
919 ret = uclass_next_device(&bus);
923 return bus ? skip_to_next_device(bus, devp) : 0;
926 int pci_find_first_device(struct udevice **devp)
932 ret = uclass_first_device(UCLASS_PCI, &bus);
936 return skip_to_next_device(bus, devp);
939 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
943 return (value >> ((offset & 3) * 8)) & 0xff;
945 return (value >> ((offset & 2) * 8)) & 0xffff;
951 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
952 enum pci_size_t size)
955 uint val_mask, shift;
970 shift = (offset & off_mask) * 8;
971 ldata = (value & val_mask) << shift;
972 mask = val_mask << shift;
973 value = (old & ~mask) | ldata;
978 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
979 struct pci_region **memp, struct pci_region **prefp)
981 struct udevice *bus = pci_get_controller(dev);
982 struct pci_controller *hose = dev_get_uclass_priv(bus);
988 for (i = 0; i < hose->region_count; i++) {
989 switch (hose->regions[i].flags) {
991 if (!*iop || (*iop)->size < hose->regions[i].size)
992 *iop = hose->regions + i;
995 if (!*memp || (*memp)->size < hose->regions[i].size)
996 *memp = hose->regions + i;
998 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
999 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1000 *prefp = hose->regions + i;
1005 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1008 UCLASS_DRIVER(pci) = {
1011 .flags = DM_UC_FLAG_SEQ_ALIAS,
1012 .post_bind = pci_uclass_post_bind,
1013 .pre_probe = pci_uclass_pre_probe,
1014 .post_probe = pci_uclass_post_probe,
1015 .child_post_bind = pci_uclass_child_post_bind,
1016 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1017 .per_child_platdata_auto_alloc_size =
1018 sizeof(struct pci_child_platdata),
1021 static const struct dm_pci_ops pci_bridge_ops = {
1022 .read_config = pci_bridge_read_config,
1023 .write_config = pci_bridge_write_config,
1026 static const struct udevice_id pci_bridge_ids[] = {
1027 { .compatible = "pci-bridge" },
1031 U_BOOT_DRIVER(pci_bridge_drv) = {
1032 .name = "pci_bridge_drv",
1034 .of_match = pci_bridge_ids,
1035 .ops = &pci_bridge_ops,
1038 UCLASS_DRIVER(pci_generic) = {
1039 .id = UCLASS_PCI_GENERIC,
1040 .name = "pci_generic",
1043 static const struct udevice_id pci_generic_ids[] = {
1044 { .compatible = "pci-generic" },
1048 U_BOOT_DRIVER(pci_generic_drv) = {
1049 .name = "pci_generic_drv",
1050 .id = UCLASS_PCI_GENERIC,
1051 .of_match = pci_generic_ids,