2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <dm/device-internal.h>
17 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
18 #include <asm/fsp/fsp_support.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 static int pci_get_bus(int busnum, struct udevice **busp)
27 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
29 /* Since buses may not be numbered yet try a little harder with bus 0 */
31 ret = uclass_first_device(UCLASS_PCI, busp);
36 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
42 struct pci_controller *pci_bus_to_hose(int busnum)
47 ret = pci_get_bus(busnum, &bus);
49 debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret);
53 return dev_get_uclass_priv(bus);
56 pci_dev_t pci_get_bdf(struct udevice *dev)
58 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
59 struct udevice *bus = dev->parent;
61 return PCI_ADD_BUS(bus->seq, pplat->devfn);
65 * pci_get_bus_max() - returns the bus number of the last active bus
67 * @return last bus number, or -1 if no active buses
69 static int pci_get_bus_max(void)
75 ret = uclass_get(UCLASS_PCI, &uc);
76 uclass_foreach_dev(bus, uc) {
81 debug("%s: ret=%d\n", __func__, ret);
86 int pci_last_busno(void)
88 struct pci_controller *hose;
93 debug("pci_last_busno\n");
94 ret = uclass_get(UCLASS_PCI, &uc);
95 if (ret || list_empty(&uc->dev_head))
98 /* Probe the last bus */
99 bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node);
100 debug("bus = %p, %s\n", bus, bus->name);
102 ret = device_probe(bus);
106 /* If that bus has bridges, we may have new buses now. Get the last */
107 bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node);
108 hose = dev_get_uclass_priv(bus);
109 debug("bus = %s, hose = %p\n", bus->name, hose);
111 return hose->last_busno;
114 int pci_get_ff(enum pci_size_t size)
126 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
127 struct udevice **devp)
131 for (device_find_first_child(bus, &dev);
133 device_find_next_child(&dev)) {
134 struct pci_child_platdata *pplat;
136 pplat = dev_get_parent_platdata(dev);
137 if (pplat && pplat->devfn == find_devfn) {
146 int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
151 ret = pci_get_bus(PCI_BUS(bdf), &bus);
154 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
157 static int pci_device_matches_ids(struct udevice *dev,
158 struct pci_device_id *ids)
160 struct pci_child_platdata *pplat;
163 pplat = dev_get_parent_platdata(dev);
166 for (i = 0; ids[i].vendor != 0; i++) {
167 if (pplat->vendor == ids[i].vendor &&
168 pplat->device == ids[i].device)
175 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
176 int *indexp, struct udevice **devp)
180 /* Scan all devices on this bus */
181 for (device_find_first_child(bus, &dev);
183 device_find_next_child(&dev)) {
184 if (pci_device_matches_ids(dev, ids) >= 0) {
185 if ((*indexp)-- <= 0) {
195 int pci_find_device_id(struct pci_device_id *ids, int index,
196 struct udevice **devp)
200 /* Scan all known buses */
201 for (uclass_first_device(UCLASS_PCI, &bus);
203 uclass_next_device(&bus)) {
204 if (!pci_bus_find_devices(bus, ids, &index, devp))
212 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
213 unsigned long value, enum pci_size_t size)
215 struct dm_pci_ops *ops;
217 ops = pci_get_ops(bus);
218 if (!ops->write_config)
220 return ops->write_config(bus, bdf, offset, value, size);
223 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
224 enum pci_size_t size)
229 ret = pci_get_bus(PCI_BUS(bdf), &bus);
233 return pci_bus_write_config(bus, bdf, offset, value, size);
236 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
237 enum pci_size_t size)
241 for (bus = dev; device_is_on_pci_bus(bus);)
243 return pci_bus_write_config(bus, pci_get_bdf(dev), offset, value, size);
247 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
249 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
252 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
254 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
257 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
259 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
262 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
264 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
267 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
269 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
272 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
274 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
277 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
278 unsigned long *valuep, enum pci_size_t size)
280 struct dm_pci_ops *ops;
282 ops = pci_get_ops(bus);
283 if (!ops->read_config)
285 return ops->read_config(bus, bdf, offset, valuep, size);
288 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
289 enum pci_size_t size)
294 ret = pci_get_bus(PCI_BUS(bdf), &bus);
298 return pci_bus_read_config(bus, bdf, offset, valuep, size);
301 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
302 enum pci_size_t size)
306 for (bus = dev; device_is_on_pci_bus(bus);)
308 return pci_bus_read_config(bus, pci_get_bdf(dev), offset, valuep,
312 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
317 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
325 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
330 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
338 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
343 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
351 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
356 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
364 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
369 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
377 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
382 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
390 int pci_auto_config_devices(struct udevice *bus)
392 struct pci_controller *hose = bus->uclass_priv;
393 unsigned int sub_bus;
398 debug("%s: start\n", __func__);
399 pciauto_config_init(hose);
400 for (ret = device_find_first_child(bus, &dev);
402 ret = device_find_next_child(&dev)) {
403 unsigned int max_bus;
406 debug("%s: device %s\n", __func__, dev->name);
407 ret = pciauto_config_device(hose, pci_get_bdf(dev));
411 sub_bus = max(sub_bus, max_bus);
413 debug("%s: done\n", __func__);
418 int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf)
420 struct udevice *parent, *bus;
424 debug("%s\n", __func__);
427 /* Find the bus within the parent */
428 ret = pci_bus_find_devfn(parent, PCI_MASK_BUS(bdf), &bus);
430 debug("%s: Cannot find device %x on bus %s: %d\n", __func__,
431 bdf, parent->name, ret);
435 sub_bus = pci_get_bus_max() + 1;
436 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
437 pciauto_prescan_setup_bridge(hose, bdf, sub_bus);
439 ret = device_probe(bus);
441 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
445 if (sub_bus != bus->seq) {
446 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
447 __func__, bus->name, bus->seq, sub_bus);
450 sub_bus = pci_get_bus_max();
451 pciauto_postscan_setup_bridge(hose, bdf, sub_bus);
457 * pci_match_one_device - Tell if a PCI device structure has a matching
458 * PCI device id structure
459 * @id: single PCI device id structure to match
460 * @dev: the PCI device structure to match against
462 * Returns the matching pci_device_id structure or %NULL if there is no match.
464 static bool pci_match_one_id(const struct pci_device_id *id,
465 const struct pci_device_id *find)
467 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
468 (id->device == PCI_ANY_ID || id->device == find->device) &&
469 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
470 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
471 !((id->class ^ find->class) & id->class_mask))
478 * pci_find_and_bind_driver() - Find and bind the right PCI driver
480 * This only looks at certain fields in the descriptor.
482 * @parent: Parent bus
483 * @find_id: Specification of the driver to find
484 * @bdf: Bus/device/function addreess - see PCI_BDF()
485 * @devp: Returns a pointer to the device created
486 * @return 0 if OK, -EPERM if the device is not needed before relocation and
487 * therefore was not created, other -ve value on error
489 static int pci_find_and_bind_driver(struct udevice *parent,
490 struct pci_device_id *find_id,
491 pci_dev_t bdf, struct udevice **devp)
493 struct pci_driver_entry *start, *entry;
502 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
503 find_id->vendor, find_id->device);
504 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
505 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
506 for (entry = start; entry != start + n_ents; entry++) {
507 const struct pci_device_id *id;
509 const struct driver *drv;
511 for (id = entry->match;
512 id->vendor || id->subvendor || id->class_mask;
514 if (!pci_match_one_id(id, find_id))
520 * In the pre-relocation phase, we only bind devices
521 * whose driver has the DM_FLAG_PRE_RELOC set, to save
522 * precious memory space as on some platforms as that
523 * space is pretty limited (ie: using Cache As RAM).
525 if (!(gd->flags & GD_FLG_RELOC) &&
526 !(drv->flags & DM_FLAG_PRE_RELOC))
530 * We could pass the descriptor to the driver as
531 * platdata (instead of NULL) and allow its bind()
532 * method to return -ENOENT if it doesn't support this
533 * device. That way we could continue the search to
534 * find another driver. For now this doesn't seem
535 * necesssary, so just bind the first match.
537 ret = device_bind(parent, drv, drv->name, NULL, -1,
541 debug("%s: Match found: %s\n", __func__, drv->name);
542 dev->driver_data = find_id->driver_data;
548 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
550 * In the pre-relocation phase, we only bind bridge devices to save
551 * precious memory space as on some platforms as that space is pretty
552 * limited (ie: using Cache As RAM).
554 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
557 /* Bind a generic driver so that the device can be used */
558 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
563 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
565 ret = device_bind_driver(parent, drv, str, devp);
567 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
570 debug("%s: No match found: bound generic driver instead\n", __func__);
575 debug("%s: No match found: error %d\n", __func__, ret);
579 int pci_bind_bus_devices(struct udevice *bus)
581 ulong vendor, device;
588 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
589 PCI_MAX_PCI_FUNCTIONS - 1);
590 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end;
591 bdf += PCI_BDF(0, 0, 1)) {
592 struct pci_child_platdata *pplat;
596 if (PCI_FUNC(bdf) && !found_multi)
598 /* Check only the first access, we don't expect problems */
599 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
600 &header_type, PCI_SIZE_8);
603 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
605 if (vendor == 0xffff || vendor == 0x0000)
609 found_multi = header_type & 0x80;
611 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
612 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
613 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
615 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
619 /* Find this device in the device tree */
620 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
622 /* Search for a driver */
624 /* If nothing in the device tree, bind a generic device */
625 if (ret == -ENODEV) {
626 struct pci_device_id find_id;
629 memset(&find_id, '\0', sizeof(find_id));
630 find_id.vendor = vendor;
631 find_id.device = device;
632 find_id.class = class;
633 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
634 pci_bus_read_config(bus, bdf,
635 PCI_SUBSYSTEM_VENDOR_ID,
637 find_id.subvendor = val & 0xffff;
638 find_id.subdevice = val >> 16;
640 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
648 /* Update the platform data */
649 pplat = dev_get_parent_platdata(dev);
650 pplat->devfn = PCI_MASK_BUS(bdf);
651 pplat->vendor = vendor;
652 pplat->device = device;
653 pplat->class = class;
658 printf("Cannot read bus configuration: %d\n", ret);
663 static int pci_uclass_post_bind(struct udevice *bus)
666 * If there is no pci device listed in the device tree,
667 * don't bother scanning the device tree.
669 if (bus->of_offset == -1)
673 * Scan the device tree for devices. This does not probe the PCI bus,
674 * as this is not permitted while binding. It just finds devices
675 * mentioned in the device tree.
677 * Before relocation, only bind devices marked for pre-relocation
680 return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
681 gd->flags & GD_FLG_RELOC ? false : true);
684 static int decode_regions(struct pci_controller *hose, const void *blob,
685 int parent_node, int node)
687 int pci_addr_cells, addr_cells, size_cells;
688 int cells_per_record;
694 prop = fdt_getprop(blob, node, "ranges", &len);
697 pci_addr_cells = fdt_address_cells(blob, node);
698 addr_cells = fdt_address_cells(blob, parent_node);
699 size_cells = fdt_size_cells(blob, node);
701 /* PCI addresses are always 3-cells */
703 cells_per_record = pci_addr_cells + addr_cells + size_cells;
704 hose->region_count = 0;
705 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
707 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
708 u64 pci_addr, addr, size;
713 if (len < cells_per_record)
715 flags = fdt32_to_cpu(prop[0]);
716 space_code = (flags >> 24) & 3;
717 pci_addr = fdtdec_get_number(prop + 1, 2);
718 prop += pci_addr_cells;
719 addr = fdtdec_get_number(prop, addr_cells);
721 size = fdtdec_get_number(prop, size_cells);
723 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
724 ", size=%" PRIx64 ", space_code=%d\n", __func__,
725 hose->region_count, pci_addr, addr, size, space_code);
726 if (space_code & 2) {
727 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
729 } else if (space_code & 1) {
730 type = PCI_REGION_IO;
734 debug(" - type=%d\n", type);
735 pci_set_region(hose->regions + hose->region_count++, pci_addr,
739 /* Add a region for our local memory */
741 if (gd->pci_ram_top && gd->pci_ram_top < addr)
742 addr = gd->pci_ram_top;
743 pci_set_region(hose->regions + hose->region_count++, 0, 0, addr,
744 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
749 static int pci_uclass_pre_probe(struct udevice *bus)
751 struct pci_controller *hose;
754 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
756 hose = bus->uclass_priv;
758 /* For bridges, use the top-level PCI controller */
759 if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
761 ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
764 debug("%s: Cannot decode regions\n", __func__);
768 struct pci_controller *parent_hose;
770 parent_hose = dev_get_uclass_priv(bus->parent);
771 hose->ctlr = parent_hose->bus;
774 hose->first_busno = bus->seq;
775 hose->last_busno = bus->seq;
780 static int pci_uclass_post_probe(struct udevice *bus)
784 debug("%s: probing bus %d\n", __func__, bus->seq);
785 ret = pci_bind_bus_devices(bus);
789 #ifdef CONFIG_PCI_PNP
790 ret = pci_auto_config_devices(bus);
795 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
797 * Per Intel FSP specification, we should call FSP notify API to
798 * inform FSP that PCI enumeration has been done so that FSP will
799 * do any necessary initialization as required by the chipset's
800 * BIOS Writer's Guide (BWG).
802 * Unfortunately we have to put this call here as with driver model,
803 * the enumeration is all done on a lazy basis as needed, so until
804 * something is touched on PCI it won't happen.
806 * Note we only call this 1) after U-Boot is relocated, and 2)
807 * root bus has finished probing.
809 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
810 ret = fsp_init_phase_pci();
819 static int pci_uclass_child_post_bind(struct udevice *dev)
821 struct pci_child_platdata *pplat;
822 struct fdt_pci_addr addr;
825 if (dev->of_offset == -1)
829 * We could read vendor, device, class if available. But for now we
830 * just check the address.
832 pplat = dev_get_parent_platdata(dev);
833 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
834 FDT_PCI_SPACE_CONFIG, "reg", &addr);
840 /* extract the devfn from fdt_pci_addr */
841 pplat->devfn = addr.phys_hi & 0xff00;
847 static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
848 uint offset, ulong *valuep,
849 enum pci_size_t size)
851 struct pci_controller *hose = bus->uclass_priv;
853 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
856 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
857 uint offset, ulong value,
858 enum pci_size_t size)
860 struct pci_controller *hose = bus->uclass_priv;
862 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
865 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
871 * Scan through all the PCI controllers. On x86 there will only be one
872 * but that is not necessarily true on other hardware.
875 device_find_first_child(bus, &dev);
880 ret = uclass_next_device(&bus);
888 int pci_find_next_device(struct udevice **devp)
890 struct udevice *child = *devp;
891 struct udevice *bus = child->parent;
894 /* First try all the siblings */
897 device_find_next_child(&child);
904 /* We ran out of siblings. Try the next bus */
905 ret = uclass_next_device(&bus);
909 return bus ? skip_to_next_device(bus, devp) : 0;
912 int pci_find_first_device(struct udevice **devp)
918 ret = uclass_first_device(UCLASS_PCI, &bus);
922 return skip_to_next_device(bus, devp);
925 UCLASS_DRIVER(pci) = {
928 .flags = DM_UC_FLAG_SEQ_ALIAS,
929 .post_bind = pci_uclass_post_bind,
930 .pre_probe = pci_uclass_pre_probe,
931 .post_probe = pci_uclass_post_probe,
932 .child_post_bind = pci_uclass_child_post_bind,
933 .per_device_auto_alloc_size = sizeof(struct pci_controller),
934 .per_child_platdata_auto_alloc_size =
935 sizeof(struct pci_child_platdata),
938 static const struct dm_pci_ops pci_bridge_ops = {
939 .read_config = pci_bridge_read_config,
940 .write_config = pci_bridge_write_config,
943 static const struct udevice_id pci_bridge_ids[] = {
944 { .compatible = "pci-bridge" },
948 U_BOOT_DRIVER(pci_bridge_drv) = {
949 .name = "pci_bridge_drv",
951 .of_match = pci_bridge_ids,
952 .ops = &pci_bridge_ops,
955 UCLASS_DRIVER(pci_generic) = {
956 .id = UCLASS_PCI_GENERIC,
957 .name = "pci_generic",
960 static const struct udevice_id pci_generic_ids[] = {
961 { .compatible = "pci-generic" },
965 U_BOOT_DRIVER(pci_generic_drv) = {
966 .name = "pci_generic_drv",
967 .id = UCLASS_PCI_GENERIC,
968 .of_match = pci_generic_ids,