2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <dm/device-internal.h>
17 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
18 #include <asm/fsp/fsp_support.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 static int pci_get_bus(int busnum, struct udevice **busp)
27 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
29 /* Since buses may not be numbered yet try a little harder with bus 0 */
31 ret = uclass_first_device(UCLASS_PCI, busp);
36 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
42 struct pci_controller *pci_bus_to_hose(int busnum)
47 ret = pci_get_bus(busnum, &bus);
49 debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret);
53 return dev_get_uclass_priv(bus);
56 struct udevice *pci_get_controller(struct udevice *dev)
58 while (device_is_on_pci_bus(dev))
64 pci_dev_t pci_get_bdf(struct udevice *dev)
66 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
67 struct udevice *bus = dev->parent;
69 return PCI_ADD_BUS(bus->seq, pplat->devfn);
73 * pci_get_bus_max() - returns the bus number of the last active bus
75 * @return last bus number, or -1 if no active buses
77 static int pci_get_bus_max(void)
83 ret = uclass_get(UCLASS_PCI, &uc);
84 uclass_foreach_dev(bus, uc) {
89 debug("%s: ret=%d\n", __func__, ret);
94 int pci_last_busno(void)
96 return pci_get_bus_max();
99 int pci_get_ff(enum pci_size_t size)
111 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
112 struct udevice **devp)
116 for (device_find_first_child(bus, &dev);
118 device_find_next_child(&dev)) {
119 struct pci_child_platdata *pplat;
121 pplat = dev_get_parent_platdata(dev);
122 if (pplat && pplat->devfn == find_devfn) {
131 int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
136 ret = pci_get_bus(PCI_BUS(bdf), &bus);
139 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
142 static int pci_device_matches_ids(struct udevice *dev,
143 struct pci_device_id *ids)
145 struct pci_child_platdata *pplat;
148 pplat = dev_get_parent_platdata(dev);
151 for (i = 0; ids[i].vendor != 0; i++) {
152 if (pplat->vendor == ids[i].vendor &&
153 pplat->device == ids[i].device)
160 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
161 int *indexp, struct udevice **devp)
165 /* Scan all devices on this bus */
166 for (device_find_first_child(bus, &dev);
168 device_find_next_child(&dev)) {
169 if (pci_device_matches_ids(dev, ids) >= 0) {
170 if ((*indexp)-- <= 0) {
180 int pci_find_device_id(struct pci_device_id *ids, int index,
181 struct udevice **devp)
185 /* Scan all known buses */
186 for (uclass_first_device(UCLASS_PCI, &bus);
188 uclass_next_device(&bus)) {
189 if (!pci_bus_find_devices(bus, ids, &index, devp))
197 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
198 unsigned long value, enum pci_size_t size)
200 struct dm_pci_ops *ops;
202 ops = pci_get_ops(bus);
203 if (!ops->write_config)
205 return ops->write_config(bus, bdf, offset, value, size);
208 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
209 enum pci_size_t size)
214 ret = pci_get_bus(PCI_BUS(bdf), &bus);
218 return pci_bus_write_config(bus, bdf, offset, value, size);
221 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
222 enum pci_size_t size)
226 for (bus = dev; device_is_on_pci_bus(bus);)
228 return pci_bus_write_config(bus, pci_get_bdf(dev), offset, value, size);
232 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
234 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
237 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
239 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
242 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
244 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
247 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
249 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
252 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
254 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
257 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
259 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
262 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
263 unsigned long *valuep, enum pci_size_t size)
265 struct dm_pci_ops *ops;
267 ops = pci_get_ops(bus);
268 if (!ops->read_config)
270 return ops->read_config(bus, bdf, offset, valuep, size);
273 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
274 enum pci_size_t size)
279 ret = pci_get_bus(PCI_BUS(bdf), &bus);
283 return pci_bus_read_config(bus, bdf, offset, valuep, size);
286 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
287 enum pci_size_t size)
291 for (bus = dev; device_is_on_pci_bus(bus);)
293 return pci_bus_read_config(bus, pci_get_bdf(dev), offset, valuep,
297 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
302 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
310 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
315 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
323 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
328 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
336 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
341 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
349 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
354 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
362 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
367 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
375 static void set_vga_bridge_bits(struct udevice *dev)
377 struct udevice *parent = dev->parent;
380 while (parent->seq != 0) {
381 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
382 bc |= PCI_BRIDGE_CTL_VGA;
383 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
384 parent = parent->parent;
388 int pci_auto_config_devices(struct udevice *bus)
390 struct pci_controller *hose = bus->uclass_priv;
391 struct pci_child_platdata *pplat;
392 unsigned int sub_bus;
397 debug("%s: start\n", __func__);
398 pciauto_config_init(hose);
399 for (ret = device_find_first_child(bus, &dev);
401 ret = device_find_next_child(&dev)) {
402 unsigned int max_bus;
405 debug("%s: device %s\n", __func__, dev->name);
406 ret = pciauto_config_device(hose, pci_get_bdf(dev));
410 sub_bus = max(sub_bus, max_bus);
412 pplat = dev_get_parent_platdata(dev);
413 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
414 set_vga_bridge_bits(dev);
416 debug("%s: done\n", __func__);
421 int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf)
423 struct udevice *parent, *bus;
427 debug("%s\n", __func__);
430 /* Find the bus within the parent */
431 ret = pci_bus_find_devfn(parent, PCI_MASK_BUS(bdf), &bus);
433 debug("%s: Cannot find device %x on bus %s: %d\n", __func__,
434 bdf, parent->name, ret);
438 sub_bus = pci_get_bus_max() + 1;
439 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
440 pciauto_prescan_setup_bridge(hose, bdf, sub_bus);
442 ret = device_probe(bus);
444 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
448 if (sub_bus != bus->seq) {
449 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
450 __func__, bus->name, bus->seq, sub_bus);
453 sub_bus = pci_get_bus_max();
454 pciauto_postscan_setup_bridge(hose, bdf, sub_bus);
460 * pci_match_one_device - Tell if a PCI device structure has a matching
461 * PCI device id structure
462 * @id: single PCI device id structure to match
463 * @dev: the PCI device structure to match against
465 * Returns the matching pci_device_id structure or %NULL if there is no match.
467 static bool pci_match_one_id(const struct pci_device_id *id,
468 const struct pci_device_id *find)
470 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
471 (id->device == PCI_ANY_ID || id->device == find->device) &&
472 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
473 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
474 !((id->class ^ find->class) & id->class_mask))
481 * pci_find_and_bind_driver() - Find and bind the right PCI driver
483 * This only looks at certain fields in the descriptor.
485 * @parent: Parent bus
486 * @find_id: Specification of the driver to find
487 * @bdf: Bus/device/function addreess - see PCI_BDF()
488 * @devp: Returns a pointer to the device created
489 * @return 0 if OK, -EPERM if the device is not needed before relocation and
490 * therefore was not created, other -ve value on error
492 static int pci_find_and_bind_driver(struct udevice *parent,
493 struct pci_device_id *find_id,
494 pci_dev_t bdf, struct udevice **devp)
496 struct pci_driver_entry *start, *entry;
505 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
506 find_id->vendor, find_id->device);
507 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
508 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
509 for (entry = start; entry != start + n_ents; entry++) {
510 const struct pci_device_id *id;
512 const struct driver *drv;
514 for (id = entry->match;
515 id->vendor || id->subvendor || id->class_mask;
517 if (!pci_match_one_id(id, find_id))
523 * In the pre-relocation phase, we only bind devices
524 * whose driver has the DM_FLAG_PRE_RELOC set, to save
525 * precious memory space as on some platforms as that
526 * space is pretty limited (ie: using Cache As RAM).
528 if (!(gd->flags & GD_FLG_RELOC) &&
529 !(drv->flags & DM_FLAG_PRE_RELOC))
533 * We could pass the descriptor to the driver as
534 * platdata (instead of NULL) and allow its bind()
535 * method to return -ENOENT if it doesn't support this
536 * device. That way we could continue the search to
537 * find another driver. For now this doesn't seem
538 * necesssary, so just bind the first match.
540 ret = device_bind(parent, drv, drv->name, NULL, -1,
544 debug("%s: Match found: %s\n", __func__, drv->name);
545 dev->driver_data = find_id->driver_data;
551 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
553 * In the pre-relocation phase, we only bind bridge devices to save
554 * precious memory space as on some platforms as that space is pretty
555 * limited (ie: using Cache As RAM).
557 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
560 /* Bind a generic driver so that the device can be used */
561 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
566 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
568 ret = device_bind_driver(parent, drv, str, devp);
570 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
573 debug("%s: No match found: bound generic driver instead\n", __func__);
578 debug("%s: No match found: error %d\n", __func__, ret);
582 int pci_bind_bus_devices(struct udevice *bus)
584 ulong vendor, device;
591 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
592 PCI_MAX_PCI_FUNCTIONS - 1);
593 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end;
594 bdf += PCI_BDF(0, 0, 1)) {
595 struct pci_child_platdata *pplat;
599 if (PCI_FUNC(bdf) && !found_multi)
601 /* Check only the first access, we don't expect problems */
602 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
603 &header_type, PCI_SIZE_8);
606 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
608 if (vendor == 0xffff || vendor == 0x0000)
612 found_multi = header_type & 0x80;
614 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
615 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
616 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
618 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
622 /* Find this device in the device tree */
623 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
625 /* Search for a driver */
627 /* If nothing in the device tree, bind a generic device */
628 if (ret == -ENODEV) {
629 struct pci_device_id find_id;
632 memset(&find_id, '\0', sizeof(find_id));
633 find_id.vendor = vendor;
634 find_id.device = device;
635 find_id.class = class;
636 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
637 pci_bus_read_config(bus, bdf,
638 PCI_SUBSYSTEM_VENDOR_ID,
640 find_id.subvendor = val & 0xffff;
641 find_id.subdevice = val >> 16;
643 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
651 /* Update the platform data */
652 pplat = dev_get_parent_platdata(dev);
653 pplat->devfn = PCI_MASK_BUS(bdf);
654 pplat->vendor = vendor;
655 pplat->device = device;
656 pplat->class = class;
661 printf("Cannot read bus configuration: %d\n", ret);
666 static int pci_uclass_post_bind(struct udevice *bus)
669 * If there is no pci device listed in the device tree,
670 * don't bother scanning the device tree.
672 if (bus->of_offset == -1)
676 * Scan the device tree for devices. This does not probe the PCI bus,
677 * as this is not permitted while binding. It just finds devices
678 * mentioned in the device tree.
680 * Before relocation, only bind devices marked for pre-relocation
683 return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
684 gd->flags & GD_FLG_RELOC ? false : true);
687 static int decode_regions(struct pci_controller *hose, const void *blob,
688 int parent_node, int node)
690 int pci_addr_cells, addr_cells, size_cells;
691 phys_addr_t base = 0, size;
692 int cells_per_record;
697 prop = fdt_getprop(blob, node, "ranges", &len);
700 pci_addr_cells = fdt_address_cells(blob, node);
701 addr_cells = fdt_address_cells(blob, parent_node);
702 size_cells = fdt_size_cells(blob, node);
704 /* PCI addresses are always 3-cells */
706 cells_per_record = pci_addr_cells + addr_cells + size_cells;
707 hose->region_count = 0;
708 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
710 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
711 u64 pci_addr, addr, size;
717 if (len < cells_per_record)
719 flags = fdt32_to_cpu(prop[0]);
720 space_code = (flags >> 24) & 3;
721 pci_addr = fdtdec_get_number(prop + 1, 2);
722 prop += pci_addr_cells;
723 addr = fdtdec_get_number(prop, addr_cells);
725 size = fdtdec_get_number(prop, size_cells);
727 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
728 ", size=%" PRIx64 ", space_code=%d\n", __func__,
729 hose->region_count, pci_addr, addr, size, space_code);
730 if (space_code & 2) {
731 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
733 } else if (space_code & 1) {
734 type = PCI_REGION_IO;
739 for (i = 0; i < hose->region_count; i++) {
740 if (hose->regions[i].flags == type)
744 pos = hose->region_count++;
745 debug(" - type=%d, pos=%d\n", type, pos);
746 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
749 /* Add a region for our local memory */
751 #ifdef CONFIG_SYS_SDRAM_BASE
752 base = CONFIG_SYS_SDRAM_BASE;
754 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
755 size = gd->pci_ram_top - base;
756 pci_set_region(hose->regions + hose->region_count++, base, base,
757 size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
762 static int pci_uclass_pre_probe(struct udevice *bus)
764 struct pci_controller *hose;
767 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
769 hose = bus->uclass_priv;
771 /* For bridges, use the top-level PCI controller */
772 if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
774 ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
777 debug("%s: Cannot decode regions\n", __func__);
781 struct pci_controller *parent_hose;
783 parent_hose = dev_get_uclass_priv(bus->parent);
784 hose->ctlr = parent_hose->bus;
787 hose->first_busno = bus->seq;
788 hose->last_busno = bus->seq;
793 static int pci_uclass_post_probe(struct udevice *bus)
797 debug("%s: probing bus %d\n", __func__, bus->seq);
798 ret = pci_bind_bus_devices(bus);
802 #ifdef CONFIG_PCI_PNP
803 ret = pci_auto_config_devices(bus);
808 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
810 * Per Intel FSP specification, we should call FSP notify API to
811 * inform FSP that PCI enumeration has been done so that FSP will
812 * do any necessary initialization as required by the chipset's
813 * BIOS Writer's Guide (BWG).
815 * Unfortunately we have to put this call here as with driver model,
816 * the enumeration is all done on a lazy basis as needed, so until
817 * something is touched on PCI it won't happen.
819 * Note we only call this 1) after U-Boot is relocated, and 2)
820 * root bus has finished probing.
822 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
823 ret = fsp_init_phase_pci();
832 static int pci_uclass_child_post_bind(struct udevice *dev)
834 struct pci_child_platdata *pplat;
835 struct fdt_pci_addr addr;
838 if (dev->of_offset == -1)
842 * We could read vendor, device, class if available. But for now we
843 * just check the address.
845 pplat = dev_get_parent_platdata(dev);
846 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
847 FDT_PCI_SPACE_CONFIG, "reg", &addr);
853 /* extract the devfn from fdt_pci_addr */
854 pplat->devfn = addr.phys_hi & 0xff00;
860 static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
861 uint offset, ulong *valuep,
862 enum pci_size_t size)
864 struct pci_controller *hose = bus->uclass_priv;
866 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
869 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
870 uint offset, ulong value,
871 enum pci_size_t size)
873 struct pci_controller *hose = bus->uclass_priv;
875 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
878 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
884 * Scan through all the PCI controllers. On x86 there will only be one
885 * but that is not necessarily true on other hardware.
888 device_find_first_child(bus, &dev);
893 ret = uclass_next_device(&bus);
901 int pci_find_next_device(struct udevice **devp)
903 struct udevice *child = *devp;
904 struct udevice *bus = child->parent;
907 /* First try all the siblings */
910 device_find_next_child(&child);
917 /* We ran out of siblings. Try the next bus */
918 ret = uclass_next_device(&bus);
922 return bus ? skip_to_next_device(bus, devp) : 0;
925 int pci_find_first_device(struct udevice **devp)
931 ret = uclass_first_device(UCLASS_PCI, &bus);
935 return skip_to_next_device(bus, devp);
938 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
942 return (value >> ((offset & 3) * 8)) & 0xff;
944 return (value >> ((offset & 2) * 8)) & 0xffff;
950 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
951 enum pci_size_t size)
954 uint val_mask, shift;
969 shift = (offset & off_mask) * 8;
970 ldata = (value & val_mask) << shift;
971 mask = val_mask << shift;
972 value = (old & ~mask) | ldata;
977 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
978 struct pci_region **memp, struct pci_region **prefp)
980 struct udevice *bus = pci_get_controller(dev);
981 struct pci_controller *hose = dev_get_uclass_priv(bus);
987 for (i = 0; i < hose->region_count; i++) {
988 switch (hose->regions[i].flags) {
990 if (!*iop || (*iop)->size < hose->regions[i].size)
991 *iop = hose->regions + i;
994 if (!*memp || (*memp)->size < hose->regions[i].size)
995 *memp = hose->regions + i;
997 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
998 if (!*prefp || (*prefp)->size < hose->regions[i].size)
999 *prefp = hose->regions + i;
1004 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1007 UCLASS_DRIVER(pci) = {
1010 .flags = DM_UC_FLAG_SEQ_ALIAS,
1011 .post_bind = pci_uclass_post_bind,
1012 .pre_probe = pci_uclass_pre_probe,
1013 .post_probe = pci_uclass_post_probe,
1014 .child_post_bind = pci_uclass_child_post_bind,
1015 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1016 .per_child_platdata_auto_alloc_size =
1017 sizeof(struct pci_child_platdata),
1020 static const struct dm_pci_ops pci_bridge_ops = {
1021 .read_config = pci_bridge_read_config,
1022 .write_config = pci_bridge_write_config,
1025 static const struct udevice_id pci_bridge_ids[] = {
1026 { .compatible = "pci-bridge" },
1030 U_BOOT_DRIVER(pci_bridge_drv) = {
1031 .name = "pci_bridge_drv",
1033 .of_match = pci_bridge_ids,
1034 .ops = &pci_bridge_ops,
1037 UCLASS_DRIVER(pci_generic) = {
1038 .id = UCLASS_PCI_GENERIC,
1039 .name = "pci_generic",
1042 static const struct udevice_id pci_generic_ids[] = {
1043 { .compatible = "pci-generic" },
1047 U_BOOT_DRIVER(pci_generic_drv) = {
1048 .name = "pci_generic_drv",
1049 .id = UCLASS_PCI_GENERIC,
1050 .of_match = pci_generic_ids,