2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <dm/device-internal.h>
17 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
18 #include <asm/fsp/fsp_support.h>
20 #include "pci_internal.h"
22 DECLARE_GLOBAL_DATA_PTR;
24 static int pci_get_bus(int busnum, struct udevice **busp)
28 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
30 /* Since buses may not be numbered yet try a little harder with bus 0 */
32 ret = uclass_first_device(UCLASS_PCI, busp);
37 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
43 struct pci_controller *pci_bus_to_hose(int busnum)
48 ret = pci_get_bus(busnum, &bus);
50 debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret);
54 return dev_get_uclass_priv(bus);
57 struct udevice *pci_get_controller(struct udevice *dev)
59 while (device_is_on_pci_bus(dev))
65 pci_dev_t dm_pci_get_bdf(struct udevice *dev)
67 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
68 struct udevice *bus = dev->parent;
70 return PCI_ADD_BUS(bus->seq, pplat->devfn);
74 * pci_get_bus_max() - returns the bus number of the last active bus
76 * @return last bus number, or -1 if no active buses
78 static int pci_get_bus_max(void)
84 ret = uclass_get(UCLASS_PCI, &uc);
85 uclass_foreach_dev(bus, uc) {
90 debug("%s: ret=%d\n", __func__, ret);
95 int pci_last_busno(void)
97 return pci_get_bus_max();
100 int pci_get_ff(enum pci_size_t size)
112 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
113 struct udevice **devp)
117 for (device_find_first_child(bus, &dev);
119 device_find_next_child(&dev)) {
120 struct pci_child_platdata *pplat;
122 pplat = dev_get_parent_platdata(dev);
123 if (pplat && pplat->devfn == find_devfn) {
132 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
137 ret = pci_get_bus(PCI_BUS(bdf), &bus);
140 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
143 static int pci_device_matches_ids(struct udevice *dev,
144 struct pci_device_id *ids)
146 struct pci_child_platdata *pplat;
149 pplat = dev_get_parent_platdata(dev);
152 for (i = 0; ids[i].vendor != 0; i++) {
153 if (pplat->vendor == ids[i].vendor &&
154 pplat->device == ids[i].device)
161 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
162 int *indexp, struct udevice **devp)
166 /* Scan all devices on this bus */
167 for (device_find_first_child(bus, &dev);
169 device_find_next_child(&dev)) {
170 if (pci_device_matches_ids(dev, ids) >= 0) {
171 if ((*indexp)-- <= 0) {
181 int pci_find_device_id(struct pci_device_id *ids, int index,
182 struct udevice **devp)
186 /* Scan all known buses */
187 for (uclass_first_device(UCLASS_PCI, &bus);
189 uclass_next_device(&bus)) {
190 if (!pci_bus_find_devices(bus, ids, &index, devp))
198 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
199 unsigned int device, int *indexp,
200 struct udevice **devp)
202 struct pci_child_platdata *pplat;
205 for (device_find_first_child(bus, &dev);
207 device_find_next_child(&dev)) {
208 pplat = dev_get_parent_platdata(dev);
209 if (pplat->vendor == vendor && pplat->device == device) {
220 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
221 struct udevice **devp)
225 /* Scan all known buses */
226 for (uclass_first_device(UCLASS_PCI, &bus);
228 uclass_next_device(&bus)) {
229 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
230 return device_probe(*devp);
237 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
238 unsigned long value, enum pci_size_t size)
240 struct dm_pci_ops *ops;
242 ops = pci_get_ops(bus);
243 if (!ops->write_config)
245 return ops->write_config(bus, bdf, offset, value, size);
248 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
249 enum pci_size_t size)
254 ret = pci_get_bus(PCI_BUS(bdf), &bus);
258 return pci_bus_write_config(bus, bdf, offset, value, size);
261 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
262 enum pci_size_t size)
266 for (bus = dev; device_is_on_pci_bus(bus);)
268 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
273 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
275 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
278 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
280 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
283 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
285 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
288 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
290 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
293 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
295 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
298 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
300 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
303 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
304 unsigned long *valuep, enum pci_size_t size)
306 struct dm_pci_ops *ops;
308 ops = pci_get_ops(bus);
309 if (!ops->read_config)
311 return ops->read_config(bus, bdf, offset, valuep, size);
314 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
315 enum pci_size_t size)
320 ret = pci_get_bus(PCI_BUS(bdf), &bus);
324 return pci_bus_read_config(bus, bdf, offset, valuep, size);
327 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
328 enum pci_size_t size)
332 for (bus = dev; device_is_on_pci_bus(bus);)
334 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
338 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
343 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
351 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
356 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
364 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
369 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
377 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
382 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
390 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
395 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
403 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
408 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
416 static void set_vga_bridge_bits(struct udevice *dev)
418 struct udevice *parent = dev->parent;
421 while (parent->seq != 0) {
422 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
423 bc |= PCI_BRIDGE_CTL_VGA;
424 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
425 parent = parent->parent;
429 int pci_auto_config_devices(struct udevice *bus)
431 struct pci_controller *hose = bus->uclass_priv;
432 struct pci_child_platdata *pplat;
433 unsigned int sub_bus;
438 debug("%s: start\n", __func__);
439 pciauto_config_init(hose);
440 for (ret = device_find_first_child(bus, &dev);
442 ret = device_find_next_child(&dev)) {
443 unsigned int max_bus;
446 debug("%s: device %s\n", __func__, dev->name);
447 ret = dm_pciauto_config_device(dev);
451 sub_bus = max(sub_bus, max_bus);
453 pplat = dev_get_parent_platdata(dev);
454 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
455 set_vga_bridge_bits(dev);
457 debug("%s: done\n", __func__);
462 int dm_pci_hose_probe_bus(struct udevice *bus)
467 debug("%s\n", __func__);
469 sub_bus = pci_get_bus_max() + 1;
470 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
471 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
473 ret = device_probe(bus);
475 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
479 if (sub_bus != bus->seq) {
480 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
481 __func__, bus->name, bus->seq, sub_bus);
484 sub_bus = pci_get_bus_max();
485 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
491 * pci_match_one_device - Tell if a PCI device structure has a matching
492 * PCI device id structure
493 * @id: single PCI device id structure to match
494 * @dev: the PCI device structure to match against
496 * Returns the matching pci_device_id structure or %NULL if there is no match.
498 static bool pci_match_one_id(const struct pci_device_id *id,
499 const struct pci_device_id *find)
501 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
502 (id->device == PCI_ANY_ID || id->device == find->device) &&
503 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
504 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
505 !((id->class ^ find->class) & id->class_mask))
512 * pci_find_and_bind_driver() - Find and bind the right PCI driver
514 * This only looks at certain fields in the descriptor.
516 * @parent: Parent bus
517 * @find_id: Specification of the driver to find
518 * @bdf: Bus/device/function addreess - see PCI_BDF()
519 * @devp: Returns a pointer to the device created
520 * @return 0 if OK, -EPERM if the device is not needed before relocation and
521 * therefore was not created, other -ve value on error
523 static int pci_find_and_bind_driver(struct udevice *parent,
524 struct pci_device_id *find_id,
525 pci_dev_t bdf, struct udevice **devp)
527 struct pci_driver_entry *start, *entry;
536 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
537 find_id->vendor, find_id->device);
538 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
539 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
540 for (entry = start; entry != start + n_ents; entry++) {
541 const struct pci_device_id *id;
543 const struct driver *drv;
545 for (id = entry->match;
546 id->vendor || id->subvendor || id->class_mask;
548 if (!pci_match_one_id(id, find_id))
554 * In the pre-relocation phase, we only bind devices
555 * whose driver has the DM_FLAG_PRE_RELOC set, to save
556 * precious memory space as on some platforms as that
557 * space is pretty limited (ie: using Cache As RAM).
559 if (!(gd->flags & GD_FLG_RELOC) &&
560 !(drv->flags & DM_FLAG_PRE_RELOC))
564 * We could pass the descriptor to the driver as
565 * platdata (instead of NULL) and allow its bind()
566 * method to return -ENOENT if it doesn't support this
567 * device. That way we could continue the search to
568 * find another driver. For now this doesn't seem
569 * necesssary, so just bind the first match.
571 ret = device_bind(parent, drv, drv->name, NULL, -1,
575 debug("%s: Match found: %s\n", __func__, drv->name);
576 dev->driver_data = find_id->driver_data;
582 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
584 * In the pre-relocation phase, we only bind bridge devices to save
585 * precious memory space as on some platforms as that space is pretty
586 * limited (ie: using Cache As RAM).
588 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
591 /* Bind a generic driver so that the device can be used */
592 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
597 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
599 ret = device_bind_driver(parent, drv, str, devp);
601 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
604 debug("%s: No match found: bound generic driver instead\n", __func__);
609 debug("%s: No match found: error %d\n", __func__, ret);
613 int pci_bind_bus_devices(struct udevice *bus)
615 ulong vendor, device;
622 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
623 PCI_MAX_PCI_FUNCTIONS - 1);
624 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end;
625 bdf += PCI_BDF(0, 0, 1)) {
626 struct pci_child_platdata *pplat;
630 if (PCI_FUNC(bdf) && !found_multi)
632 /* Check only the first access, we don't expect problems */
633 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
634 &header_type, PCI_SIZE_8);
637 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
639 if (vendor == 0xffff || vendor == 0x0000)
643 found_multi = header_type & 0x80;
645 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
646 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
647 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
649 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
653 /* Find this device in the device tree */
654 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
656 /* Search for a driver */
658 /* If nothing in the device tree, bind a generic device */
659 if (ret == -ENODEV) {
660 struct pci_device_id find_id;
663 memset(&find_id, '\0', sizeof(find_id));
664 find_id.vendor = vendor;
665 find_id.device = device;
666 find_id.class = class;
667 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
668 pci_bus_read_config(bus, bdf,
669 PCI_SUBSYSTEM_VENDOR_ID,
671 find_id.subvendor = val & 0xffff;
672 find_id.subdevice = val >> 16;
674 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
682 /* Update the platform data */
683 pplat = dev_get_parent_platdata(dev);
684 pplat->devfn = PCI_MASK_BUS(bdf);
685 pplat->vendor = vendor;
686 pplat->device = device;
687 pplat->class = class;
692 printf("Cannot read bus configuration: %d\n", ret);
697 static int pci_uclass_post_bind(struct udevice *bus)
700 * If there is no pci device listed in the device tree,
701 * don't bother scanning the device tree.
703 if (bus->of_offset == -1)
707 * Scan the device tree for devices. This does not probe the PCI bus,
708 * as this is not permitted while binding. It just finds devices
709 * mentioned in the device tree.
711 * Before relocation, only bind devices marked for pre-relocation
714 return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
715 gd->flags & GD_FLG_RELOC ? false : true);
718 static int decode_regions(struct pci_controller *hose, const void *blob,
719 int parent_node, int node)
721 int pci_addr_cells, addr_cells, size_cells;
722 phys_addr_t base = 0, size;
723 int cells_per_record;
728 prop = fdt_getprop(blob, node, "ranges", &len);
731 pci_addr_cells = fdt_address_cells(blob, node);
732 addr_cells = fdt_address_cells(blob, parent_node);
733 size_cells = fdt_size_cells(blob, node);
735 /* PCI addresses are always 3-cells */
737 cells_per_record = pci_addr_cells + addr_cells + size_cells;
738 hose->region_count = 0;
739 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
741 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
742 u64 pci_addr, addr, size;
748 if (len < cells_per_record)
750 flags = fdt32_to_cpu(prop[0]);
751 space_code = (flags >> 24) & 3;
752 pci_addr = fdtdec_get_number(prop + 1, 2);
753 prop += pci_addr_cells;
754 addr = fdtdec_get_number(prop, addr_cells);
756 size = fdtdec_get_number(prop, size_cells);
758 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
759 ", size=%" PRIx64 ", space_code=%d\n", __func__,
760 hose->region_count, pci_addr, addr, size, space_code);
761 if (space_code & 2) {
762 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
764 } else if (space_code & 1) {
765 type = PCI_REGION_IO;
770 for (i = 0; i < hose->region_count; i++) {
771 if (hose->regions[i].flags == type)
775 pos = hose->region_count++;
776 debug(" - type=%d, pos=%d\n", type, pos);
777 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
780 /* Add a region for our local memory */
782 #ifdef CONFIG_SYS_SDRAM_BASE
783 base = CONFIG_SYS_SDRAM_BASE;
785 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
786 size = gd->pci_ram_top - base;
787 pci_set_region(hose->regions + hose->region_count++, base, base,
788 size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
793 static int pci_uclass_pre_probe(struct udevice *bus)
795 struct pci_controller *hose;
798 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
800 hose = bus->uclass_priv;
802 /* For bridges, use the top-level PCI controller */
803 if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
805 ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
808 debug("%s: Cannot decode regions\n", __func__);
812 struct pci_controller *parent_hose;
814 parent_hose = dev_get_uclass_priv(bus->parent);
815 hose->ctlr = parent_hose->bus;
818 hose->first_busno = bus->seq;
819 hose->last_busno = bus->seq;
824 static int pci_uclass_post_probe(struct udevice *bus)
828 debug("%s: probing bus %d\n", __func__, bus->seq);
829 ret = pci_bind_bus_devices(bus);
833 #ifdef CONFIG_PCI_PNP
834 ret = pci_auto_config_devices(bus);
839 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
841 * Per Intel FSP specification, we should call FSP notify API to
842 * inform FSP that PCI enumeration has been done so that FSP will
843 * do any necessary initialization as required by the chipset's
844 * BIOS Writer's Guide (BWG).
846 * Unfortunately we have to put this call here as with driver model,
847 * the enumeration is all done on a lazy basis as needed, so until
848 * something is touched on PCI it won't happen.
850 * Note we only call this 1) after U-Boot is relocated, and 2)
851 * root bus has finished probing.
853 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
854 ret = fsp_init_phase_pci();
863 static int pci_uclass_child_post_bind(struct udevice *dev)
865 struct pci_child_platdata *pplat;
866 struct fdt_pci_addr addr;
869 if (dev->of_offset == -1)
873 * We could read vendor, device, class if available. But for now we
874 * just check the address.
876 pplat = dev_get_parent_platdata(dev);
877 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
878 FDT_PCI_SPACE_CONFIG, "reg", &addr);
884 /* extract the devfn from fdt_pci_addr */
885 pplat->devfn = addr.phys_hi & 0xff00;
891 static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
892 uint offset, ulong *valuep,
893 enum pci_size_t size)
895 struct pci_controller *hose = bus->uclass_priv;
897 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
900 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
901 uint offset, ulong value,
902 enum pci_size_t size)
904 struct pci_controller *hose = bus->uclass_priv;
906 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
909 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
915 * Scan through all the PCI controllers. On x86 there will only be one
916 * but that is not necessarily true on other hardware.
919 device_find_first_child(bus, &dev);
924 ret = uclass_next_device(&bus);
932 int pci_find_next_device(struct udevice **devp)
934 struct udevice *child = *devp;
935 struct udevice *bus = child->parent;
938 /* First try all the siblings */
941 device_find_next_child(&child);
948 /* We ran out of siblings. Try the next bus */
949 ret = uclass_next_device(&bus);
953 return bus ? skip_to_next_device(bus, devp) : 0;
956 int pci_find_first_device(struct udevice **devp)
962 ret = uclass_first_device(UCLASS_PCI, &bus);
966 return skip_to_next_device(bus, devp);
969 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
973 return (value >> ((offset & 3) * 8)) & 0xff;
975 return (value >> ((offset & 2) * 8)) & 0xffff;
981 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
982 enum pci_size_t size)
985 uint val_mask, shift;
1000 shift = (offset & off_mask) * 8;
1001 ldata = (value & val_mask) << shift;
1002 mask = val_mask << shift;
1003 value = (old & ~mask) | ldata;
1008 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1009 struct pci_region **memp, struct pci_region **prefp)
1011 struct udevice *bus = pci_get_controller(dev);
1012 struct pci_controller *hose = dev_get_uclass_priv(bus);
1018 for (i = 0; i < hose->region_count; i++) {
1019 switch (hose->regions[i].flags) {
1021 if (!*iop || (*iop)->size < hose->regions[i].size)
1022 *iop = hose->regions + i;
1024 case PCI_REGION_MEM:
1025 if (!*memp || (*memp)->size < hose->regions[i].size)
1026 *memp = hose->regions + i;
1028 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1029 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1030 *prefp = hose->regions + i;
1035 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1038 UCLASS_DRIVER(pci) = {
1041 .flags = DM_UC_FLAG_SEQ_ALIAS,
1042 .post_bind = pci_uclass_post_bind,
1043 .pre_probe = pci_uclass_pre_probe,
1044 .post_probe = pci_uclass_post_probe,
1045 .child_post_bind = pci_uclass_child_post_bind,
1046 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1047 .per_child_platdata_auto_alloc_size =
1048 sizeof(struct pci_child_platdata),
1051 static const struct dm_pci_ops pci_bridge_ops = {
1052 .read_config = pci_bridge_read_config,
1053 .write_config = pci_bridge_write_config,
1056 static const struct udevice_id pci_bridge_ids[] = {
1057 { .compatible = "pci-bridge" },
1061 U_BOOT_DRIVER(pci_bridge_drv) = {
1062 .name = "pci_bridge_drv",
1064 .of_match = pci_bridge_ids,
1065 .ops = &pci_bridge_ops,
1068 UCLASS_DRIVER(pci_generic) = {
1069 .id = UCLASS_PCI_GENERIC,
1070 .name = "pci_generic",
1073 static const struct udevice_id pci_generic_ids[] = {
1074 { .compatible = "pci-generic" },
1078 U_BOOT_DRIVER(pci_generic_drv) = {
1079 .name = "pci_generic_drv",
1080 .id = UCLASS_PCI_GENERIC,
1081 .of_match = pci_generic_ids,