2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <dm/device-internal.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 struct pci_controller *pci_bus_to_hose(int busnum)
25 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
27 debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret);
30 return dev_get_uclass_priv(bus);
33 pci_dev_t pci_get_bdf(struct udevice *dev)
35 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
36 struct udevice *bus = dev->parent;
38 return PCI_ADD_BUS(bus->seq, pplat->devfn);
42 * pci_get_bus_max() - returns the bus number of the last active bus
44 * @return last bus number, or -1 if no active buses
46 static int pci_get_bus_max(void)
52 ret = uclass_get(UCLASS_PCI, &uc);
53 uclass_foreach_dev(bus, uc) {
58 debug("%s: ret=%d\n", __func__, ret);
63 int pci_last_busno(void)
65 struct pci_controller *hose;
70 debug("pci_last_busno\n");
71 ret = uclass_get(UCLASS_PCI, &uc);
72 if (ret || list_empty(&uc->dev_head))
75 /* Probe the last bus */
76 bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node);
77 debug("bus = %p, %s\n", bus, bus->name);
79 ret = device_probe(bus);
83 /* If that bus has bridges, we may have new buses now. Get the last */
84 bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node);
85 hose = dev_get_uclass_priv(bus);
86 debug("bus = %s, hose = %p\n", bus->name, hose);
88 return hose->last_busno;
91 int pci_get_ff(enum pci_size_t size)
103 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
104 struct udevice **devp)
108 for (device_find_first_child(bus, &dev);
110 device_find_next_child(&dev)) {
111 struct pci_child_platdata *pplat;
113 pplat = dev_get_parent_platdata(dev);
114 if (pplat && pplat->devfn == find_devfn) {
123 int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
128 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus);
131 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
134 static int pci_device_matches_ids(struct udevice *dev,
135 struct pci_device_id *ids)
137 struct pci_child_platdata *pplat;
140 pplat = dev_get_parent_platdata(dev);
143 for (i = 0; ids[i].vendor != 0; i++) {
144 if (pplat->vendor == ids[i].vendor &&
145 pplat->device == ids[i].device)
152 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
153 int *indexp, struct udevice **devp)
157 /* Scan all devices on this bus */
158 for (device_find_first_child(bus, &dev);
160 device_find_next_child(&dev)) {
161 if (pci_device_matches_ids(dev, ids) >= 0) {
162 if ((*indexp)-- <= 0) {
172 int pci_find_device_id(struct pci_device_id *ids, int index,
173 struct udevice **devp)
177 /* Scan all known buses */
178 for (uclass_first_device(UCLASS_PCI, &bus);
180 uclass_next_device(&bus)) {
181 if (!pci_bus_find_devices(bus, ids, &index, devp))
189 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
190 unsigned long value, enum pci_size_t size)
192 struct dm_pci_ops *ops;
194 ops = pci_get_ops(bus);
195 if (!ops->write_config)
197 return ops->write_config(bus, bdf, offset, value, size);
200 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
201 enum pci_size_t size)
206 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus);
210 return pci_bus_write_config(bus, bdf, offset, value, size);
213 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
215 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
218 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
220 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
223 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
225 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
228 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
229 unsigned long *valuep, enum pci_size_t size)
231 struct dm_pci_ops *ops;
233 ops = pci_get_ops(bus);
234 if (!ops->read_config)
236 return ops->read_config(bus, bdf, offset, valuep, size);
239 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
240 enum pci_size_t size)
245 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus);
249 return pci_bus_read_config(bus, bdf, offset, valuep, size);
252 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
257 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
265 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
270 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
278 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
283 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
291 int pci_auto_config_devices(struct udevice *bus)
293 struct pci_controller *hose = bus->uclass_priv;
294 unsigned int sub_bus;
299 debug("%s: start\n", __func__);
300 pciauto_config_init(hose);
301 for (ret = device_find_first_child(bus, &dev);
303 ret = device_find_next_child(&dev)) {
304 struct pci_controller *ctlr_hose;
305 unsigned int max_bus;
307 debug("%s: device %s\n", __func__, dev->name);
309 /* The root controller has the region information */
310 ctlr_hose = hose->ctlr->uclass_priv;
311 max_bus = pciauto_config_device(ctlr_hose, pci_get_bdf(dev));
312 sub_bus = max(sub_bus, max_bus);
314 debug("%s: done\n", __func__);
319 int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf)
321 struct udevice *parent, *bus;
325 debug("%s\n", __func__);
328 /* Find the bus within the parent */
329 ret = pci_bus_find_devfn(parent, PCI_MASK_BUS(bdf), &bus);
331 debug("%s: Cannot find device %x on bus %s: %d\n", __func__,
332 bdf, parent->name, ret);
336 sub_bus = pci_get_bus_max() + 1;
337 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
338 pciauto_prescan_setup_bridge(hose, bdf, sub_bus);
340 ret = device_probe(bus);
342 debug("%s: Cannot probe bus bus %s: %d\n", __func__, bus->name,
346 if (sub_bus != bus->seq) {
347 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
348 __func__, bus->name, bus->seq, sub_bus);
351 sub_bus = pci_get_bus_max();
352 pciauto_postscan_setup_bridge(hose, bdf, sub_bus);
358 * pci_match_one_device - Tell if a PCI device structure has a matching
359 * PCI device id structure
360 * @id: single PCI device id structure to match
361 * @dev: the PCI device structure to match against
363 * Returns the matching pci_device_id structure or %NULL if there is no match.
365 static bool pci_match_one_id(const struct pci_device_id *id,
366 const struct pci_device_id *find)
368 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
369 (id->device == PCI_ANY_ID || id->device == find->device) &&
370 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
371 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
372 !((id->class ^ find->class) & id->class_mask))
379 * pci_find_and_bind_driver() - Find and bind the right PCI driver
381 * This only looks at certain fields in the descriptor.
383 static int pci_find_and_bind_driver(struct udevice *parent,
384 struct pci_device_id *find_id, pci_dev_t bdf,
385 struct udevice **devp)
387 struct pci_driver_entry *start, *entry;
395 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
396 find_id->vendor, find_id->device);
397 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
398 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
399 for (entry = start; entry != start + n_ents; entry++) {
400 const struct pci_device_id *id;
402 const struct driver *drv;
404 for (id = entry->match;
405 id->vendor || id->subvendor || id->class_mask;
407 if (!pci_match_one_id(id, find_id))
412 * We could pass the descriptor to the driver as
413 * platdata (instead of NULL) and allow its bind()
414 * method to return -ENOENT if it doesn't support this
415 * device. That way we could continue the search to
416 * find another driver. For now this doesn't seem
417 * necesssary, so just bind the first match.
419 ret = device_bind(parent, drv, drv->name, NULL, -1,
423 debug("%s: Match found: %s\n", __func__, drv->name);
424 dev->driver_data = find_id->driver_data;
430 /* Bind a generic driver so that the device can be used */
431 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
436 drv = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI ? "pci_bridge_drv" :
438 ret = device_bind_driver(parent, drv, str, devp);
440 debug("%s: Failed to bind generic driver: %d", __func__, ret);
443 debug("%s: No match found: bound generic driver instead\n", __func__);
448 debug("%s: No match found: error %d\n", __func__, ret);
452 int pci_bind_bus_devices(struct udevice *bus)
454 ulong vendor, device;
461 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
462 PCI_MAX_PCI_FUNCTIONS - 1);
463 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end;
464 bdf += PCI_BDF(0, 0, 1)) {
465 struct pci_child_platdata *pplat;
469 if (PCI_FUNC(bdf) && !found_multi)
471 /* Check only the first access, we don't expect problems */
472 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
473 &header_type, PCI_SIZE_8);
476 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
478 if (vendor == 0xffff || vendor == 0x0000)
482 found_multi = header_type & 0x80;
484 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
485 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
486 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
488 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
492 /* Find this device in the device tree */
493 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
495 /* Search for a driver */
497 /* If nothing in the device tree, bind a generic device */
498 if (ret == -ENODEV) {
499 struct pci_device_id find_id;
502 memset(&find_id, '\0', sizeof(find_id));
503 find_id.vendor = vendor;
504 find_id.device = device;
505 find_id.class = class;
506 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
507 pci_bus_read_config(bus, bdf,
508 PCI_SUBSYSTEM_VENDOR_ID,
510 find_id.subvendor = val & 0xffff;
511 find_id.subdevice = val >> 16;
513 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
519 /* Update the platform data */
520 pplat = dev_get_parent_platdata(dev);
521 pplat->devfn = PCI_MASK_BUS(bdf);
522 pplat->vendor = vendor;
523 pplat->device = device;
524 pplat->class = class;
529 printf("Cannot read bus configuration: %d\n", ret);
534 static int pci_uclass_post_bind(struct udevice *bus)
537 * Scan the device tree for devices. This does not probe the PCI bus,
538 * as this is not permitted while binding. It just finds devices
539 * mentioned in the device tree.
541 * Before relocation, only bind devices marked for pre-relocation
544 return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
545 gd->flags & GD_FLG_RELOC ? false : true);
548 static int decode_regions(struct pci_controller *hose, const void *blob,
549 int parent_node, int node)
551 int pci_addr_cells, addr_cells, size_cells;
552 int cells_per_record;
558 prop = fdt_getprop(blob, node, "ranges", &len);
561 pci_addr_cells = fdt_address_cells(blob, node);
562 addr_cells = fdt_address_cells(blob, parent_node);
563 size_cells = fdt_size_cells(blob, node);
565 /* PCI addresses are always 3-cells */
567 cells_per_record = pci_addr_cells + addr_cells + size_cells;
568 hose->region_count = 0;
569 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
571 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
572 u64 pci_addr, addr, size;
577 if (len < cells_per_record)
579 flags = fdt32_to_cpu(prop[0]);
580 space_code = (flags >> 24) & 3;
581 pci_addr = fdtdec_get_number(prop + 1, 2);
582 prop += pci_addr_cells;
583 addr = fdtdec_get_number(prop, addr_cells);
585 size = fdtdec_get_number(prop, size_cells);
587 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
588 ", size=%" PRIx64 ", space_code=%d\n", __func__,
589 hose->region_count, pci_addr, addr, size, space_code);
590 if (space_code & 2) {
591 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
593 } else if (space_code & 1) {
594 type = PCI_REGION_IO;
598 debug(" - type=%d\n", type);
599 pci_set_region(hose->regions + hose->region_count++, pci_addr,
603 /* Add a region for our local memory */
605 if (gd->pci_ram_top && gd->pci_ram_top < addr)
606 addr = gd->pci_ram_top;
607 pci_set_region(hose->regions + hose->region_count++, 0, 0, addr,
608 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
613 static int pci_uclass_pre_probe(struct udevice *bus)
615 struct pci_controller *hose;
618 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
620 hose = bus->uclass_priv;
622 /* For bridges, use the top-level PCI controller */
623 if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
625 ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
628 debug("%s: Cannot decode regions\n", __func__);
632 struct pci_controller *parent_hose;
634 parent_hose = dev_get_uclass_priv(bus->parent);
635 hose->ctlr = parent_hose->bus;
638 hose->first_busno = bus->seq;
639 hose->last_busno = bus->seq;
644 static int pci_uclass_post_probe(struct udevice *bus)
648 /* Don't scan buses before relocation */
649 if (!(gd->flags & GD_FLG_RELOC))
652 debug("%s: probing bus %d\n", __func__, bus->seq);
653 ret = pci_bind_bus_devices(bus);
657 #ifdef CONFIG_PCI_PNP
658 ret = pci_auto_config_devices(bus);
661 return ret < 0 ? ret : 0;
664 static int pci_uclass_child_post_bind(struct udevice *dev)
666 struct pci_child_platdata *pplat;
667 struct fdt_pci_addr addr;
670 if (dev->of_offset == -1)
674 * We could read vendor, device, class if available. But for now we
675 * just check the address.
677 pplat = dev_get_parent_platdata(dev);
678 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
679 FDT_PCI_SPACE_CONFIG, "reg", &addr);
685 /* extract the bdf from fdt_pci_addr */
686 pplat->devfn = addr.phys_hi & 0xffff00;
692 static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
693 uint offset, ulong *valuep,
694 enum pci_size_t size)
696 struct pci_controller *hose = bus->uclass_priv;
698 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
701 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
702 uint offset, ulong value,
703 enum pci_size_t size)
705 struct pci_controller *hose = bus->uclass_priv;
707 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
710 UCLASS_DRIVER(pci) = {
713 .flags = DM_UC_FLAG_SEQ_ALIAS,
714 .post_bind = pci_uclass_post_bind,
715 .pre_probe = pci_uclass_pre_probe,
716 .post_probe = pci_uclass_post_probe,
717 .child_post_bind = pci_uclass_child_post_bind,
718 .per_device_auto_alloc_size = sizeof(struct pci_controller),
719 .per_child_platdata_auto_alloc_size =
720 sizeof(struct pci_child_platdata),
723 static const struct dm_pci_ops pci_bridge_ops = {
724 .read_config = pci_bridge_read_config,
725 .write_config = pci_bridge_write_config,
728 static const struct udevice_id pci_bridge_ids[] = {
729 { .compatible = "pci-bridge" },
733 U_BOOT_DRIVER(pci_bridge_drv) = {
734 .name = "pci_bridge_drv",
736 .of_match = pci_bridge_ids,
737 .ops = &pci_bridge_ops,
740 UCLASS_DRIVER(pci_generic) = {
741 .id = UCLASS_PCI_GENERIC,
742 .name = "pci_generic",
745 static const struct udevice_id pci_generic_ids[] = {
746 { .compatible = "pci-generic" },
750 U_BOOT_DRIVER(pci_generic_drv) = {
751 .name = "pci_generic_drv",
752 .id = UCLASS_PCI_GENERIC,
753 .of_match = pci_generic_ids,