2 * arch/powerpc/kernel/pci_auto.c
4 * PCI autoconfiguration library
6 * Author: Matt Porter <mporter@mvista.com>
8 * Copyright 2000 MontaVista Software Inc.
10 * SPDX-License-Identifier: GPL-2.0+
18 #define DEBUGF(x...) printf(x)
23 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
24 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
25 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
32 void pciauto_region_init(struct pci_region *res)
35 * Avoid allocating PCI resources from address 0 -- this is illegal
36 * according to PCI 2.1 and moreover, this is known to cause Linux IDE
37 * drivers to fail. Use a reasonable starting value of 0x1000 instead.
39 res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
42 void pciauto_region_align(struct pci_region *res, pci_size_t size)
44 res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
47 int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
53 DEBUGF("No resource");
57 addr = ((res->bus_lower - 1) | (size - 1)) + 1;
59 if (addr - res->bus_start + size > res->size) {
60 DEBUGF("No room in resource");
64 res->bus_lower = addr + size;
66 DEBUGF("address=0x%llx bus_lower=0x%llx", (u64)addr, (u64)res->bus_lower);
72 *bar = (pci_addr_t)-1;
80 void pciauto_setup_device(struct pci_controller *hose,
81 pci_dev_t dev, int bars_num,
82 struct pci_region *mem,
83 struct pci_region *prefetch,
84 struct pci_region *io)
92 #ifndef CONFIG_PCI_ENUM_ONLY
94 struct pci_region *bar_res;
98 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
99 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
101 for (bar = PCI_BASE_ADDRESS_0;
102 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
103 /* Tickle the BAR and get the response */
104 #ifndef CONFIG_PCI_ENUM_ONLY
105 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
107 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
109 /* If BAR is not implemented go to the next BAR */
113 #ifndef CONFIG_PCI_ENUM_ONLY
117 /* Check the BAR type and set our address mask */
118 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
119 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
121 #ifndef CONFIG_PCI_ENUM_ONLY
125 DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
127 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
128 PCI_BASE_ADDRESS_MEM_TYPE_64) {
129 u32 bar_response_upper;
132 #ifndef CONFIG_PCI_ENUM_ONLY
133 pci_hose_write_config_dword(hose, dev, bar + 4,
136 pci_hose_read_config_dword(hose, dev, bar + 4,
137 &bar_response_upper);
139 bar64 = ((u64)bar_response_upper << 32) | bar_response;
141 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
142 #ifndef CONFIG_PCI_ENUM_ONLY
146 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
148 #ifndef CONFIG_PCI_ENUM_ONLY
149 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
155 DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
158 #ifndef CONFIG_PCI_ENUM_ONLY
159 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
160 /* Write it out and update our limit */
161 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
165 #ifdef CONFIG_SYS_PCI_64BIT
166 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
169 * If we are a 64-bit decoder then increment to the
170 * upper 32 bits of the bar and force it to locate
171 * in the lower 4GB of memory.
173 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
179 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
180 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
187 /* Configure the expansion ROM address */
188 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
189 if (header_type != PCI_HEADER_TYPE_CARDBUS) {
190 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
191 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
192 pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
193 pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
195 bar_size = -(bar_response & ~1);
196 DEBUGF("PCI Autoconfig: ROM, size=%#x, ", bar_size);
197 if (pciauto_region_allocate(mem, bar_size,
199 pci_hose_write_config_dword(hose, dev, rom_addr,
202 cmdstat |= PCI_COMMAND_MEMORY;
207 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
208 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
209 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
210 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
213 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
214 pci_dev_t dev, int sub_bus)
216 struct pci_region *pci_mem;
217 struct pci_region *pci_prefetch;
218 struct pci_region *pci_io;
219 u16 cmdstat, prefechable_64;
222 /* The root controller has the region information */
223 struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
225 pci_mem = ctlr_hose->pci_mem;
226 pci_prefetch = ctlr_hose->pci_prefetch;
227 pci_io = ctlr_hose->pci_io;
229 pci_mem = hose->pci_mem;
230 pci_prefetch = hose->pci_prefetch;
231 pci_io = hose->pci_io;
234 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
235 pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
237 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
239 /* Configure bus number registers */
241 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
242 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
244 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
245 PCI_BUS(dev) - hose->first_busno);
246 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
247 sub_bus - hose->first_busno);
249 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
252 /* Round memory allocator to 1MB boundary */
253 pciauto_region_align(pci_mem, 0x100000);
255 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
256 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
257 (pci_mem->bus_lower & 0xfff00000) >> 16);
259 cmdstat |= PCI_COMMAND_MEMORY;
263 /* Round memory allocator to 1MB boundary */
264 pciauto_region_align(pci_prefetch, 0x100000);
266 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
267 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
268 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
269 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
270 #ifdef CONFIG_SYS_PCI_64BIT
271 pci_hose_write_config_dword(hose, dev,
272 PCI_PREF_BASE_UPPER32,
273 pci_prefetch->bus_lower >> 32);
275 pci_hose_write_config_dword(hose, dev,
276 PCI_PREF_BASE_UPPER32,
280 cmdstat |= PCI_COMMAND_MEMORY;
282 /* We don't support prefetchable memory for now, so disable */
283 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
284 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
285 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
286 pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
287 pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
292 /* Round I/O allocator to 4KB boundary */
293 pciauto_region_align(pci_io, 0x1000);
295 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
296 (pci_io->bus_lower & 0x0000f000) >> 8);
297 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
298 (pci_io->bus_lower & 0xffff0000) >> 16);
300 cmdstat |= PCI_COMMAND_IO;
303 /* Enable memory and I/O accesses, enable bus master */
304 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
305 cmdstat | PCI_COMMAND_MASTER);
308 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
309 pci_dev_t dev, int sub_bus)
311 struct pci_region *pci_mem;
312 struct pci_region *pci_prefetch;
313 struct pci_region *pci_io;
316 /* The root controller has the region information */
317 struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
319 pci_mem = ctlr_hose->pci_mem;
320 pci_prefetch = ctlr_hose->pci_prefetch;
321 pci_io = ctlr_hose->pci_io;
323 pci_mem = hose->pci_mem;
324 pci_prefetch = hose->pci_prefetch;
325 pci_io = hose->pci_io;
328 /* Configure bus number registers */
330 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
332 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
333 sub_bus - hose->first_busno);
337 /* Round memory allocator to 1MB boundary */
338 pciauto_region_align(pci_mem, 0x100000);
340 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
341 (pci_mem->bus_lower - 1) >> 16);
347 pci_hose_read_config_word(hose, dev,
348 PCI_PREF_MEMORY_LIMIT,
350 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
352 /* Round memory allocator to 1MB boundary */
353 pciauto_region_align(pci_prefetch, 0x100000);
355 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
356 (pci_prefetch->bus_lower - 1) >> 16);
357 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
358 #ifdef CONFIG_SYS_PCI_64BIT
359 pci_hose_write_config_dword(hose, dev,
360 PCI_PREF_LIMIT_UPPER32,
361 (pci_prefetch->bus_lower - 1) >> 32);
363 pci_hose_write_config_dword(hose, dev,
364 PCI_PREF_LIMIT_UPPER32,
370 /* Round I/O allocator to 4KB boundary */
371 pciauto_region_align(pci_io, 0x1000);
373 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
374 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
375 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
376 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
384 void pciauto_config_init(struct pci_controller *hose)
388 hose->pci_io = hose->pci_mem = hose->pci_prefetch = NULL;
390 for (i = 0; i < hose->region_count; i++) {
391 switch(hose->regions[i].flags) {
394 hose->pci_io->size < hose->regions[i].size)
395 hose->pci_io = hose->regions + i;
398 if (!hose->pci_mem ||
399 hose->pci_mem->size < hose->regions[i].size)
400 hose->pci_mem = hose->regions + i;
402 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
403 if (!hose->pci_prefetch ||
404 hose->pci_prefetch->size < hose->regions[i].size)
405 hose->pci_prefetch = hose->regions + i;
412 pciauto_region_init(hose->pci_mem);
414 DEBUGF("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
415 "\t\tPhysical Memory [%llx-%llxx]\n",
416 (u64)hose->pci_mem->bus_start,
417 (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
418 (u64)hose->pci_mem->phys_start,
419 (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
422 if (hose->pci_prefetch) {
423 pciauto_region_init(hose->pci_prefetch);
425 DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
426 "\t\tPhysical Memory [%llx-%llx]\n",
427 (u64)hose->pci_prefetch->bus_start,
428 (u64)(hose->pci_prefetch->bus_start +
429 hose->pci_prefetch->size - 1),
430 (u64)hose->pci_prefetch->phys_start,
431 (u64)(hose->pci_prefetch->phys_start +
432 hose->pci_prefetch->size - 1));
436 pciauto_region_init(hose->pci_io);
438 DEBUGF("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
439 "\t\tPhysical Memory: [%llx-%llx]\n",
440 (u64)hose->pci_io->bus_start,
441 (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
442 (u64)hose->pci_io->phys_start,
443 (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
449 * HJF: Changed this to return int. I think this is required
450 * to get the correct result when scanning bridges
452 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
454 struct pci_region *pci_mem;
455 struct pci_region *pci_prefetch;
456 struct pci_region *pci_io;
457 unsigned int sub_bus = PCI_BUS(dev);
458 unsigned short class;
462 /* The root controller has the region information */
463 struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
465 pci_mem = ctlr_hose->pci_mem;
466 pci_prefetch = ctlr_hose->pci_prefetch;
467 pci_io = ctlr_hose->pci_io;
469 pci_mem = hose->pci_mem;
470 pci_prefetch = hose->pci_prefetch;
471 pci_io = hose->pci_io;
474 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
477 case PCI_CLASS_BRIDGE_PCI:
478 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n",
481 pciauto_setup_device(hose, dev, 2, pci_mem,
482 pci_prefetch, pci_io);
485 n = dm_pci_hose_probe_bus(hose, dev);
488 sub_bus = (unsigned int)n;
490 /* Passing in current_busno allows for sibling P2P bridges */
491 hose->current_busno++;
492 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
494 * need to figure out if this is a subordinate bridge on the bus
495 * to be able to properly set the pri/sec/sub bridge registers.
497 n = pci_hose_scan_bus(hose, hose->current_busno);
499 /* figure out the deepest we've gone for this leg */
500 sub_bus = max((unsigned int)n, sub_bus);
501 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
503 sub_bus = hose->current_busno;
507 case PCI_CLASS_BRIDGE_CARDBUS:
509 * just do a minimal setup of the bridge,
510 * let the OS take care of the rest
512 pciauto_setup_device(hose, dev, 0, pci_mem,
513 pci_prefetch, pci_io);
515 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
518 #ifndef CONFIG_DM_PCI
519 hose->current_busno++;
523 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
524 case PCI_CLASS_BRIDGE_OTHER:
525 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
529 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
530 case PCI_CLASS_BRIDGE_OTHER:
532 * The host/PCI bridge 1 seems broken in 8349 - it presents
533 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
534 * device claiming resources io/mem/irq.. we only allow for
535 * the PIMMR window to be allocated (BAR0 - 1MB size)
537 DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
538 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
539 hose->pci_prefetch, hose->pci_io);
543 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
544 DEBUGF("PCI AutoConfig: Found PowerPC device\n");
547 pciauto_setup_device(hose, dev, 6, pci_mem,
548 pci_prefetch, pci_io);