2 * arch/powerpc/kernel/pci_auto.c
4 * PCI autoconfiguration library
6 * Author: Matt Porter <mporter@mvista.com>
8 * Copyright 2000 MontaVista Software Inc.
10 * SPDX-License-Identifier: GPL-2.0+
17 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
18 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
19 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
26 void pciauto_region_init(struct pci_region *res)
29 * Avoid allocating PCI resources from address 0 -- this is illegal
30 * according to PCI 2.1 and moreover, this is known to cause Linux IDE
31 * drivers to fail. Use a reasonable starting value of 0x1000 instead.
33 res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
36 void pciauto_region_align(struct pci_region *res, pci_size_t size)
38 res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
41 int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
51 addr = ((res->bus_lower - 1) | (size - 1)) + 1;
53 if (addr - res->bus_start + size > res->size) {
54 debug("No room in resource");
58 res->bus_lower = addr + size;
60 debug("address=0x%llx bus_lower=0x%llx", (unsigned long long)addr,
61 (unsigned long long)res->bus_lower);
67 *bar = (pci_addr_t)-1;
75 void pciauto_setup_device(struct pci_controller *hose,
76 pci_dev_t dev, int bars_num,
77 struct pci_region *mem,
78 struct pci_region *prefetch,
79 struct pci_region *io)
87 #ifndef CONFIG_PCI_ENUM_ONLY
89 struct pci_region *bar_res;
93 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
94 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
96 for (bar = PCI_BASE_ADDRESS_0;
97 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
98 /* Tickle the BAR and get the response */
99 #ifndef CONFIG_PCI_ENUM_ONLY
100 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
102 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
104 /* If BAR is not implemented go to the next BAR */
108 #ifndef CONFIG_PCI_ENUM_ONLY
112 /* Check the BAR type and set our address mask */
113 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
114 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
116 #ifndef CONFIG_PCI_ENUM_ONLY
120 debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
121 bar_nr, (unsigned long long)bar_size);
123 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
124 PCI_BASE_ADDRESS_MEM_TYPE_64) {
125 u32 bar_response_upper;
128 #ifndef CONFIG_PCI_ENUM_ONLY
129 pci_hose_write_config_dword(hose, dev, bar + 4,
132 pci_hose_read_config_dword(hose, dev, bar + 4,
133 &bar_response_upper);
135 bar64 = ((u64)bar_response_upper << 32) | bar_response;
137 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
138 #ifndef CONFIG_PCI_ENUM_ONLY
142 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
144 #ifndef CONFIG_PCI_ENUM_ONLY
145 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
151 debug("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ",
152 bar_nr, (unsigned long long)bar_size);
155 #ifndef CONFIG_PCI_ENUM_ONLY
156 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
157 /* Write it out and update our limit */
158 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
162 #ifdef CONFIG_SYS_PCI_64BIT
163 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
166 * If we are a 64-bit decoder then increment to the
167 * upper 32 bits of the bar and force it to locate
168 * in the lower 4GB of memory.
170 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
176 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
177 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
184 /* Configure the expansion ROM address */
185 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
186 if (header_type != PCI_HEADER_TYPE_CARDBUS) {
187 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
188 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
189 pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
190 pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
192 bar_size = -(bar_response & ~1);
193 debug("PCI Autoconfig: ROM, size=%#x, ",
194 (unsigned int)bar_size);
195 if (pciauto_region_allocate(mem, bar_size,
197 pci_hose_write_config_dword(hose, dev, rom_addr,
200 cmdstat |= PCI_COMMAND_MEMORY;
205 pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
206 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
207 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
208 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
211 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
212 pci_dev_t dev, int sub_bus)
214 struct pci_region *pci_mem;
215 struct pci_region *pci_prefetch;
216 struct pci_region *pci_io;
217 u16 cmdstat, prefechable_64;
220 /* The root controller has the region information */
221 struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
223 pci_mem = ctlr_hose->pci_mem;
224 pci_prefetch = ctlr_hose->pci_prefetch;
225 pci_io = ctlr_hose->pci_io;
227 pci_mem = hose->pci_mem;
228 pci_prefetch = hose->pci_prefetch;
229 pci_io = hose->pci_io;
232 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
233 pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
235 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
237 /* Configure bus number registers */
239 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
240 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
242 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
243 PCI_BUS(dev) - hose->first_busno);
244 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
245 sub_bus - hose->first_busno);
247 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
250 /* Round memory allocator to 1MB boundary */
251 pciauto_region_align(pci_mem, 0x100000);
253 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
254 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
255 (pci_mem->bus_lower & 0xfff00000) >> 16);
257 cmdstat |= PCI_COMMAND_MEMORY;
261 /* Round memory allocator to 1MB boundary */
262 pciauto_region_align(pci_prefetch, 0x100000);
264 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
265 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
266 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
267 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
268 #ifdef CONFIG_SYS_PCI_64BIT
269 pci_hose_write_config_dword(hose, dev,
270 PCI_PREF_BASE_UPPER32,
271 pci_prefetch->bus_lower >> 32);
273 pci_hose_write_config_dword(hose, dev,
274 PCI_PREF_BASE_UPPER32,
278 cmdstat |= PCI_COMMAND_MEMORY;
280 /* We don't support prefetchable memory for now, so disable */
281 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
282 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
283 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
284 pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
285 pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
290 /* Round I/O allocator to 4KB boundary */
291 pciauto_region_align(pci_io, 0x1000);
293 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
294 (pci_io->bus_lower & 0x0000f000) >> 8);
295 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
296 (pci_io->bus_lower & 0xffff0000) >> 16);
298 cmdstat |= PCI_COMMAND_IO;
301 /* Enable memory and I/O accesses, enable bus master */
302 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
303 cmdstat | PCI_COMMAND_MASTER);
306 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
307 pci_dev_t dev, int sub_bus)
309 struct pci_region *pci_mem;
310 struct pci_region *pci_prefetch;
311 struct pci_region *pci_io;
314 /* The root controller has the region information */
315 struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
317 pci_mem = ctlr_hose->pci_mem;
318 pci_prefetch = ctlr_hose->pci_prefetch;
319 pci_io = ctlr_hose->pci_io;
321 pci_mem = hose->pci_mem;
322 pci_prefetch = hose->pci_prefetch;
323 pci_io = hose->pci_io;
326 /* Configure bus number registers */
328 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
330 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
331 sub_bus - hose->first_busno);
335 /* Round memory allocator to 1MB boundary */
336 pciauto_region_align(pci_mem, 0x100000);
338 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
339 (pci_mem->bus_lower - 1) >> 16);
345 pci_hose_read_config_word(hose, dev,
346 PCI_PREF_MEMORY_LIMIT,
348 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
350 /* Round memory allocator to 1MB boundary */
351 pciauto_region_align(pci_prefetch, 0x100000);
353 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
354 (pci_prefetch->bus_lower - 1) >> 16);
355 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
356 #ifdef CONFIG_SYS_PCI_64BIT
357 pci_hose_write_config_dword(hose, dev,
358 PCI_PREF_LIMIT_UPPER32,
359 (pci_prefetch->bus_lower - 1) >> 32);
361 pci_hose_write_config_dword(hose, dev,
362 PCI_PREF_LIMIT_UPPER32,
368 /* Round I/O allocator to 4KB boundary */
369 pciauto_region_align(pci_io, 0x1000);
371 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
372 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
373 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
374 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
382 void pciauto_config_init(struct pci_controller *hose)
386 hose->pci_io = hose->pci_mem = hose->pci_prefetch = NULL;
388 for (i = 0; i < hose->region_count; i++) {
389 switch(hose->regions[i].flags) {
392 hose->pci_io->size < hose->regions[i].size)
393 hose->pci_io = hose->regions + i;
396 if (!hose->pci_mem ||
397 hose->pci_mem->size < hose->regions[i].size)
398 hose->pci_mem = hose->regions + i;
400 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
401 if (!hose->pci_prefetch ||
402 hose->pci_prefetch->size < hose->regions[i].size)
403 hose->pci_prefetch = hose->regions + i;
410 pciauto_region_init(hose->pci_mem);
412 debug("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
413 "\t\tPhysical Memory [%llx-%llxx]\n",
414 (u64)hose->pci_mem->bus_start,
415 (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
416 (u64)hose->pci_mem->phys_start,
417 (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
420 if (hose->pci_prefetch) {
421 pciauto_region_init(hose->pci_prefetch);
423 debug("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
424 "\t\tPhysical Memory [%llx-%llx]\n",
425 (u64)hose->pci_prefetch->bus_start,
426 (u64)(hose->pci_prefetch->bus_start +
427 hose->pci_prefetch->size - 1),
428 (u64)hose->pci_prefetch->phys_start,
429 (u64)(hose->pci_prefetch->phys_start +
430 hose->pci_prefetch->size - 1));
434 pciauto_region_init(hose->pci_io);
436 debug("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
437 "\t\tPhysical Memory: [%llx-%llx]\n",
438 (u64)hose->pci_io->bus_start,
439 (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
440 (u64)hose->pci_io->phys_start,
441 (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
447 * HJF: Changed this to return int. I think this is required
448 * to get the correct result when scanning bridges
450 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
452 struct pci_region *pci_mem;
453 struct pci_region *pci_prefetch;
454 struct pci_region *pci_io;
455 unsigned int sub_bus = PCI_BUS(dev);
456 unsigned short class;
460 /* The root controller has the region information */
461 struct pci_controller *ctlr_hose = pci_bus_to_hose(0);
463 pci_mem = ctlr_hose->pci_mem;
464 pci_prefetch = ctlr_hose->pci_prefetch;
465 pci_io = ctlr_hose->pci_io;
467 pci_mem = hose->pci_mem;
468 pci_prefetch = hose->pci_prefetch;
469 pci_io = hose->pci_io;
472 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
475 case PCI_CLASS_BRIDGE_PCI:
476 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
479 pciauto_setup_device(hose, dev, 2, pci_mem,
480 pci_prefetch, pci_io);
483 n = dm_pci_hose_probe_bus(hose, dev);
486 sub_bus = (unsigned int)n;
488 /* Passing in current_busno allows for sibling P2P bridges */
489 hose->current_busno++;
490 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
492 * need to figure out if this is a subordinate bridge on the bus
493 * to be able to properly set the pri/sec/sub bridge registers.
495 n = pci_hose_scan_bus(hose, hose->current_busno);
497 /* figure out the deepest we've gone for this leg */
498 sub_bus = max((unsigned int)n, sub_bus);
499 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
501 sub_bus = hose->current_busno;
505 case PCI_CLASS_BRIDGE_CARDBUS:
507 * just do a minimal setup of the bridge,
508 * let the OS take care of the rest
510 pciauto_setup_device(hose, dev, 0, pci_mem,
511 pci_prefetch, pci_io);
513 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
516 #ifndef CONFIG_DM_PCI
517 hose->current_busno++;
521 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
522 case PCI_CLASS_BRIDGE_OTHER:
523 debug("PCI Autoconfig: Skipping bridge device %d\n",
527 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
528 case PCI_CLASS_BRIDGE_OTHER:
530 * The host/PCI bridge 1 seems broken in 8349 - it presents
531 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
532 * device claiming resources io/mem/irq.. we only allow for
533 * the PIMMR window to be allocated (BAR0 - 1MB size)
535 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
536 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
537 hose->pci_prefetch, hose->pci_io);
541 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
542 debug("PCI AutoConfig: Found PowerPC device\n");
545 pciauto_setup_device(hose, dev, 6, pci_mem,
546 pci_prefetch, pci_io);