2 * Copyright 2014-2015 Freescale Semiconductor, Inc.
3 * Layerscape PCIe driver
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/fsl_serdes.h>
14 #ifndef CONFIG_LS102XA
15 #include <asm/arch/fdt.h>
16 #include <asm/arch/soc.h>
19 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
20 #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
23 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
24 #define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
27 #ifndef CONFIG_SYS_PCI_MEMORY_SIZE
28 #define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */
31 #ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
32 #define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
36 #define PCIE_ATU_VIEWPORT 0x900
37 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
38 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
39 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
40 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
41 #define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
42 #define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
43 #define PCIE_ATU_CR1 0x904
44 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
45 #define PCIE_ATU_TYPE_IO (0x2 << 0)
46 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
47 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
48 #define PCIE_ATU_CR2 0x908
49 #define PCIE_ATU_ENABLE (0x1 << 31)
50 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
51 #define PCIE_ATU_BAR_NUM(bar) ((bar) << 8)
52 #define PCIE_ATU_LOWER_BASE 0x90C
53 #define PCIE_ATU_UPPER_BASE 0x910
54 #define PCIE_ATU_LIMIT 0x914
55 #define PCIE_ATU_LOWER_TARGET 0x918
56 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
57 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
58 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
59 #define PCIE_ATU_UPPER_TARGET 0x91C
61 #define PCIE_DBI_RO_WR_EN 0x8bc
63 #define PCIE_LINK_CAP 0x7c
64 #define PCIE_LINK_SPEED_MASK 0xf
65 #define PCIE_LINK_STA 0x82
67 #define LTSSM_STATE_MASK 0x3f
68 #define LTSSM_PCIE_L0 0x11 /* L0 state */
70 #define PCIE_DBI_SIZE 0x100000 /* 1M */
72 #define PCIE_LCTRL0_CFG2_ENABLE (1 << 31)
73 #define PCIE_LCTRL0_VF(vf) ((vf) << 22)
74 #define PCIE_LCTRL0_PF(pf) ((pf) << 16)
75 #define PCIE_LCTRL0_VF_ACTIVE (1 << 21)
76 #define PCIE_LCTRL0_VAL(pf, vf) (PCIE_LCTRL0_PF(pf) | \
77 PCIE_LCTRL0_VF(vf) | \
78 ((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \
79 PCIE_LCTRL0_CFG2_ENABLE)
81 #define PCIE_NO_SRIOV_BAR_BASE 0x1000
84 #define PCIE_VF_NUM 64
86 #define PCIE_BAR0_SIZE (4 * 1024) /* 4K */
87 #define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */
88 #define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
89 #define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
94 void __iomem *va_cfg0;
95 void __iomem *va_cfg1;
97 struct pci_controller hose;
100 struct ls_pcie_info {
116 #define SET_LS_PCIE_INFO(x, num) \
118 x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
119 x.phys_base = CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
120 x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF + \
121 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
122 x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE; \
123 x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF + \
124 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
125 x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE; \
126 x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS; \
127 x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF + \
128 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
129 x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE; \
130 x.io_bus = CONFIG_SYS_PCIE_IO_BUS; \
131 x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF + \
132 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
133 x.io_size = CONFIG_SYS_PCIE_IO_SIZE; \
137 #ifdef CONFIG_LS102XA
138 #include <asm/arch/immap_ls102xa.h>
140 /* PEX1/2 Misc Ports Status Register */
141 #define LTSSM_STATE_SHIFT 20
143 static int ls_pcie_link_state(struct ls_pcie *pcie)
146 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
148 state = in_be32(&scfg->pexmscportsr[pcie->idx]);
149 state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
150 if (state < LTSSM_PCIE_L0) {
151 debug("....PCIe link error. LTSSM=0x%02x.\n", state);
158 static int ls_pcie_link_state(struct ls_pcie *pcie)
162 state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
164 if (state < LTSSM_PCIE_L0) {
165 debug("....PCIe link error. LTSSM=0x%02x.\n", state);
173 static int ls_pcie_link_up(struct ls_pcie *pcie)
178 state = ls_pcie_link_state(pcie);
182 /* Try to download speed to gen1 */
183 cap = readl(pcie->dbi + PCIE_LINK_CAP);
184 writel((cap & (~PCIE_LINK_SPEED_MASK)) | 1, pcie->dbi + PCIE_LINK_CAP);
186 * Notice: the following delay has critical impact on link training
187 * if too short (<30ms) the link doesn't get up.
190 state = ls_pcie_link_state(pcie);
194 writel(cap, pcie->dbi + PCIE_LINK_CAP);
199 static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
201 writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
202 pcie->dbi + PCIE_ATU_VIEWPORT);
203 writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
206 static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
208 writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
209 pcie->dbi + PCIE_ATU_VIEWPORT);
210 writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
213 static void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
214 u64 phys, u64 bus_addr, pci_size_t size)
216 writel(PCIE_ATU_REGION_OUTBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
217 writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_BASE);
218 writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_BASE);
219 writel(phys + size - 1, pcie->dbi + PCIE_ATU_LIMIT);
220 writel((u32)bus_addr, pcie->dbi + PCIE_ATU_LOWER_TARGET);
221 writel(bus_addr >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
222 writel(type, pcie->dbi + PCIE_ATU_CR1);
223 writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2);
226 /* Use bar match mode and MEM type as default */
227 static void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx,
230 writel(PCIE_ATU_REGION_INBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
231 writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_TARGET);
232 writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
233 writel(PCIE_ATU_TYPE_MEM, pcie->dbi + PCIE_ATU_CR1);
234 writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
235 PCIE_ATU_BAR_NUM(bar), pcie->dbi + PCIE_ATU_CR2);
238 static void ls_pcie_setup_atu(struct ls_pcie *pcie, struct ls_pcie_info *info)
244 /* ATU 0 : OUTBOUND : CFG0 */
245 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
250 /* ATU 1 : OUTBOUND : CFG1 */
251 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
256 /* ATU 2 : OUTBOUND : MEM */
257 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX2,
262 /* ATU 3 : OUTBOUND : IO */
263 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX3,
270 for (i = 0; i <= PCIE_ATU_REGION_INDEX3; i++) {
271 writel(PCIE_ATU_REGION_OUTBOUND | i,
272 pcie->dbi + PCIE_ATU_VIEWPORT);
273 debug("iATU%d:\n", i);
274 debug("\tLOWER PHYS 0x%08x\n",
275 readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
276 debug("\tUPPER PHYS 0x%08x\n",
277 readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
278 debug("\tLOWER BUS 0x%08x\n",
279 readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
280 debug("\tUPPER BUS 0x%08x\n",
281 readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
282 debug("\tLIMIT 0x%08x\n",
283 readl(pcie->dbi + PCIE_ATU_LIMIT));
284 debug("\tCR1 0x%08x\n",
285 readl(pcie->dbi + PCIE_ATU_CR1));
286 debug("\tCR2 0x%08x\n",
287 readl(pcie->dbi + PCIE_ATU_CR2));
292 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
294 /* Do not skip controller */
298 static int ls_pcie_addr_valid(struct pci_controller *hose, pci_dev_t d)
303 /* Controller does not support multi-function in RC mode */
304 if ((PCI_BUS(d) == hose->first_busno) && (PCI_FUNC(d) > 0))
310 static int ls_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
313 struct ls_pcie *pcie = hose->priv_data;
316 if (ls_pcie_addr_valid(hose, d)) {
321 if (PCI_BUS(d) == hose->first_busno) {
322 addr = pcie->dbi + (where & ~0x3);
324 busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
325 PCIE_ATU_DEV(PCI_DEV(d)) |
326 PCIE_ATU_FUNC(PCI_FUNC(d));
328 if (PCI_BUS(d) == hose->first_busno + 1) {
329 ls_pcie_cfg0_set_busdev(pcie, busdev);
330 addr = pcie->va_cfg0 + (where & ~0x3);
332 ls_pcie_cfg1_set_busdev(pcie, busdev);
333 addr = pcie->va_cfg1 + (where & ~0x3);
342 static int ls_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
345 struct ls_pcie *pcie = hose->priv_data;
348 if (ls_pcie_addr_valid(hose, d))
351 if (PCI_BUS(d) == hose->first_busno) {
352 addr = pcie->dbi + (where & ~0x3);
354 busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
355 PCIE_ATU_DEV(PCI_DEV(d)) |
356 PCIE_ATU_FUNC(PCI_FUNC(d));
358 if (PCI_BUS(d) == hose->first_busno + 1) {
359 ls_pcie_cfg0_set_busdev(pcie, busdev);
360 addr = pcie->va_cfg0 + (where & ~0x3);
362 ls_pcie_cfg1_set_busdev(pcie, busdev);
363 addr = pcie->va_cfg1 + (where & ~0x3);
372 static void ls_pcie_setup_ctrl(struct ls_pcie *pcie,
373 struct ls_pcie_info *info)
375 struct pci_controller *hose = &pcie->hose;
376 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
378 ls_pcie_setup_atu(pcie, info);
380 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0);
382 /* program correct class for RC */
383 writel(1, pcie->dbi + PCIE_DBI_RO_WR_EN);
384 pci_hose_write_config_word(hose, dev, PCI_CLASS_DEVICE,
385 PCI_CLASS_BRIDGE_PCI);
386 #ifndef CONFIG_LS102XA
387 writel(0, pcie->dbi + PCIE_DBI_RO_WR_EN);
391 static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie,
392 struct ls_pcie_info *info)
394 u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
396 /* ATU 0 : INBOUND : map BAR0 */
397 ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX0, 0, phys);
398 /* ATU 1 : INBOUND : map BAR1 */
399 phys += PCIE_BAR1_SIZE;
400 ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX1, 1, phys);
401 /* ATU 2 : INBOUND : map BAR2 */
402 phys += PCIE_BAR2_SIZE;
403 ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX2, 2, phys);
404 /* ATU 3 : INBOUND : map BAR4 */
405 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
406 ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX3, 4, phys);
408 /* ATU 0 : OUTBOUND : map 4G MEM */
409 ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
413 4 * 1024 * 1024 * 1024ULL);
416 /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
417 static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
424 writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
427 writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
430 writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
431 writel(0, bar_base + PCI_BASE_ADDRESS_3);
434 writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
435 writel(0, bar_base + PCI_BASE_ADDRESS_5);
442 static void ls_pcie_ep_setup_bars(void *bar_base)
444 /* BAR0 - 32bit - 4K configuration */
445 ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
446 /* BAR1 - 32bit - 8K MSIX*/
447 ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
448 /* BAR2 - 64bit - 4K MEM desciptor */
449 ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
450 /* BAR4 - 64bit - 1M MEM*/
451 ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
454 static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info)
456 struct pci_controller *hose = &pcie->hose;
457 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
460 sriov = pci_hose_find_ext_capability(hose, dev, PCI_EXT_CAP_ID_SRIOV);
464 for (pf = 0; pf < PCIE_PF_NUM; pf++) {
465 for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
466 #ifndef CONFIG_LS102XA
467 writel(PCIE_LCTRL0_VAL(pf, vf),
468 pcie->dbi + PCIE_LUT_BASE +
471 ls_pcie_ep_setup_bars(pcie->dbi);
472 ls_pcie_ep_setup_atu(pcie, info);
477 #ifndef CONFIG_LS102XA
478 writel(0, pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0);
481 ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
482 ls_pcie_ep_setup_atu(pcie, info);
486 #ifdef CONFIG_FSL_LSCH3
488 * Return next available LUT index.
490 static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
492 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
493 return pcie->next_lut_index++;
495 return -1; /* LUT is full */
499 * Program a single LUT entry
501 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
506 lut = pcie->dbi + PCIE_LUT_BASE;
508 /* leave mask as all zeroes, want to match all bits */
509 writel((devid << 16), lut + PCIE_LUT_UDR(index));
510 writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index));
513 /* returns the next available streamid */
514 static u32 ls_pcie_next_streamid(void)
516 static int next_stream_id = FSL_PEX_STREAM_ID_START;
518 if (next_stream_id > FSL_PEX_STREAM_ID_END)
521 return next_stream_id++;
525 * An msi-map is a property to be added to the pci controller
526 * node. It is a table, where each entry consists of 4 fields
529 * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
530 * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
532 static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
533 u32 devid, u32 streamid)
540 /* find pci controller node */
541 snprintf(pcie_path, sizeof(pcie_path), "/soc/pcie@%llx",
543 nodeoffset = fdt_path_offset(blob, pcie_path);
544 if (nodeoffset < 0) {
545 printf("\n%s: ERROR: unable to update PCIe node: %s\n",
546 __func__, pcie_path);
550 /* get phandle to MSI controller */
551 prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
553 printf("\n%s: ERROR: missing msi-parent: %s\n", __func__,
557 phandle = be32_to_cpu(*prop);
559 /* set one msi-map row */
560 fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
561 fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
562 fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
563 fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
566 static void fdt_fixup_pcie(void *blob)
568 unsigned int found_multi = 0;
569 unsigned char header_type;
575 struct pci_controller *hose;
576 struct ls_pcie *pcie;
579 for (i = 0, hose = pci_get_hose_head(); hose; hose = hose->next, i++) {
580 pcie = hose->priv_data;
581 for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
583 for (dev = PCI_BDF(bus, 0, 0);
584 dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
585 PCI_MAX_PCI_FUNCTIONS - 1);
586 dev += PCI_BDF(0, 0, 1)) {
588 if (PCI_FUNC(dev) && !found_multi)
591 pci_read_config_word(dev, PCI_VENDOR_ID, &id);
593 pci_read_config_byte(dev, PCI_HEADER_TYPE,
596 if ((id == 0xFFFF) || (id == 0x0000))
600 found_multi = header_type & 0x80;
602 streamid = ls_pcie_next_streamid();
603 if (streamid == 0xffffffff) {
604 printf("ERROR: no stream ids free\n");
608 index = ls_pcie_next_lut_index(pcie);
610 printf("ERROR: no LUT indexes free\n");
614 /* the DT fixup must be relative to the hose first_busno */
615 bdf = dev - PCI_BDF(hose->first_busno, 0, 0);
617 /* map PCI b.d.f to streamID in LUT */
618 ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
621 /* update msi-map in device tree */
622 fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
630 int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
632 struct ls_pcie *pcie;
633 struct pci_controller *hose;
634 int num = dev - PCIE1;
635 pci_dev_t pdev = PCI_BDF(busno, 0, 0);
636 int i, linkup, ep_mode;
640 if (!is_serdes_configured(dev)) {
641 printf("PCIe%d: disabled\n", num + 1);
645 pcie = malloc(sizeof(*pcie));
648 memset(pcie, 0, sizeof(*pcie));
651 hose->priv_data = pcie;
652 hose->first_busno = busno;
654 pcie->dbi = map_physmem(info->regs, PCIE_DBI_SIZE, MAP_NOCACHE);
655 pcie->va_cfg0 = map_physmem(info->cfg0_phys,
658 pcie->va_cfg1 = map_physmem(info->cfg1_phys,
661 pcie->next_lut_index = 0;
663 /* outbound memory */
664 pci_set_region(&hose->regions[0],
665 (pci_size_t)info->mem_bus,
666 (phys_size_t)info->mem_phys,
667 (pci_size_t)info->mem_size,
671 pci_set_region(&hose->regions[1],
672 (pci_size_t)info->io_bus,
673 (phys_size_t)info->io_phys,
674 (pci_size_t)info->io_size,
677 /* System memory space */
678 pci_set_region(&hose->regions[2],
679 CONFIG_SYS_PCI_MEMORY_BUS,
680 CONFIG_SYS_PCI_MEMORY_PHYS,
681 CONFIG_SYS_PCI_MEMORY_SIZE,
682 PCI_REGION_SYS_MEMORY);
684 hose->region_count = 3;
686 for (i = 0; i < hose->region_count; i++)
687 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n",
689 (u64)hose->regions[i].phys_start,
690 (u64)hose->regions[i].bus_start,
691 (u64)hose->regions[i].size,
692 hose->regions[i].flags);
695 pci_hose_read_config_byte_via_dword,
696 pci_hose_read_config_word_via_dword,
698 pci_hose_write_config_byte_via_dword,
699 pci_hose_write_config_word_via_dword,
700 ls_pcie_write_config);
702 pci_hose_read_config_byte(hose, pdev, PCI_HEADER_TYPE, &header_type);
703 ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
704 printf("PCIe%u: %s ", info->pci_num,
705 ep_mode ? "Endpoint" : "Root Complex");
708 ls_pcie_setup_ep(pcie, info);
710 ls_pcie_setup_ctrl(pcie, info);
712 linkup = ls_pcie_link_up(pcie);
715 /* Let the user know there's no PCIe link */
716 printf("no link, regs @ 0x%lx\n", info->regs);
717 hose->last_busno = hose->first_busno;
721 /* Print the negotiated PCIe link width */
722 pci_hose_read_config_word(hose, pdev, PCIE_LINK_STA, &temp16);
723 printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
724 (temp16 & 0xf), info->regs);
729 pci_register_hose(hose);
731 hose->last_busno = pci_hose_scan(hose);
733 printf("PCIe%x: Bus %02x - %02x\n",
734 info->pci_num, hose->first_busno, hose->last_busno);
736 return hose->last_busno + 1;
739 int ls_pcie_init_board(int busno)
741 struct ls_pcie_info info;
744 SET_LS_PCIE_INFO(info, 1);
745 busno = ls_pcie_init_ctrl(busno, PCIE1, &info);
749 SET_LS_PCIE_INFO(info, 2);
750 busno = ls_pcie_init_ctrl(busno, PCIE2, &info);
754 SET_LS_PCIE_INFO(info, 3);
755 busno = ls_pcie_init_ctrl(busno, PCIE3, &info);
759 SET_LS_PCIE_INFO(info, 4);
760 busno = ls_pcie_init_ctrl(busno, PCIE4, &info);
766 void pci_init_board(void)
768 ls_pcie_init_board(0);
771 #ifdef CONFIG_OF_BOARD_SETUP
773 #include <fdt_support.h>
775 static void ft_pcie_ls_setup(void *blob, const char *pci_compat,
776 unsigned long ctrl_addr, enum srds_prtcl dev)
780 off = fdt_node_offset_by_compat_reg(blob, pci_compat,
781 (phys_addr_t)ctrl_addr);
785 if (!is_serdes_configured(dev))
786 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
789 void ft_pci_setup(void *blob, bd_t *bd)
792 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1);
796 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
800 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE3_ADDR, PCIE3);
804 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4);
807 #ifdef CONFIG_FSL_LSCH3
808 fdt_fixup_pcie(blob);
813 void ft_pci_setup(void *blob, bd_t *bd)