2 * Copyright 2014-2015 Freescale Semiconductor, Inc.
3 * Layerscape PCIe driver
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/fsl_serdes.h>
13 #ifdef CONFIG_OF_BOARD_SETUP
15 #include <fdt_support.h>
16 #include "pcie_layerscape.h"
18 #ifdef CONFIG_FSL_LSCH3
20 * Return next available LUT index.
22 static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
24 if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
25 return pcie->next_lut_index++;
27 return -ENOSPC; /* LUT is full */
30 /* returns the next available streamid for pcie, -errno if failed */
31 static int ls_pcie_next_streamid(void)
33 static int next_stream_id = FSL_PEX_STREAM_ID_START;
35 if (next_stream_id > FSL_PEX_STREAM_ID_END)
38 return next_stream_id++;
44 #ifdef CONFIG_FSL_LSCH3
46 * Program a single LUT entry
48 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
53 lut = pcie->dbi + PCIE_LUT_BASE;
55 /* leave mask as all zeroes, want to match all bits */
56 writel((devid << 16), lut + PCIE_LUT_UDR(index));
57 writel(streamid | PCIE_LUT_ENABLE, lut + PCIE_LUT_LDR(index));
61 * An msi-map is a property to be added to the pci controller
62 * node. It is a table, where each entry consists of 4 fields
65 * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
66 * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
68 static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
69 u32 devid, u32 streamid)
76 /* find pci controller node */
77 snprintf(pcie_path, sizeof(pcie_path), "/soc/pcie@%llx",
79 nodeoffset = fdt_path_offset(blob, pcie_path);
81 printf("\n%s: ERROR: unable to update PCIe node: %s\n",
86 /* get phandle to MSI controller */
87 prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
89 printf("\n%s: ERROR: missing msi-parent: %s\n", __func__,
93 phandle = fdt32_to_cpu(*prop);
95 /* set one msi-map row */
96 fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
97 fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
98 fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
99 fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
102 static void fdt_fixup_pcie(void *blob)
104 unsigned int found_multi = 0;
105 unsigned char header_type;
111 struct pci_controller *hose;
112 struct ls_pcie *pcie;
115 for (i = 0, hose = pci_get_hose_head(); hose; hose = hose->next, i++) {
116 pcie = hose->priv_data;
117 for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
119 for (dev = PCI_BDF(bus, 0, 0);
120 dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
121 PCI_MAX_PCI_FUNCTIONS - 1);
122 dev += PCI_BDF(0, 0, 1)) {
124 if (PCI_FUNC(dev) && !found_multi)
127 pci_read_config_word(dev, PCI_VENDOR_ID, &id);
129 pci_read_config_byte(dev, PCI_HEADER_TYPE,
132 if ((id == 0xFFFF) || (id == 0x0000))
136 found_multi = header_type & 0x80;
138 streamid = ls_pcie_next_streamid();
140 debug("ERROR: no stream ids free\n");
144 index = ls_pcie_next_lut_index(pcie);
146 debug("ERROR: no LUT indexes free\n");
150 /* the DT fixup must be relative to the hose first_busno */
151 bdf = dev - PCI_BDF(hose->first_busno, 0, 0);
153 /* map PCI b.d.f to streamID in LUT */
154 ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
157 /* update msi-map in device tree */
158 fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
166 static void ft_pcie_ls_setup(void *blob, const char *pci_compat,
167 unsigned long ctrl_addr, enum srds_prtcl dev)
171 off = fdt_node_offset_by_compat_reg(blob, pci_compat,
172 (phys_addr_t)ctrl_addr);
176 if (!is_serdes_configured(dev))
177 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
180 /* Fixup Kernel DT for PCIe */
181 void ft_pci_setup(void *blob, bd_t *bd)
184 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1);
188 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
192 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE3_ADDR, PCIE3);
196 ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4);
199 #ifdef CONFIG_FSL_LSCH3
200 fdt_fixup_pcie(blob);
204 #else /* CONFIG_DM_PCI */
206 #ifdef CONFIG_FSL_LSCH3
207 static void lut_writel(struct ls_pcie *pcie, unsigned int value,
210 if (pcie->big_endian)
211 out_be32(pcie->lut + offset, value);
213 out_le32(pcie->lut + offset, value);
217 * Program a single LUT entry
219 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
222 /* leave mask as all zeroes, want to match all bits */
223 lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
224 lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
228 * An msi-map is a property to be added to the pci controller
229 * node. It is a table, where each entry consists of 4 fields
232 * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
233 * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
235 static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
236 u32 devid, u32 streamid)
242 /* find pci controller node */
243 nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
244 pcie->dbi_res.start);
245 if (nodeoffset < 0) {
246 #ifdef FSL_PCIE_COMPAT /* Compatible with older version of dts node */
247 nodeoffset = fdt_node_offset_by_compat_reg(blob,
248 FSL_PCIE_COMPAT, pcie->dbi_res.start);
256 /* get phandle to MSI controller */
257 prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
259 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
260 __func__, pcie->idx);
263 phandle = fdt32_to_cpu(*prop);
265 /* set one msi-map row */
266 fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
267 fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
268 fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
269 fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
272 static void fdt_fixup_pcie(void *blob)
274 struct udevice *dev, *bus;
275 struct ls_pcie *pcie;
280 /* Scan all known buses */
281 for (pci_find_first_device(&dev);
283 pci_find_next_device(&dev)) {
284 for (bus = dev; device_is_on_pci_bus(bus);)
286 pcie = dev_get_priv(bus);
288 streamid = ls_pcie_next_streamid();
290 debug("ERROR: no stream ids free\n");
294 index = ls_pcie_next_lut_index(pcie);
296 debug("ERROR: no LUT indexes free\n");
300 /* the DT fixup must be relative to the hose first_busno */
301 bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
302 /* map PCI b.d.f to streamID in LUT */
303 ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
305 /* update msi-map in device tree */
306 fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
312 static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
316 off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
317 pcie->dbi_res.start);
319 #ifdef FSL_PCIE_COMPAT /* Compatible with older version of dts node */
320 off = fdt_node_offset_by_compat_reg(blob,
322 pcie->dbi_res.start);
331 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
333 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
336 /* Fixup Kernel DT for PCIe */
337 void ft_pci_setup(void *blob, bd_t *bd)
339 struct ls_pcie *pcie;
341 list_for_each_entry(pcie, &ls_pcie_list, list)
342 ft_pcie_ls_setup(blob, pcie);
344 #ifdef CONFIG_FSL_LSCH3
345 fdt_fixup_pcie(blob);
348 #endif /* CONFIG_DM_PCI */
350 #else /* !CONFIG_OF_BOARD_SETUP */
351 void ft_pci_setup(void *blob, bd_t *bd)