2 * Xilinx AXI Bridge for PCI Express Driver
4 * Copyright (C) 2016 Imagination Technologies
6 * SPDX-License-Identifier: GPL-2.0
16 * struct xilinx_pcie - Xilinx PCIe controller state
17 * @hose: The parent classes PCI controller state
18 * @cfg_base: The base address of memory mapped configuration space
21 struct pci_controller hose;
25 /* Register definitions */
26 #define XILINX_PCIE_REG_PSCR 0x144
27 #define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
30 * pcie_xilinx_link_up() - Check whether the PCIe link is up
31 * @pcie: Pointer to the PCI controller state
33 * Checks whether the PCIe link for the given device is up or down.
35 * Return: true if the link is up, else false
37 static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie)
39 uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR);
41 return pscr & XILINX_PCIE_REG_PSCR_LNKUP;
45 * pcie_xilinx_config_address() - Calculate the address of a config access
46 * @pcie: Pointer to the PCI controller state
47 * @bdf: Identifies the PCIe device to access
48 * @offset: The offset into the device's configuration space
49 * @paddress: Pointer to the pointer to write the calculates address to
51 * Calculates the address that should be accessed to perform a PCIe
52 * configuration space access for a given device identified by the PCIe
53 * controller device @pcie and the bus, device & function numbers in @bdf. If
54 * access to the device is not valid then the function will return an error
55 * code. Otherwise the address to access will be written to the pointer pointed
58 * Return: 0 on success, else -ENODEV
60 static int pcie_xilinx_config_address(struct xilinx_pcie *pcie, pci_dev_t bdf,
61 uint offset, void **paddress)
63 unsigned int bus = PCI_BUS(bdf);
64 unsigned int dev = PCI_DEV(bdf);
65 unsigned int func = PCI_FUNC(bdf);
68 if ((bus > 0) && !pcie_xilinx_link_up(pcie))
72 * Busses 0 (host-PCIe bridge) & 1 (its immediate child) are
73 * limited to a single device each.
75 if ((bus < 2) && (dev > 0))
78 addr = pcie->cfg_base;
89 * pcie_xilinx_read_config() - Read from configuration space
90 * @pcie: Pointer to the PCI controller state
91 * @bdf: Identifies the PCIe device to access
92 * @offset: The offset into the device's configuration space
93 * @valuep: A pointer at which to store the read value
94 * @size: Indicates the size of access to perform
96 * Read a value of size @size from offset @offset within the configuration
97 * space of the device identified by the bus, device & function numbers in @bdf
98 * on the PCI bus @bus.
100 * Return: 0 on success, else -ENODEV or -EINVAL
102 static int pcie_xilinx_read_config(struct udevice *bus, pci_dev_t bdf,
103 uint offset, ulong *valuep,
104 enum pci_size_t size)
106 struct xilinx_pcie *pcie = dev_get_priv(bus);
110 err = pcie_xilinx_config_address(pcie, bdf, offset, &address);
112 *valuep = pci_get_ff(size);
118 *valuep = __raw_readb(address);
121 *valuep = __raw_readw(address);
124 *valuep = __raw_readl(address);
132 * pcie_xilinx_write_config() - Write to configuration space
133 * @pcie: Pointer to the PCI controller state
134 * @bdf: Identifies the PCIe device to access
135 * @offset: The offset into the device's configuration space
136 * @value: The value to write
137 * @size: Indicates the size of access to perform
139 * Write the value @value of size @size from offset @offset within the
140 * configuration space of the device identified by the bus, device & function
141 * numbers in @bdf on the PCI bus @bus.
143 * Return: 0 on success, else -ENODEV or -EINVAL
145 static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf,
146 uint offset, ulong value,
147 enum pci_size_t size)
149 struct xilinx_pcie *pcie = dev_get_priv(bus);
153 err = pcie_xilinx_config_address(pcie, bdf, offset, &address);
159 __raw_writeb(value, address);
162 __raw_writew(value, address);
165 __raw_writel(value, address);
173 * pcie_xilinx_ofdata_to_platdata() - Translate from DT to device state
174 * @dev: A pointer to the device being operated on
176 * Translate relevant data from the device tree pertaining to device @dev into
177 * state that the driver will later make use of. This state is stored in the
178 * device's private data structure.
180 * Return: 0 on success, else -EINVAL
182 static int pcie_xilinx_ofdata_to_platdata(struct udevice *dev)
184 struct xilinx_pcie *pcie = dev_get_priv(dev);
185 struct fdt_resource reg_res;
186 DECLARE_GLOBAL_DATA_PTR;
189 err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
192 error("\"reg\" resource not found\n");
196 pcie->cfg_base = map_physmem(reg_res.start,
197 fdt_resource_size(®_res),
203 static const struct dm_pci_ops pcie_xilinx_ops = {
204 .read_config = pcie_xilinx_read_config,
205 .write_config = pcie_xilinx_write_config,
208 static const struct udevice_id pcie_xilinx_ids[] = {
209 { .compatible = "xlnx,axi-pcie-host-1.00.a" },
213 U_BOOT_DRIVER(pcie_xilinx) = {
214 .name = "pcie_xilinx",
216 .of_match = pcie_xilinx_ids,
217 .ops = &pcie_xilinx_ops,
218 .ofdata_to_platdata = pcie_xilinx_ofdata_to_platdata,
219 .priv_auto_alloc_size = sizeof(struct xilinx_pcie),