2 * Allwinner sun4i USB PHY driver
4 * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
5 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
6 * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
8 * Modelled arch/arm/mach-sunxi/usb_phy.c to compatible with generic-phy.
10 * SPDX-License-Identifier: GPL-2.0+
15 #include <dm/device.h>
16 #include <generic-phy.h>
17 #include <phy-sun4i-usb.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/cpu.h>
24 #define REG_PHYCTL_A10 0x04
25 #define REG_PHYBIST 0x08
26 #define REG_PHYTUNE 0x0c
27 #define REG_PHYCTL_A33 0x10
28 #define REG_PHY_OTGCTL 0x20
29 #define REG_PMU_UNK1 0x10
31 /* Common Control Bits for Both PHYs */
32 #define PHY_PLL_BW 0x03
33 #define PHY_RES45_CAL_EN 0x0c
35 /* Private Control Bits for Each PHY */
36 #define PHY_TX_AMPLITUDE_TUNE 0x20
37 #define PHY_TX_SLEWRATE_TUNE 0x22
38 #define PHY_DISCON_TH_SEL 0x2a
40 #define PHYCTL_DATA BIT(7)
41 #define OTGCTL_ROUTE_MUSB BIT(0)
43 #define PHY_TX_RATE BIT(4)
44 #define PHY_TX_MAGNITUDE BIT(2)
45 #define PHY_TX_AMPLITUDE_LEN 5
47 #define PHY_RES45_CAL_DATA BIT(0)
48 #define PHY_RES45_CAL_LEN 1
49 #define PHY_DISCON_TH_LEN 2
51 #define SUNXI_AHB_ICHR8_EN BIT(10)
52 #define SUNXI_AHB_INCR4_BURST_EN BIT(9)
53 #define SUNXI_AHB_INCRX_ALIGN_EN BIT(8)
54 #define SUNXI_ULPI_BYPASS_EN BIT(0)
56 /* A83T specific control bits for PHY0 */
57 #define PHY_CTL_VBUSVLDEXT BIT(5)
58 #define PHY_CTL_SIDDQ BIT(3)
60 /* A83T specific control bits for PHY2 HSIC */
61 #define SUNXI_EHCI_HS_FORCE BIT(20)
62 #define SUNXI_HSIC_CONNECT_INT BIT(16)
63 #define SUNXI_HSIC BIT(1)
67 enum sun4i_usb_phy_type {
77 struct sun4i_usb_phy_cfg {
79 enum sun4i_usb_phy_type type;
86 struct sun4i_usb_phy_info {
87 const char *gpio_vbus;
88 const char *gpio_vbus_det;
89 const char *gpio_id_det;
93 .gpio_vbus = CONFIG_USB0_VBUS_PIN,
94 .gpio_vbus_det = CONFIG_USB0_VBUS_DET,
95 .gpio_id_det = CONFIG_USB0_ID_DET,
96 .rst_mask = (CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK),
99 .gpio_vbus = CONFIG_USB1_VBUS_PIN,
100 .gpio_vbus_det = NULL,
102 .rst_mask = (CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK),
105 .gpio_vbus = CONFIG_USB2_VBUS_PIN,
106 .gpio_vbus_det = NULL,
108 #ifdef CONFIG_MACH_SUN8I_A83T
109 .rst_mask = (CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |
110 CCM_USB_CTRL_12M_CLK),
112 .rst_mask = (CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK),
116 .gpio_vbus = CONFIG_USB3_VBUS_PIN,
117 .gpio_vbus_det = NULL,
119 #ifdef CONFIG_MACH_SUN6I
120 .rst_mask = (CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK),
125 struct sun4i_usb_phy_plat {
135 struct sun4i_usb_phy_data {
137 struct sunxi_ccm_reg *ccm;
138 const struct sun4i_usb_phy_cfg *cfg;
139 struct sun4i_usb_phy_plat *usb_phy;
142 static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
144 static void sun4i_usb_phy_write(struct phy *phy, u32 addr, u32 data, int len)
146 struct sun4i_usb_phy_data *phy_data = dev_get_priv(phy->dev);
147 struct sun4i_usb_phy_plat *usb_phy = &phy_data->usb_phy[phy->id];
148 u32 temp, usbc_bit = BIT(usb_phy->id * 2);
149 void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
152 if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
153 /* SoCs newer than A33 need us to set phyctl to 0 explicitly */
157 for (i = 0; i < len; i++) {
158 temp = readl(phyctl);
160 /* clear the address portion */
161 temp &= ~(0xff << 8);
163 /* set the address */
164 temp |= ((addr + i) << 8);
165 writel(temp, phyctl);
167 /* set the data bit and clear usbc bit*/
168 temp = readb(phyctl);
172 temp &= ~PHYCTL_DATA;
174 writeb(temp, phyctl);
177 temp = readb(phyctl);
179 writeb(temp, phyctl);
181 temp = readb(phyctl);
183 writeb(temp, phyctl);
189 static void sun4i_usb_phy_passby(struct phy *phy, bool enable)
191 struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
192 struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
198 bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
199 SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
201 /* A83T USB2 is HSIC */
202 if (data->cfg->type == sun8i_a83t_phy && usb_phy->id == 2)
203 bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
206 reg_value = readl(usb_phy->pmu);
213 writel(reg_value, usb_phy->pmu);
216 static int sun4i_usb_phy_power_on(struct phy *phy)
218 struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
219 struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
221 if (initial_usb_scan_delay) {
222 mdelay(initial_usb_scan_delay);
223 initial_usb_scan_delay = 0;
226 usb_phy->power_on_count++;
227 if (usb_phy->power_on_count != 1)
230 if (usb_phy->gpio_vbus >= 0)
231 gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP);
236 static int sun4i_usb_phy_power_off(struct phy *phy)
238 struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
239 struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
241 usb_phy->power_on_count--;
242 if (usb_phy->power_on_count != 0)
245 if (usb_phy->gpio_vbus >= 0)
246 gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE);
251 static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, bool id_det)
255 regval = readl(data->base + REG_PHY_OTGCTL);
257 /* Host mode. Route phy0 to EHCI/OHCI */
258 regval &= ~OTGCTL_ROUTE_MUSB;
260 /* Peripheral mode. Route phy0 to MUSB */
261 regval |= OTGCTL_ROUTE_MUSB;
263 writel(regval, data->base + REG_PHY_OTGCTL);
266 static int sun4i_usb_phy_init(struct phy *phy)
268 struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
269 struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
272 setbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
274 if (data->cfg->type == sun8i_a83t_phy) {
276 val = readl(data->base + data->cfg->phyctl_offset);
277 val |= PHY_CTL_VBUSVLDEXT;
278 val &= ~PHY_CTL_SIDDQ;
279 writel(val, data->base + data->cfg->phyctl_offset);
282 if (usb_phy->pmu && data->cfg->enable_pmu_unk1) {
283 val = readl(usb_phy->pmu + REG_PMU_UNK1);
284 writel(val & ~2, usb_phy->pmu + REG_PMU_UNK1);
287 if (usb_phy->id == 0)
288 sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
292 /* Adjust PHY's magnitude and rate */
293 sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE,
294 PHY_TX_MAGNITUDE | PHY_TX_RATE,
295 PHY_TX_AMPLITUDE_LEN);
297 /* Disconnect threshold adjustment */
298 sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
299 data->cfg->disc_thresh, PHY_DISCON_TH_LEN);
302 if (usb_phy->id != 0)
303 sun4i_usb_phy_passby(phy, true);
305 sun4i_usb_phy0_reroute(data, true);
310 static int sun4i_usb_phy_exit(struct phy *phy)
312 struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
313 struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
316 if (data->cfg->type == sun8i_a83t_phy) {
317 void __iomem *phyctl = data->base +
318 data->cfg->phyctl_offset;
320 writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
324 sun4i_usb_phy_passby(phy, false);
326 clrbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
331 static int sun4i_usb_phy_xlate(struct phy *phy,
332 struct ofnode_phandle_args *args)
334 struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
336 if (args->args_count >= data->cfg->num_phys)
339 if (args->args_count)
340 phy->id = args->args[0];
344 debug("%s: phy_id = %ld\n", __func__, phy->id);
348 int sun4i_usb_phy_vbus_detect(struct phy *phy)
350 struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
351 struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
352 int err, retries = 3;
354 debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
356 if (usb_phy->gpio_vbus_det < 0)
357 return usb_phy->gpio_vbus_det;
359 err = gpio_get_value(usb_phy->gpio_vbus_det);
361 * Vbus may have been provided by the board and just been turned of
362 * some milliseconds ago on reset, what we're measuring then is a
363 * residual charge on Vbus, sleep a bit and try again.
365 while (err > 0 && retries--) {
367 err = gpio_get_value(usb_phy->gpio_vbus_det);
373 int sun4i_usb_phy_id_detect(struct phy *phy)
375 struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
376 struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
378 debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
380 if (usb_phy->gpio_id_det < 0)
381 return usb_phy->gpio_id_det;
383 return gpio_get_value(usb_phy->gpio_id_det);
386 static struct phy_ops sun4i_usb_phy_ops = {
387 .of_xlate = sun4i_usb_phy_xlate,
388 .init = sun4i_usb_phy_init,
389 .power_on = sun4i_usb_phy_power_on,
390 .power_off = sun4i_usb_phy_power_off,
391 .exit = sun4i_usb_phy_exit,
394 static int sun4i_usb_phy_probe(struct udevice *dev)
396 struct sun4i_usb_phy_plat *plat = dev_get_platdata(dev);
397 struct sun4i_usb_phy_data *data = dev_get_priv(dev);
400 data->cfg = (const struct sun4i_usb_phy_cfg *)dev_get_driver_data(dev);
404 data->base = (void __iomem *)devfdt_get_addr_name(dev, "phy_ctrl");
405 if (IS_ERR(data->base))
406 return PTR_ERR(data->base);
408 data->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
409 if (IS_ERR(data->ccm))
410 return PTR_ERR(data->ccm);
412 data->usb_phy = plat;
413 for (i = 0; i < data->cfg->num_phys; i++) {
414 struct sun4i_usb_phy_plat *phy = &plat[i];
415 struct sun4i_usb_phy_info *info = &phy_info[i];
418 phy->gpio_vbus = sunxi_name_to_gpio(info->gpio_vbus);
419 if (phy->gpio_vbus >= 0) {
420 ret = gpio_request(phy->gpio_vbus, "usb_vbus");
423 ret = gpio_direction_output(phy->gpio_vbus, 0);
428 phy->gpio_vbus_det = sunxi_name_to_gpio(info->gpio_vbus_det);
429 if (phy->gpio_vbus_det >= 0) {
430 ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
433 ret = gpio_direction_input(phy->gpio_vbus_det);
438 phy->gpio_id_det = sunxi_name_to_gpio(info->gpio_id_det);
439 if (phy->gpio_id_det >= 0) {
440 ret = gpio_request(phy->gpio_id_det, "usb_id_det");
443 ret = gpio_direction_input(phy->gpio_id_det);
446 sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
449 if (i || data->cfg->phy0_dual_route) {
450 snprintf(name, sizeof(name), "pmu%d", i);
451 phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);
452 if (IS_ERR(phy->pmu))
453 return PTR_ERR(phy->pmu);
457 phy->rst_mask = info->rst_mask;
460 setbits_le32(&data->ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
462 debug("Allwinner Sun4I USB PHY driver loaded\n");
466 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
468 .type = sun4i_a10_phy,
470 .phyctl_offset = REG_PHYCTL_A10,
471 .enable_pmu_unk1 = false,
474 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
476 .type = sun4i_a10_phy,
478 .phyctl_offset = REG_PHYCTL_A10,
479 .enable_pmu_unk1 = false,
482 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
484 .type = sun6i_a31_phy,
486 .phyctl_offset = REG_PHYCTL_A10,
487 .enable_pmu_unk1 = false,
490 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
492 .type = sun4i_a10_phy,
494 .phyctl_offset = REG_PHYCTL_A10,
495 .enable_pmu_unk1 = false,
498 static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
500 .type = sun4i_a10_phy,
502 .phyctl_offset = REG_PHYCTL_A10,
503 .enable_pmu_unk1 = false,
506 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
508 .type = sun8i_a33_phy,
510 .phyctl_offset = REG_PHYCTL_A33,
511 .enable_pmu_unk1 = false,
514 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
516 .type = sun8i_a83t_phy,
517 .phyctl_offset = REG_PHYCTL_A33,
520 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
522 .type = sun8i_h3_phy,
524 .phyctl_offset = REG_PHYCTL_A33,
525 .enable_pmu_unk1 = true,
526 .phy0_dual_route = true,
529 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
531 .type = sun8i_v3s_phy,
533 .phyctl_offset = REG_PHYCTL_A33,
534 .enable_pmu_unk1 = true,
535 .phy0_dual_route = true,
538 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
540 .type = sun50i_a64_phy,
542 .phyctl_offset = REG_PHYCTL_A33,
543 .enable_pmu_unk1 = true,
544 .phy0_dual_route = true,
547 static const struct udevice_id sun4i_usb_phy_ids[] = {
548 { .compatible = "allwinner,sun4i-a10-usb-phy", .data = (ulong)&sun4i_a10_cfg },
549 { .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg },
550 { .compatible = "allwinner,sun6i-a31-usb-phy", .data = (ulong)&sun6i_a31_cfg },
551 { .compatible = "allwinner,sun7i-a20-usb-phy", .data = (ulong)&sun7i_a20_cfg },
552 { .compatible = "allwinner,sun8i-a23-usb-phy", .data = (ulong)&sun8i_a23_cfg },
553 { .compatible = "allwinner,sun8i-a33-usb-phy", .data = (ulong)&sun8i_a33_cfg },
554 { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
555 { .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
556 { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },
557 { .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
561 U_BOOT_DRIVER(sun4i_usb_phy) = {
562 .name = "sun4i_usb_phy",
564 .of_match = sun4i_usb_phy_ids,
565 .ops = &sun4i_usb_phy_ops,
566 .probe = sun4i_usb_phy_probe,
567 .platdata_auto_alloc_size = sizeof(struct sun4i_usb_phy_plat[MAX_PHYS]),
568 .priv_auto_alloc_size = sizeof(struct sun4i_usb_phy_data),