git.sur5r.net Git - u-boot/blob - drivers/phy/marvell/comphy.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2015-2016 Marvell International Ltd.
   4  */
   5
   6 #ifndef _COMPHY_H_
   7 #define _COMPHY_H_
   8
   9 #include <dt-bindings/comphy/comphy_data.h>
  10 #include <fdtdec.h>
  11
  12 #if defined(DEBUG)
  13 #define debug_enter()   printf("----> Enter %s\n", __func__);
  14 #define debug_exit()    printf("<---- Exit  %s\n", __func__);
  15 #else
  16 #define debug_enter()
  17 #define debug_exit()
  18 #endif
  19
  20 /* COMPHY registers */
  21 #define COMMON_PHY_CFG1_REG                     0x0
  22 #define COMMON_PHY_CFG1_PWR_UP_OFFSET           1
  23 #define COMMON_PHY_CFG1_PWR_UP_MASK             \
  24         (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
  25 #define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET      2
  26 #define COMMON_PHY_CFG1_PIPE_SELECT_MASK        \
  27         (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
  28 #define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET     13
  29 #define COMMON_PHY_CFG1_PWR_ON_RESET_MASK       \
  30         (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
  31 #define COMMON_PHY_CFG1_CORE_RSTN_OFFSET        14
  32 #define COMMON_PHY_CFG1_CORE_RSTN_MASK          \
  33         (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
  34 #define COMMON_PHY_PHY_MODE_OFFSET              15
  35 #define COMMON_PHY_PHY_MODE_MASK                \
  36         (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
  37
  38 #define COMMON_PHY_CFG6_REG                     0x14
  39 #define COMMON_PHY_CFG6_IF_40_SEL_OFFSET        18
  40 #define COMMON_PHY_CFG6_IF_40_SEL_MASK          \
  41         (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
  42
  43 #define COMMON_SELECTOR_PHY_OFFSET              0x140
  44 #define COMMON_SELECTOR_PIPE_OFFSET             0x144
  45
  46 #define COMMON_PHY_SD_CTRL1                     0x148
  47 #define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET      0
  48 #define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK        0xFFFF
  49 #define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET   24
  50 #define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK     \
  51         (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
  52 #define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET   25
  53 #define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK     \
  54         (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
  55 #define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET       26
  56 #define COMMON_PHY_SD_CTRL1_RXAUI1_MASK         \
  57         (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
  58 #define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET       27
  59 #define COMMON_PHY_SD_CTRL1_RXAUI0_MASK         \
  60         (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
  61
  62 /* ToDo: Get this address via DT */
  63 #define MVEBU_CP0_REGS_BASE                     0xF2000000UL
  64
  65 #define DFX_DEV_GEN_CTRL12                      (MVEBU_CP0_REGS_BASE + 0x400280)
  66 #define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET         7
  67 #define DFX_DEV_GEN_PCIE_CLK_SRC_MASK           \
  68         (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET)
  69
  70 #define MAX_LANE_OPTIONS                        10
  71 #define MAX_UTMI_PHY_COUNT                      3
  72
  73 struct comphy_mux_options {
  74         u32 type;
  75         u32 mux_value;
  76 };
  77
  78 struct comphy_mux_data {
  79         u32 max_lane_values;
  80         struct comphy_mux_options mux_values[MAX_LANE_OPTIONS];
  81 };
  82
  83 struct comphy_map {
  84         u32 type;
  85         u32 speed;
  86         u32 invert;
  87         bool clk_src;
  88         bool end_point;
  89 };
  90
  91 struct chip_serdes_phy_config {
  92         struct comphy_mux_data *mux_data;
  93         int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *,
  94                                     struct comphy_map *);
  95         void __iomem *comphy_base_addr;
  96         void __iomem *hpipe3_base_addr;
  97         u32 comphy_lanes_count;
  98         u32 comphy_mux_bitcount;
  99         u32 cp_index;
 100 };
 101
 102 /* Register helper functions */
 103 void reg_set(void __iomem *addr, u32 data, u32 mask);
 104 void reg_set_silent(void __iomem *addr, u32 data, u32 mask);
 105 void reg_set16(void __iomem *addr, u16 data, u16 mask);
 106 void reg_set_silent16(void __iomem *addr, u16 data, u16 mask);
 107
 108 /* SoC specific init functions */
 109 #ifdef CONFIG_ARMADA_3700
 110 int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 111                       struct comphy_map *serdes_map);
 112 #else
 113 static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 114                                     struct comphy_map *serdes_map)
 115 {
 116         /*
 117          * This function should never be called in this configuration, so
 118          * lets return an error here.
 119          */
 120         return -1;
 121 }
 122 #endif
 123
 124 #ifdef CONFIG_ARMADA_8K
 125 int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 126                       struct comphy_map *serdes_map);
 127 #else
 128 static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 129                       struct comphy_map *serdes_map)
 130 {
 131         /*
 132          * This function should never be called in this configuration, so
 133          * lets return an error here.
 134          */
 135         return -1;
 136 }
 137 #endif
 138
 139 void comphy_dedicated_phys_init(void);
 140
 141 /* MUX function */
 142 void comphy_mux_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 143                      struct comphy_map *comphy_map_data,
 144                      void __iomem *selector_base);
 145
 146 void comphy_pcie_config_set(u32 comphy_max_count,
 147                             struct comphy_map *serdes_map);
 148 void comphy_pcie_config_detect(u32 comphy_max_count,
 149                                struct comphy_map *serdes_map);
 150 void comphy_pcie_unit_general_config(u32 pex_index);
 151
 152 #endif /* _COMPHY_H_ */
 153