2 * Copyright (C) 2015-2016 Marvell International Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _COMPHY_HPIPE_H_
8 #define _COMPHY_HPIPE_H_
10 /* SerDes IP register */
11 #define SD_EXTERNAL_CONFIG0_REG 0
12 #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1
13 #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \
14 (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET)
15 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3
16 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \
17 (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET)
18 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7
19 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \
20 (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET)
21 #define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11
22 #define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \
23 (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET)
24 #define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12
25 #define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \
26 (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET)
27 #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14
28 #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \
29 (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET)
30 #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15
31 #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \
32 (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
34 #define SD_EXTERNAL_CONFIG1_REG 0x4
35 #define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3
36 #define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \
37 (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
38 #define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4
39 #define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \
40 (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET)
41 #define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5
42 #define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \
43 (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET)
44 #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6
45 #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \
46 (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)
48 #define SD_EXTERNAL_CONFIG2_REG 0x8
49 #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4
50 #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \
51 (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
53 #define SD_EXTERNAL_STATUS0_REG 0x18
54 #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2
55 #define SD_EXTERNAL_STATUS0_PLL_TX_MASK \
56 (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET)
57 #define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3
58 #define SD_EXTERNAL_STATUS0_PLL_RX_MASK \
59 (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET)
60 #define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4
61 #define SD_EXTERNAL_STATUS0_RX_INIT_MASK \
62 (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET)
63 #define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET 6
64 #define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \
65 (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET)
68 #define HPIPE_PWR_PLL_REG 0x4
69 #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0
70 #define HPIPE_PWR_PLL_REF_FREQ_MASK \
71 (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET)
72 #define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5
73 #define HPIPE_PWR_PLL_PHY_MODE_MASK \
74 (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
76 #define HPIPE_KVCO_CALIB_CTRL_REG 0x8
77 #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12
78 #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \
79 (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)
81 #define HPIPE_CAL_REG1_REG 0xc
82 #define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10
83 #define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \
84 (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET)
85 #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15
86 #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \
87 (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)
89 #define HPIPE_SQUELCH_FFE_SETTING_REG 0x018
91 #define HPIPE_DFE_REG0 0x01C
92 #define HPIPE_DFE_RES_FORCE_OFFSET 15
93 #define HPIPE_DFE_RES_FORCE_MASK \
94 (0x1 << HPIPE_DFE_RES_FORCE_OFFSET)
96 #define HPIPE_DFE_F3_F5_REG 0x028
97 #define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14
98 #define HPIPE_DFE_F3_F5_DFE_EN_MASK \
99 (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET)
100 #define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15
101 #define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \
102 (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
104 #define HPIPE_G1_SET_0_REG 0x034
105 #define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1
106 #define HPIPE_G1_SET_0_G1_TX_AMP_MASK \
107 (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
108 #define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7
109 #define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \
110 (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
112 #define HPIPE_G1_SET_1_REG 0x038
113 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
114 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \
115 (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
116 #define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3
117 #define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \
118 (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
119 #define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10
120 #define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \
121 (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
123 #define HPIPE_G2_SETTINGS_1_REG 0x040
125 #define HPIPE_G3_SETTINGS_1_REG 0x048
126 #define HPIPE_G3_RX_SELMUPI_OFFSET 0
127 #define HPIPE_G3_RX_SELMUPI_MASK \
128 (0x7 << HPIPE_G3_RX_SELMUPI_OFFSET)
129 #define HPIPE_G3_RX_SELMUPF_OFFSET 3
130 #define HPIPE_G3_RX_SELMUPF_MASK \
131 (0x7 << HPIPE_G3_RX_SELMUPF_OFFSET)
132 #define HPIPE_G3_SETTING_BIT_OFFSET 13
133 #define HPIPE_G3_SETTING_BIT_MASK \
134 (0x1 << HPIPE_G3_SETTING_BIT_OFFSET)
136 #define HPIPE_LOOPBACK_REG 0x08c
137 #define HPIPE_LOOPBACK_SEL_OFFSET 1
138 #define HPIPE_LOOPBACK_SEL_MASK \
139 (0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
141 #define HPIPE_SYNC_PATTERN_REG 0x090
143 #define HPIPE_INTERFACE_REG 0x94
144 #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
145 #define HPIPE_INTERFACE_GEN_MAX_MASK \
146 (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
147 #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14
148 #define HPIPE_INTERFACE_LINK_TRAIN_MASK \
149 (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
151 #define HPIPE_ISOLATE_MODE_REG 0x98
152 #define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0
153 #define HPIPE_ISOLATE_MODE_GEN_RX_MASK \
154 (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET)
155 #define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4
156 #define HPIPE_ISOLATE_MODE_GEN_TX_MASK \
157 (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)
159 #define HPIPE_G1_SET_2_REG 0xf4
160 #define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0
161 #define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \
162 (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET)
163 #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4
164 #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \
165 (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK)
167 #define HPIPE_VTHIMPCAL_CTRL_REG 0x104
169 #define HPIPE_PCIE_REG0 0x120
170 #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12
171 #define HPIPE_PCIE_IDLE_SYNC_MASK \
172 (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET)
173 #define HPIPE_PCIE_SEL_BITS_OFFSET 13
174 #define HPIPE_PCIE_SEL_BITS_MASK \
175 (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET)
177 #define HPIPE_LANE_ALIGN_REG 0x124
178 #define HPIPE_LANE_ALIGN_OFF_OFFSET 12
179 #define HPIPE_LANE_ALIGN_OFF_MASK \
180 (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET)
182 #define HPIPE_MISC_REG 0x13C
183 #define HPIPE_MISC_CLK100M_125M_OFFSET 4
184 #define HPIPE_MISC_CLK100M_125M_MASK \
185 (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
186 #define HPIPE_MISC_ICP_FORCE_OFFSET 5
187 #define HPIPE_MISC_ICP_FORCE_MASK \
188 (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET)
189 #define HPIPE_MISC_TXDCLK_2X_OFFSET 6
190 #define HPIPE_MISC_TXDCLK_2X_MASK \
191 (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
192 #define HPIPE_MISC_CLK500_EN_OFFSET 7
193 #define HPIPE_MISC_CLK500_EN_MASK \
194 (0x1 << HPIPE_MISC_CLK500_EN_OFFSET)
195 #define HPIPE_MISC_REFCLK_SEL_OFFSET 10
196 #define HPIPE_MISC_REFCLK_SEL_MASK \
197 (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET)
199 #define HPIPE_RX_CONTROL_1_REG 0x140
200 #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11
201 #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \
202 (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET)
203 #define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12
204 #define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \
205 (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET)
207 #define HPIPE_PWR_CTR_REG 0x148
208 #define HPIPE_PWR_CTR_RST_DFE_OFFSET 0
209 #define HPIPE_PWR_CTR_RST_DFE_MASK \
210 (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET)
211 #define HPIPE_PWR_CTR_SFT_RST_OFFSET 10
212 #define HPIPE_PWR_CTR_SFT_RST_MASK \
213 (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
215 #define HPIPE_PLLINTP_REG1 0x150
217 #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C
218 #define HPIPE_SMAPLER_OFFSET 12
219 #define HPIPE_SMAPLER_MASK \
220 (0x1 << HPIPE_SMAPLER_OFFSET)
222 #define HPIPE_TX_REG1_REG 0x174
223 #define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5
224 #define HPIPE_TX_REG1_TX_EMPH_RES_MASK \
225 (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET)
226 #define HPIPE_TX_REG1_SLC_EN_OFFSET 10
227 #define HPIPE_TX_REG1_SLC_EN_MASK \
228 (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
230 #define HPIPE_PWR_CTR_DTL_REG 0x184
231 #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
232 #define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
233 (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
235 #define HPIPE_RX_REG3 0x188
237 #define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
238 #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15
239 #define HPIPE_TX_TRAIN_P2P_HOLD_MASK \
240 (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET)
242 #define HPIPE_TX_TRAIN_CTRL_REG 0x26C
243 #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0
244 #define HPIPE_TX_TRAIN_CTRL_G1_MASK \
245 (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET)
246 #define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1
247 #define HPIPE_TX_TRAIN_CTRL_GN1_MASK \
248 (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET)
249 #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2
250 #define HPIPE_TX_TRAIN_CTRL_G0_MASK \
251 (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
253 #define HPIPE_TX_TRAIN_CTRL_4_REG 0x278
254 #define HPIPE_TRX_TRAIN_TIMER_OFFSET 0
255 #define HPIPE_TRX_TRAIN_TIMER_MASK \
256 (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET)
258 #define HPIPE_PCIE_REG1 0x288
259 #define HPIPE_PCIE_REG3 0x290
261 #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4
262 #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11
263 #define HPIPE_TX_TRAIN_START_SQ_EN_MASK \
264 (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
265 #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12
266 #define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \
267 (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET)
268 #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13
269 #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \
270 (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET)
271 #define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14
272 #define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \
273 (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET)
275 #define HPIPE_TX_TRAIN_REG 0x31C
276 #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4
277 #define HPIPE_TX_TRAIN_CHK_INIT_MASK \
278 (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET)
279 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7
280 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \
281 (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
283 #define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
284 #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
285 #define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \
286 (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET)
287 #define HPIPE_TX_NUM_OF_PRESET_OFFSET 10
288 #define HPIPE_TX_NUM_OF_PRESET_MASK \
289 (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET)
290 #define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15
291 #define HPIPE_TX_SWEEP_PRESET_EN_MASK \
292 (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
294 #define HPIPE_G1_SETTINGS_3_REG 0x440
295 #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9
296 #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \
297 (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
299 #define HPIPE_G1_SETTINGS_4_REG 0x444
300 #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8
301 #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \
302 (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
304 #define HPIPE_G2_SETTINGS_3_REG 0x448
305 #define HPIPE_G2_SETTINGS_4_REG 0x44C
307 #define HPIPE_G3_SETTING_3_REG 0x450
308 #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12
309 #define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \
310 (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
311 #define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14
312 #define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \
313 (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET)
315 #define HPIPE_G3_SETTING_4_REG 0x454
316 #define HPIPE_G3_DFE_RES_OFFSET 8
317 #define HPIPE_G3_DFE_RES_MASK \
318 (0x3 << HPIPE_G3_DFE_RES_OFFSET)
320 #define HPIPE_DFE_CTRL_28_REG 0x49C
321 #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7
322 #define HPIPE_DFE_CTRL_28_PIPE4_MASK \
323 (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
325 #define HPIPE_G1_SETTING_5_REG 0x538
326 #define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0
327 #define HPIPE_G1_SETTING_5_G1_ICP_MASK \
328 (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
330 #define HPIPE_LANE_CONFIG0_REG 0x600
331 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0
332 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \
333 (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET)
335 #define HPIPE_LANE_CONFIG1_REG 0x604
336 #define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET 9
337 #define HPIPE_LANE_CONFIG1_MAX_PLL_MASK \
338 (0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET)
339 #define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET 10
340 #define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK \
341 (0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET)
343 #define HPIPE_LANE_STATUS1_REG 0x60C
344 #define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0
345 #define HPIPE_LANE_STATUS1_PCLK_EN_MASK \
346 (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET)
348 #define HPIPE_LANE_CFG4_REG 0x620
349 #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0
350 #define HPIPE_LANE_CFG4_DFE_CTRL_MASK \
351 (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
352 #define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6
353 #define HPIPE_LANE_CFG4_DFE_OVER_MASK \
354 (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
355 #define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7
356 #define HPIPE_LANE_CFG4_SSC_CTRL_MASK \
357 (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)
359 #define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C
360 #define HPIPE_CFG_PHY_RC_EP_OFFSET 12
361 #define HPIPE_CFG_PHY_RC_EP_MASK \
362 (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET)
364 #define HPIPE_LANE_EQ_CFG1_REG 0x6a0
365 #define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12
366 #define HPIPE_CFG_UPDATE_POLARITY_MASK \
367 (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
369 #define HPIPE_RST_CLK_CTRL_REG 0x704
370 #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
371 #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \
372 (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
373 #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2
374 #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \
375 (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
376 #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3
377 #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \
378 (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
379 #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9
380 #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \
381 (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
383 #define HPIPE_TST_MODE_CTRL_REG 0x708
384 #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2
385 #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \
386 (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET)
388 #define HPIPE_CLK_SRC_LO_REG 0x70c
389 #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
390 #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \
391 (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
392 #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
393 #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \
394 (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
395 #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5
396 #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \
397 (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
399 #define HPIPE_CLK_SRC_HI_REG 0x710
400 #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0
401 #define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \
402 (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
403 #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1
404 #define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \
405 (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
406 #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2
407 #define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \
408 (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
409 #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7
410 #define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \
411 (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
413 #define HPIPE_GLOBAL_MISC_CTRL 0x718
414 #define HPIPE_GLOBAL_PM_CTRL 0x740
415 #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0
416 #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \
417 (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET)
419 #endif /* _COMPHY_HPIPE_H_ */