2 * Copyright (C) 2015-2016 Marvell International Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _COMPHY_HPIPE_H_
8 #define _COMPHY_HPIPE_H_
10 /* SerDes IP register */
11 #define SD_EXTERNAL_CONFIG0_REG 0
12 #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1
13 #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \
14 (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET)
15 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3
16 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \
17 (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET)
18 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7
19 #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \
20 (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET)
21 #define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11
22 #define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \
23 (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET)
24 #define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12
25 #define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \
26 (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET)
27 #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14
28 #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \
29 (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET)
30 #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15
31 #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \
32 (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
34 #define SD_EXTERNAL_CONFIG1_REG 0x4
35 #define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3
36 #define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \
37 (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
38 #define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4
39 #define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \
40 (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET)
41 #define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5
42 #define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \
43 (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET)
44 #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6
45 #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \
46 (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)
48 #define SD_EXTERNAL_CONFIG2_REG 0x8
49 #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4
50 #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \
51 (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
52 #define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7
53 #define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \
54 (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET)
56 #define SD_EXTERNAL_STATUS0_REG 0x18
57 #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2
58 #define SD_EXTERNAL_STATUS0_PLL_TX_MASK \
59 (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET)
60 #define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3
61 #define SD_EXTERNAL_STATUS0_PLL_RX_MASK \
62 (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET)
63 #define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4
64 #define SD_EXTERNAL_STATUS0_RX_INIT_MASK \
65 (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET)
66 #define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET 6
67 #define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \
68 (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET)
71 #define HPIPE_PWR_PLL_REG 0x4
72 #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0
73 #define HPIPE_PWR_PLL_REF_FREQ_MASK \
74 (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET)
75 #define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5
76 #define HPIPE_PWR_PLL_PHY_MODE_MASK \
77 (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
79 #define HPIPE_KVCO_CALIB_CTRL_REG 0x8
80 #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12
81 #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \
82 (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)
84 #define HPIPE_CAL_REG1_REG 0xc
85 #define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10
86 #define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \
87 (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET)
88 #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15
89 #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \
90 (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)
92 #define HPIPE_SQUELCH_FFE_SETTING_REG 0x018
94 #define HPIPE_DFE_REG0 0x01C
95 #define HPIPE_DFE_RES_FORCE_OFFSET 15
96 #define HPIPE_DFE_RES_FORCE_MASK \
97 (0x1 << HPIPE_DFE_RES_FORCE_OFFSET)
99 #define HPIPE_DFE_F3_F5_REG 0x028
100 #define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14
101 #define HPIPE_DFE_F3_F5_DFE_EN_MASK \
102 (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET)
103 #define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15
104 #define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \
105 (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
107 #define HPIPE_G1_SET_0_REG 0x034
108 #define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1
109 #define HPIPE_G1_SET_0_G1_TX_AMP_MASK \
110 (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
111 #define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6
112 #define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \
113 (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET)
114 #define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7
115 #define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \
116 (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
117 #define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11
118 #define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \
119 (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET)
121 #define HPIPE_G1_SET_1_REG 0x038
122 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
123 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \
124 (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
125 #define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3
126 #define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \
127 (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
128 #define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6
129 #define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \
130 (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET)
131 #define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8
132 #define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \
133 (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET)
134 #define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10
135 #define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \
136 (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
138 #define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11
139 #define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \
140 (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET)
142 #define HPIPE_G2_SET_0_REG 0x3c
143 #define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1
144 #define HPIPE_G2_SET_0_G2_TX_AMP_MASK \
145 (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET)
146 #define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6
147 #define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \
148 (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET)
149 #define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7
150 #define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \
151 (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET)
152 #define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11
153 #define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \
154 (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET)
156 #define HPIPE_G2_SET_1_REG 0x040
157 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0
158 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \
159 (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
160 #define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3
161 #define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \
162 (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET)
163 #define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6
164 #define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \
165 (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)
166 #define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8
167 #define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \
168 (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET)
169 #define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10
170 #define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \
171 (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET)
172 #define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11
173 #define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \
174 (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET)
176 #define HPIPE_G3_SET_0_REG 0x44
177 #define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1
178 #define HPIPE_G3_SET_0_G3_TX_AMP_MASK \
179 (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET)
180 #define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6
181 #define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \
182 (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET)
183 #define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7
184 #define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \
185 (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET)
186 #define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11
187 #define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \
188 (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET)
189 #define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12
190 #define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \
191 (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET)
192 #define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15
193 #define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \
194 (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET)
196 #define HPIPE_G3_SET_1_REG 0x048
197 #define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0
198 #define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \
199 (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET)
200 #define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3
201 #define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \
202 (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET)
203 #define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6
204 #define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \
205 (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET)
206 #define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8
207 #define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \
208 (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET)
209 #define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10
210 #define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \
211 (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET)
212 #define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11
213 #define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \
214 (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET)
215 #define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13
216 #define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \
217 (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET)
219 #define HPIPE_LOOPBACK_REG 0x08c
220 #define HPIPE_LOOPBACK_SEL_OFFSET 1
221 #define HPIPE_LOOPBACK_SEL_MASK \
222 (0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
224 #define HPIPE_SYNC_PATTERN_REG 0x090
226 #define HPIPE_INTERFACE_REG 0x94
227 #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
228 #define HPIPE_INTERFACE_GEN_MAX_MASK \
229 (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
230 #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14
231 #define HPIPE_INTERFACE_LINK_TRAIN_MASK \
232 (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
234 #define HPIPE_ISOLATE_MODE_REG 0x98
235 #define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0
236 #define HPIPE_ISOLATE_MODE_GEN_RX_MASK \
237 (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET)
238 #define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4
239 #define HPIPE_ISOLATE_MODE_GEN_TX_MASK \
240 (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)
242 #define HPIPE_G1_SET_2_REG 0xf4
243 #define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0
244 #define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \
245 (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET)
246 #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4
247 #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \
248 (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK)
250 #define HPIPE_VTHIMPCAL_CTRL_REG 0x104
252 #define HPIPE_VDD_CAL_CTRL_REG 0x114
253 #define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5
254 #define HPIPE_EXT_SELLV_RXSAMPL_MASK \
255 (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)
257 #define HPIPE_PCIE_REG0 0x120
258 #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12
259 #define HPIPE_PCIE_IDLE_SYNC_MASK \
260 (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET)
261 #define HPIPE_PCIE_SEL_BITS_OFFSET 13
262 #define HPIPE_PCIE_SEL_BITS_MASK \
263 (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET)
265 #define HPIPE_LANE_ALIGN_REG 0x124
266 #define HPIPE_LANE_ALIGN_OFF_OFFSET 12
267 #define HPIPE_LANE_ALIGN_OFF_MASK \
268 (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET)
270 #define HPIPE_MISC_REG 0x13C
271 #define HPIPE_MISC_CLK100M_125M_OFFSET 4
272 #define HPIPE_MISC_CLK100M_125M_MASK \
273 (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
274 #define HPIPE_MISC_ICP_FORCE_OFFSET 5
275 #define HPIPE_MISC_ICP_FORCE_MASK \
276 (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET)
277 #define HPIPE_MISC_TXDCLK_2X_OFFSET 6
278 #define HPIPE_MISC_TXDCLK_2X_MASK \
279 (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
280 #define HPIPE_MISC_CLK500_EN_OFFSET 7
281 #define HPIPE_MISC_CLK500_EN_MASK \
282 (0x1 << HPIPE_MISC_CLK500_EN_OFFSET)
283 #define HPIPE_MISC_REFCLK_SEL_OFFSET 10
284 #define HPIPE_MISC_REFCLK_SEL_MASK \
285 (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET)
287 #define HPIPE_RX_CONTROL_1_REG 0x140
288 #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11
289 #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \
290 (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET)
291 #define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12
292 #define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \
293 (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET)
295 #define HPIPE_PWR_CTR_REG 0x148
296 #define HPIPE_PWR_CTR_RST_DFE_OFFSET 0
297 #define HPIPE_PWR_CTR_RST_DFE_MASK \
298 (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET)
299 #define HPIPE_PWR_CTR_SFT_RST_OFFSET 10
300 #define HPIPE_PWR_CTR_SFT_RST_MASK \
301 (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
303 #define HPIPE_SPD_DIV_FORCE_REG 0x154
304 #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8
305 #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \
306 (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET)
307 #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10
308 #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK \
309 (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET)
310 #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13
311 #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK \
312 (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET)
313 #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15
314 #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \
315 (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET)
317 #define HPIPE_PLLINTP_REG1 0x150
319 #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C
320 #define HPIPE_SMAPLER_OFFSET 12
321 #define HPIPE_SMAPLER_MASK \
322 (0x1 << HPIPE_SMAPLER_OFFSET)
324 #define HPIPE_TX_REG1_REG 0x174
325 #define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5
326 #define HPIPE_TX_REG1_TX_EMPH_RES_MASK \
327 (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET)
328 #define HPIPE_TX_REG1_SLC_EN_OFFSET 10
329 #define HPIPE_TX_REG1_SLC_EN_MASK \
330 (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
332 #define HPIPE_PWR_CTR_DTL_REG 0x184
333 #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0
334 #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \
335 (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET)
336 #define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1
337 #define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \
338 (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET)
339 #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
340 #define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
341 (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
342 #define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4
343 #define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \
344 (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET)
345 #define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10
346 #define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \
347 (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET)
348 #define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12
349 #define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \
350 (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET)
351 #define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14
352 #define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \
353 (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET)
355 #define HPIPE_PHASE_CONTROL_REG 0x188
356 #define HPIPE_OS_PH_OFFSET_OFFSET 0
357 #define HPIPE_OS_PH_OFFSET_MASK \
358 (0x7f << HPIPE_OS_PH_OFFSET_OFFSET)
359 #define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7
360 #define HPIPE_OS_PH_OFFSET_FORCE_MASK \
361 (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET)
362 #define HPIPE_OS_PH_VALID_OFFSET 8
363 #define HPIPE_OS_PH_VALID_MASK \
364 (0x1 << HPIPE_OS_PH_VALID_OFFSET)
366 #define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
367 #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15
368 #define HPIPE_TX_TRAIN_P2P_HOLD_MASK \
369 (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET)
371 #define HPIPE_TX_TRAIN_CTRL_REG 0x26C
372 #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0
373 #define HPIPE_TX_TRAIN_CTRL_G1_MASK \
374 (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET)
375 #define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1
376 #define HPIPE_TX_TRAIN_CTRL_GN1_MASK \
377 (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET)
378 #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2
379 #define HPIPE_TX_TRAIN_CTRL_G0_MASK \
380 (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
382 #define HPIPE_TX_TRAIN_CTRL_4_REG 0x278
383 #define HPIPE_TRX_TRAIN_TIMER_OFFSET 0
384 #define HPIPE_TRX_TRAIN_TIMER_MASK \
385 (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET)
387 #define HPIPE_PCIE_REG1 0x288
388 #define HPIPE_PCIE_REG3 0x290
390 #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4
391 #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11
392 #define HPIPE_TX_TRAIN_START_SQ_EN_MASK \
393 (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
394 #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12
395 #define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \
396 (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET)
397 #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13
398 #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \
399 (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET)
400 #define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14
401 #define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \
402 (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET)
404 #define HPIPE_TX_TRAIN_REG 0x31C
405 #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4
406 #define HPIPE_TX_TRAIN_CHK_INIT_MASK \
407 (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET)
408 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7
409 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \
410 (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
412 #define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
413 #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
414 #define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \
415 (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET)
416 #define HPIPE_TX_NUM_OF_PRESET_OFFSET 10
417 #define HPIPE_TX_NUM_OF_PRESET_MASK \
418 (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET)
419 #define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15
420 #define HPIPE_TX_SWEEP_PRESET_EN_MASK \
421 (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
423 #define HPIPE_G1_SETTINGS_3_REG 0x440
424 #define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0
425 #define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \
426 (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET)
427 #define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4
428 #define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \
429 (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET)
430 #define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7
431 #define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \
432 (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET)
433 #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9
434 #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \
435 (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
436 #define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12
437 #define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \
438 (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET)
439 #define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14
440 #define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \
441 (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET)
443 #define HPIPE_G1_SETTINGS_4_REG 0x444
444 #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8
445 #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \
446 (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
448 #define HPIPE_G2_SETTINGS_3_REG 0x448
449 #define HPIPE_G2_SETTINGS_4_REG 0x44C
451 #define HPIPE_G3_SETTING_3_REG 0x450
452 #define HPIPE_G3_FFE_CAP_SEL_OFFSET 0
453 #define HPIPE_G3_FFE_CAP_SEL_MASK \
454 (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET)
455 #define HPIPE_G3_FFE_RES_SEL_OFFSET 4
456 #define HPIPE_G3_FFE_RES_SEL_MASK \
457 (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET)
458 #define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7
459 #define HPIPE_G3_FFE_SETTING_FORCE_MASK \
460 (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET)
461 #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12
462 #define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \
463 (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
464 #define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14
465 #define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \
466 (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET)
468 #define HPIPE_G3_SETTING_4_REG 0x454
469 #define HPIPE_G3_DFE_RES_OFFSET 8
470 #define HPIPE_G3_DFE_RES_MASK \
471 (0x3 << HPIPE_G3_DFE_RES_OFFSET)
473 #define HPIPE_DFE_CTRL_28_REG 0x49C
474 #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7
475 #define HPIPE_DFE_CTRL_28_PIPE4_MASK \
476 (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
478 #define HPIPE_G1_SETTING_5_REG 0x538
479 #define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0
480 #define HPIPE_G1_SETTING_5_G1_ICP_MASK \
481 (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
483 #define HPIPE_LANE_CONFIG0_REG 0x600
484 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0
485 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \
486 (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET)
488 #define HPIPE_LANE_CONFIG1_REG 0x604
489 #define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET 9
490 #define HPIPE_LANE_CONFIG1_MAX_PLL_MASK \
491 (0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET)
492 #define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET 10
493 #define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK \
494 (0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET)
496 #define HPIPE_LANE_STATUS1_REG 0x60C
497 #define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0
498 #define HPIPE_LANE_STATUS1_PCLK_EN_MASK \
499 (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET)
501 #define HPIPE_LANE_CFG4_REG 0x620
502 #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0
503 #define HPIPE_LANE_CFG4_DFE_CTRL_MASK \
504 (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
505 #define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6
506 #define HPIPE_LANE_CFG4_DFE_OVER_MASK \
507 (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
508 #define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7
509 #define HPIPE_LANE_CFG4_SSC_CTRL_MASK \
510 (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)
512 #define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C
513 #define HPIPE_CFG_PHY_RC_EP_OFFSET 12
514 #define HPIPE_CFG_PHY_RC_EP_MASK \
515 (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET)
517 #define HPIPE_LANE_EQ_CFG1_REG 0x6a0
518 #define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12
519 #define HPIPE_CFG_UPDATE_POLARITY_MASK \
520 (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
522 #define HPIPE_RST_CLK_CTRL_REG 0x704
523 #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
524 #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \
525 (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
526 #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2
527 #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \
528 (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
529 #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3
530 #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \
531 (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
532 #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9
533 #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \
534 (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
536 #define HPIPE_TST_MODE_CTRL_REG 0x708
537 #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2
538 #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \
539 (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET)
541 #define HPIPE_CLK_SRC_LO_REG 0x70c
542 #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
543 #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \
544 (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
545 #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
546 #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \
547 (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
548 #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5
549 #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \
550 (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
552 #define HPIPE_CLK_SRC_HI_REG 0x710
553 #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0
554 #define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \
555 (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
556 #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1
557 #define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \
558 (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
559 #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2
560 #define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \
561 (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
562 #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7
563 #define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \
564 (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
566 #define HPIPE_GLOBAL_MISC_CTRL 0x718
567 #define HPIPE_GLOBAL_PM_CTRL 0x740
568 #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0
569 #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \
570 (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET)
572 #endif /* _COMPHY_HPIPE_H_ */