git.sur5r.net Git - u-boot/blob - drivers/pinctrl/renesas/pfc-r8a7792.c

   1 /*
   2  * r8a7792 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2013-2014 Renesas Electronics Corporation
   5  * Copyright (C) 2016 Cogent Embedded, Inc., <source@cogentembedded.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <dm/pinctrl.h>
  14 #include <linux/kernel.h>
  15
  16 #include "sh_pfc.h"
  17
  18 #define CPU_ALL_PORT(fn, sfx)                                           \
  19         PORT_GP_29(0, fn, sfx),                                         \
  20         PORT_GP_23(1, fn, sfx),                                         \
  21         PORT_GP_32(2, fn, sfx),                                         \
  22         PORT_GP_28(3, fn, sfx),                                         \
  23         PORT_GP_17(4, fn, sfx),                                         \
  24         PORT_GP_17(5, fn, sfx),                                         \
  25         PORT_GP_17(6, fn, sfx),                                         \
  26         PORT_GP_17(7, fn, sfx),                                         \
  27         PORT_GP_17(8, fn, sfx),                                         \
  28         PORT_GP_17(9, fn, sfx),                                         \
  29         PORT_GP_32(10, fn, sfx),                                        \
  30         PORT_GP_30(11, fn, sfx)
  31
  32 enum {
  33         PINMUX_RESERVED = 0,
  34
  35         PINMUX_DATA_BEGIN,
  36         GP_ALL(DATA),
  37         PINMUX_DATA_END,
  38
  39         PINMUX_FUNCTION_BEGIN,
  40         GP_ALL(FN),
  41
  42         /* GPSR0 */
  43         FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
  44         FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
  45         FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_16,
  46         FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, FN_IP0_21,
  47         FN_IP0_22, FN_IP0_23, FN_IP1_0, FN_IP1_1, FN_IP1_2,
  48         FN_IP1_3, FN_IP1_4,
  49
  50         /* GPSR1 */
  51         FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8, FN_IP1_9, FN_IP1_10,
  52         FN_IP1_11, FN_IP1_12, FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,
  53         FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14,
  54         FN_DU1_DB5_C3_DATA15, FN_DU1_DB6_C4, FN_DU1_DB7_C5,
  55         FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,
  56         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,
  57
  58         /* GPSR2 */
  59         FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7,
  60         FN_D8, FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
  61         FN_A0, FN_A1, FN_A2, FN_A3, FN_A4, FN_A5, FN_A6, FN_A7,
  62         FN_A8, FN_A9, FN_A10, FN_A11, FN_A12, FN_A13, FN_A14, FN_A15,
  63
  64         /* GPSR3 */
  65         FN_A16, FN_A17, FN_A18, FN_A19, FN_IP1_17, FN_IP1_18,
  66         FN_CS1_N_A26, FN_EX_CS0_N, FN_EX_CS1_N, FN_EX_CS2_N, FN_EX_CS3_N,
  67         FN_EX_CS4_N, FN_EX_CS5_N, FN_BS_N, FN_RD_N, FN_RD_WR_N,
  68         FN_WE0_N, FN_WE1_N, FN_EX_WAIT0, FN_IRQ0, FN_IRQ1, FN_IRQ2, FN_IRQ3,
  69         FN_IP1_19, FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0_N,
  70
  71         /* GPSR4 */
  72         FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC_N, FN_VI0_VSYNC_N,
  73         FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,
  74         FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,
  75         FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,
  76         FN_VI0_FIELD,
  77
  78         /* GPSR5 */
  79         FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC_N, FN_VI1_VSYNC_N,
  80         FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,
  81         FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,
  82         FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,
  83         FN_VI1_FIELD,
  84
  85         /* GPSR6 */
  86         FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3, FN_IP2_4, FN_IP2_5, FN_IP2_6,
  87         FN_IP2_7, FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11, FN_IP2_12,
  88         FN_IP2_13, FN_IP2_14, FN_IP2_15, FN_IP2_16,
  89
  90         /* GPSR7 */
  91         FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3, FN_IP3_4, FN_IP3_5, FN_IP3_6,
  92         FN_IP3_7, FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11, FN_IP3_12,
  93         FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14, FN_VI3_FIELD,
  94
  95         /* GPSR8 */
  96         FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2, FN_IP4_4, FN_IP4_6_5,
  97         FN_IP4_8_7, FN_IP4_10_9, FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15,
  98         FN_IP4_18_17, FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,
  99
 100         /* GPSR9 */
 101         FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2, FN_IP5_3, FN_IP5_4, FN_IP5_5,
 102         FN_IP5_6, FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10, FN_IP5_11,
 103         FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3, FN_VI5_FIELD,
 104
 105         /* GPSR10 */
 106         FN_IP6_0, FN_IP6_1, FN_HRTS0_N, FN_IP6_2, FN_IP6_3, FN_IP6_4, FN_IP6_5,
 107         FN_HCTS1_N, FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0_N, FN_RTS0_N,
 108         FN_TX0, FN_RX0, FN_SCK1, FN_CTS1_N, FN_RTS1_N, FN_TX1, FN_RX1,
 109         FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_16,
 110         FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX, FN_CAN0_RX, FN_CAN_CLK,
 111         FN_CAN1_TX, FN_CAN1_RX,
 112
 113         /* GPSR11 */
 114         FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6, FN_IP7_7, FN_SD0_CLK,
 115         FN_SD0_CMD, FN_SD0_DAT0, FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3,
 116         FN_SD0_CD, FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,
 117         FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18, FN_IP7_19, FN_IP7_20,
 118         FN_ADICLK, FN_ADICS_SAMP, FN_ADIDATA, FN_ADICHS0, FN_ADICHS1,
 119         FN_ADICHS2, FN_AVS1, FN_AVS2,
 120
 121         /* IPSR0 */
 122         FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2,
 123         FN_DU0_DR3_Y5_DATA3, FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5,
 124         FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7, FN_DU0_DG0_DATA8,
 125         FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,
 126         FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14,
 127         FN_DU0_DG7_Y3_DATA15, FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0,
 128         FN_DU0_DB3_C1, FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4,
 129         FN_DU0_DB7_C5,
 130
 131         /* IPSR1 */
 132         FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC,
 133         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP, FN_DU0_CDE,
 134         FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,
 135         FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5,
 136         FN_DU1_DG2_C6_DATA6, FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8,
 137         FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10, FN_DU1_DG7_Y3_DATA11,
 138         FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1, FN_A22, FN_IO2,
 139         FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,
 140
 141         /* IPSR2 */
 142         FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,
 143         FN_VI2_HSYNC_N, FN_AVB_RXD0, FN_VI2_VSYNC_N, FN_AVB_RXD1,
 144         FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,
 145         FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,
 146         FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,
 147         FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,
 148         FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,
 149         FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,
 150         FN_VI2_FIELD, FN_AVB_TXD2,
 151
 152         /* IPSR3 */
 153         FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,
 154         FN_VI3_HSYNC_N, FN_AVB_TXD5, FN_VI3_VSYNC_N, FN_AVB_TXD6,
 155         FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,
 156         FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,
 157         FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,
 158         FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,
 159         FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
 160         FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
 161
 162         /* IPSR4 */
 163         FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
 164         FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, FN_RDR_CLKOUT,
 165         FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
 166         FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4,
 167         FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
 168         FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6,
 169         FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7,
 170         FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4,
 171         FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,
 172         FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6,
 173         FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,
 174         FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,
 175         FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,
 176
 177         /* IPSR5 */
 178         FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B, FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
 179         FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
 180         FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,
 181         FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,
 182         FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,
 183         FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,
 184
 185         /* IPSR6 */
 186         FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0_N,
 187         FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,
 188         FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1_N,
 189         FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,
 190         FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2, FN_DREQ0_N, FN_RX2,
 191         FN_DACK1, FN_SCK3, FN_TX3, FN_DREQ1_N, FN_RX3,
 192
 193         /* IPSR7 */
 194         FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,
 195         FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,
 196         FN_SSI_SCK34, FN_TPU0TO0, FN_SSI_WS34, FN_TPU0TO1,
 197         FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,
 198         FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT,
 199         FN_AUDIO_CLKA, FN_AUDIO_CLKB,
 200
 201         /* MOD_SEL */
 202         FN_SEL_VI1_0, FN_SEL_VI1_1,
 203         PINMUX_FUNCTION_END,
 204
 205         PINMUX_MARK_BEGIN,
 206         DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,
 207         DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,
 208         DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
 209         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
 210         DU1_DISP_MARK, DU1_CDE_MARK,
 211
 212         D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, D6_MARK,
 213         D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK,
 214         D14_MARK, D15_MARK, A0_MARK, A1_MARK, A2_MARK, A3_MARK, A4_MARK,
 215         A5_MARK, A6_MARK, A7_MARK, A8_MARK, A9_MARK, A10_MARK, A11_MARK,
 216         A12_MARK, A13_MARK, A14_MARK, A15_MARK,
 217
 218         A16_MARK, A17_MARK, A18_MARK, A19_MARK, CS1_N_A26_MARK,
 219         EX_CS0_N_MARK, EX_CS1_N_MARK, EX_CS2_N_MARK, EX_CS3_N_MARK,
 220         EX_CS4_N_MARK, EX_CS5_N_MARK, BS_N_MARK, RD_N_MARK, RD_WR_N_MARK,
 221         WE0_N_MARK, WE1_N_MARK, EX_WAIT0_MARK,
 222         IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_N_MARK,
 223
 224         VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
 225         VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK,
 226         VI0_D3_B3_C3_MARK, VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
 227         VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, VI0_D8_G0_Y0_MARK,
 228         VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
 229         VI0_FIELD_MARK,
 230
 231         VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
 232         VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, VI1_D2_B2_C2_MARK,
 233         VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
 234         VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, VI1_D8_G0_Y0_MARK,
 235         VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
 236         VI1_FIELD_MARK,
 237
 238         VI3_D10_Y2_MARK, VI3_FIELD_MARK,
 239
 240         VI4_CLK_MARK,
 241
 242         VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
 243         VI5_FIELD_MARK,
 244
 245         HRTS0_N_MARK, HCTS1_N_MARK, SCK0_MARK, CTS0_N_MARK, RTS0_N_MARK,
 246         TX0_MARK, RX0_MARK, SCK1_MARK, CTS1_N_MARK, RTS1_N_MARK,
 247         TX1_MARK, RX1_MARK, SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,
 248         CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,
 249
 250         SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK, SD0_DAT1_MARK,
 251         SD0_DAT2_MARK, SD0_DAT3_MARK, SD0_CD_MARK, SD0_WP_MARK,
 252         ADICLK_MARK, ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,
 253         ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,
 254
 255         /* IPSR0 */
 256         DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,
 257         DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,
 258         DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,
 259         DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,
 260         DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,
 261         DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,
 262         DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK, DU0_DB5_C3_MARK,
 263         DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,
 264
 265         /* IPSR1 */
 266         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
 267         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,
 268         DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,
 269         DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,
 270         DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,
 271         DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,
 272         A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,
 273         A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,
 274
 275         /* IPSR2 */
 276         VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,
 277         VI2_HSYNC_N_MARK, AVB_RXD0_MARK, VI2_VSYNC_N_MARK, AVB_RXD1_MARK,
 278         VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_TX_CLK_MARK,
 279         VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,
 280         VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,
 281         VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,
 282         VI2_D8_Y0_MARK, AVB_RXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,
 283         VI2_D10_Y2_MARK, AVB_TXD0_MARK,
 284         VI2_D11_Y3_MARK, AVB_TXD1_MARK, VI2_FIELD_MARK, AVB_TXD2_MARK,
 285
 286         /* IPSR3 */
 287         VI3_CLK_MARK, AVB_TXD3_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,
 288         VI3_HSYNC_N_MARK, AVB_TXD5_MARK, VI3_VSYNC_N_MARK, AVB_TXD6_MARK,
 289         VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,
 290         VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,
 291         VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,
 292         VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,
 293         VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,
 294         VI3_D11_Y3_MARK, AVB_AVTP_MATCH_MARK,
 295
 296         /* IPSR4 */
 297         VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_N_MARK,
 298         VI0_D13_G5_Y5_MARK, VI4_VSYNC_N_MARK, VI0_D14_G6_Y6_MARK,
 299         RDR_CLKOUT_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK, VI4_D1_C1_MARK,
 300         VI0_D16_R0_MARK, VI1_D12_G4_Y4_MARK, VI4_D2_C2_MARK, VI0_D17_R1_MARK,
 301         VI1_D13_G5_Y5_MARK, VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_MARK,
 302         VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_MARK, VI4_D5_C5_MARK,
 303         VI0_D20_R4_MARK, VI2_D12_Y4_MARK, VI4_D6_C6_MARK, VI0_D21_R5_MARK,
 304         VI2_D13_Y5_MARK, VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,
 305         VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK, VI4_D9_Y1_MARK,
 306         VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK, VI4_D11_Y3_MARK,
 307         VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,
 308
 309         /* IPSR5 */
 310         VI5_CLKENB_MARK, VI1_D12_G4_Y4_B_MARK, VI5_HSYNC_N_MARK,
 311         VI1_D13_G5_Y5_B_MARK, VI5_VSYNC_N_MARK, VI1_D14_G6_Y6_B_MARK,
 312         VI5_D0_C0_MARK, VI1_D15_G7_Y7_B_MARK, VI5_D1_C1_MARK, VI1_D16_R0_MARK,
 313         VI5_D2_C2_MARK, VI1_D17_R1_MARK, VI5_D3_C3_MARK, VI1_D18_R2_MARK,
 314         VI5_D4_C4_MARK, VI1_D19_R3_MARK, VI5_D5_C5_MARK, VI1_D20_R4_MARK,
 315         VI5_D6_C6_MARK, VI1_D21_R5_MARK, VI5_D7_C7_MARK, VI1_D22_R6_MARK,
 316         VI5_D8_Y0_MARK, VI1_D23_R7_MARK,
 317
 318         /* IPSR6 */
 319         MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_N_MARK,
 320         MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,
 321         MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_N_MARK,
 322         MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,
 323         DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK, DREQ0_N_MARK,
 324         RX2_MARK, DACK1_MARK, SCK3_MARK, TX3_MARK, DREQ1_N_MARK,
 325         RX3_MARK,
 326
 327         /* IPSR7 */
 328         PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK, PWM1_MARK, TCLK2_MARK,
 329         FSO_CFE_1_MARK, PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK, PWM3_MARK,
 330         PWM4_MARK, SSI_SCK34_MARK, TPU0TO0_MARK, SSI_WS34_MARK, TPU0TO1_MARK,
 331         SSI_SDATA3_MARK, TPU0TO2_MARK, SSI_SCK4_MARK, TPU0TO3_MARK,
 332         SSI_WS4_MARK, SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK, AUDIO_CLKA_MARK,
 333         AUDIO_CLKB_MARK,
 334         PINMUX_MARK_END,
 335 };
 336
 337 static const u16 pinmux_data[] = {
 338         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 339
 340         PINMUX_SINGLE(DU1_DB2_C0_DATA12),
 341         PINMUX_SINGLE(DU1_DB3_C1_DATA13),
 342         PINMUX_SINGLE(DU1_DB4_C2_DATA14),
 343         PINMUX_SINGLE(DU1_DB5_C3_DATA15),
 344         PINMUX_SINGLE(DU1_DB6_C4),
 345         PINMUX_SINGLE(DU1_DB7_C5),
 346         PINMUX_SINGLE(DU1_EXHSYNC_DU1_HSYNC),
 347         PINMUX_SINGLE(DU1_EXVSYNC_DU1_VSYNC),
 348         PINMUX_SINGLE(DU1_EXODDF_DU1_ODDF_DISP_CDE),
 349         PINMUX_SINGLE(DU1_DISP),
 350         PINMUX_SINGLE(DU1_CDE),
 351         PINMUX_SINGLE(D0),
 352         PINMUX_SINGLE(D1),
 353         PINMUX_SINGLE(D2),
 354         PINMUX_SINGLE(D3),
 355         PINMUX_SINGLE(D4),
 356         PINMUX_SINGLE(D5),
 357         PINMUX_SINGLE(D6),
 358         PINMUX_SINGLE(D7),
 359         PINMUX_SINGLE(D8),
 360         PINMUX_SINGLE(D9),
 361         PINMUX_SINGLE(D10),
 362         PINMUX_SINGLE(D11),
 363         PINMUX_SINGLE(D12),
 364         PINMUX_SINGLE(D13),
 365         PINMUX_SINGLE(D14),
 366         PINMUX_SINGLE(D15),
 367         PINMUX_SINGLE(A0),
 368         PINMUX_SINGLE(A1),
 369         PINMUX_SINGLE(A2),
 370         PINMUX_SINGLE(A3),
 371         PINMUX_SINGLE(A4),
 372         PINMUX_SINGLE(A5),
 373         PINMUX_SINGLE(A6),
 374         PINMUX_SINGLE(A7),
 375         PINMUX_SINGLE(A8),
 376         PINMUX_SINGLE(A9),
 377         PINMUX_SINGLE(A10),
 378         PINMUX_SINGLE(A11),
 379         PINMUX_SINGLE(A12),
 380         PINMUX_SINGLE(A13),
 381         PINMUX_SINGLE(A14),
 382         PINMUX_SINGLE(A15),
 383         PINMUX_SINGLE(A16),
 384         PINMUX_SINGLE(A17),
 385         PINMUX_SINGLE(A18),
 386         PINMUX_SINGLE(A19),
 387         PINMUX_SINGLE(CS1_N_A26),
 388         PINMUX_SINGLE(EX_CS0_N),
 389         PINMUX_SINGLE(EX_CS1_N),
 390         PINMUX_SINGLE(EX_CS2_N),
 391         PINMUX_SINGLE(EX_CS3_N),
 392         PINMUX_SINGLE(EX_CS4_N),
 393         PINMUX_SINGLE(EX_CS5_N),
 394         PINMUX_SINGLE(BS_N),
 395         PINMUX_SINGLE(RD_N),
 396         PINMUX_SINGLE(RD_WR_N),
 397         PINMUX_SINGLE(WE0_N),
 398         PINMUX_SINGLE(WE1_N),
 399         PINMUX_SINGLE(EX_WAIT0),
 400         PINMUX_SINGLE(IRQ0),
 401         PINMUX_SINGLE(IRQ1),
 402         PINMUX_SINGLE(IRQ2),
 403         PINMUX_SINGLE(IRQ3),
 404         PINMUX_SINGLE(CS0_N),
 405         PINMUX_SINGLE(VI0_CLK),
 406         PINMUX_SINGLE(VI0_CLKENB),
 407         PINMUX_SINGLE(VI0_HSYNC_N),
 408         PINMUX_SINGLE(VI0_VSYNC_N),
 409         PINMUX_SINGLE(VI0_D0_B0_C0),
 410         PINMUX_SINGLE(VI0_D1_B1_C1),
 411         PINMUX_SINGLE(VI0_D2_B2_C2),
 412         PINMUX_SINGLE(VI0_D3_B3_C3),
 413         PINMUX_SINGLE(VI0_D4_B4_C4),
 414         PINMUX_SINGLE(VI0_D5_B5_C5),
 415         PINMUX_SINGLE(VI0_D6_B6_C6),
 416         PINMUX_SINGLE(VI0_D7_B7_C7),
 417         PINMUX_SINGLE(VI0_D8_G0_Y0),
 418         PINMUX_SINGLE(VI0_D9_G1_Y1),
 419         PINMUX_SINGLE(VI0_D10_G2_Y2),
 420         PINMUX_SINGLE(VI0_D11_G3_Y3),
 421         PINMUX_SINGLE(VI0_FIELD),
 422         PINMUX_SINGLE(VI1_CLK),
 423         PINMUX_SINGLE(VI1_CLKENB),
 424         PINMUX_SINGLE(VI1_HSYNC_N),
 425         PINMUX_SINGLE(VI1_VSYNC_N),
 426         PINMUX_SINGLE(VI1_D0_B0_C0),
 427         PINMUX_SINGLE(VI1_D1_B1_C1),
 428         PINMUX_SINGLE(VI1_D2_B2_C2),
 429         PINMUX_SINGLE(VI1_D3_B3_C3),
 430         PINMUX_SINGLE(VI1_D4_B4_C4),
 431         PINMUX_SINGLE(VI1_D5_B5_C5),
 432         PINMUX_SINGLE(VI1_D6_B6_C6),
 433         PINMUX_SINGLE(VI1_D7_B7_C7),
 434         PINMUX_SINGLE(VI1_D8_G0_Y0),
 435         PINMUX_SINGLE(VI1_D9_G1_Y1),
 436         PINMUX_SINGLE(VI1_D10_G2_Y2),
 437         PINMUX_SINGLE(VI1_D11_G3_Y3),
 438         PINMUX_SINGLE(VI1_FIELD),
 439         PINMUX_SINGLE(VI3_D10_Y2),
 440         PINMUX_SINGLE(VI3_FIELD),
 441         PINMUX_SINGLE(VI4_CLK),
 442         PINMUX_SINGLE(VI5_CLK),
 443         PINMUX_SINGLE(VI5_D9_Y1),
 444         PINMUX_SINGLE(VI5_D10_Y2),
 445         PINMUX_SINGLE(VI5_D11_Y3),
 446         PINMUX_SINGLE(VI5_FIELD),
 447         PINMUX_SINGLE(HRTS0_N),
 448         PINMUX_SINGLE(HCTS1_N),
 449         PINMUX_SINGLE(SCK0),
 450         PINMUX_SINGLE(CTS0_N),
 451         PINMUX_SINGLE(RTS0_N),
 452         PINMUX_SINGLE(TX0),
 453         PINMUX_SINGLE(RX0),
 454         PINMUX_SINGLE(SCK1),
 455         PINMUX_SINGLE(CTS1_N),
 456         PINMUX_SINGLE(RTS1_N),
 457         PINMUX_SINGLE(TX1),
 458         PINMUX_SINGLE(RX1),
 459         PINMUX_SINGLE(SCIF_CLK),
 460         PINMUX_SINGLE(CAN0_TX),
 461         PINMUX_SINGLE(CAN0_RX),
 462         PINMUX_SINGLE(CAN_CLK),
 463         PINMUX_SINGLE(CAN1_TX),
 464         PINMUX_SINGLE(CAN1_RX),
 465         PINMUX_SINGLE(SD0_CLK),
 466         PINMUX_SINGLE(SD0_CMD),
 467         PINMUX_SINGLE(SD0_DAT0),
 468         PINMUX_SINGLE(SD0_DAT1),
 469         PINMUX_SINGLE(SD0_DAT2),
 470         PINMUX_SINGLE(SD0_DAT3),
 471         PINMUX_SINGLE(SD0_CD),
 472         PINMUX_SINGLE(SD0_WP),
 473         PINMUX_SINGLE(ADICLK),
 474         PINMUX_SINGLE(ADICS_SAMP),
 475         PINMUX_SINGLE(ADIDATA),
 476         PINMUX_SINGLE(ADICHS0),
 477         PINMUX_SINGLE(ADICHS1),
 478         PINMUX_SINGLE(ADICHS2),
 479         PINMUX_SINGLE(AVS1),
 480         PINMUX_SINGLE(AVS2),
 481
 482         /* IPSR0 */
 483         PINMUX_IPSR_GPSR(IP0_0, DU0_DR0_DATA0),
 484         PINMUX_IPSR_GPSR(IP0_1, DU0_DR1_DATA1),
 485         PINMUX_IPSR_GPSR(IP0_2, DU0_DR2_Y4_DATA2),
 486         PINMUX_IPSR_GPSR(IP0_3, DU0_DR3_Y5_DATA3),
 487         PINMUX_IPSR_GPSR(IP0_4, DU0_DR4_Y6_DATA4),
 488         PINMUX_IPSR_GPSR(IP0_5, DU0_DR5_Y7_DATA5),
 489         PINMUX_IPSR_GPSR(IP0_6, DU0_DR6_Y8_DATA6),
 490         PINMUX_IPSR_GPSR(IP0_7, DU0_DR7_Y9_DATA7),
 491         PINMUX_IPSR_GPSR(IP0_8, DU0_DG0_DATA8),
 492         PINMUX_IPSR_GPSR(IP0_9, DU0_DG1_DATA9),
 493         PINMUX_IPSR_GPSR(IP0_10, DU0_DG2_C6_DATA10),
 494         PINMUX_IPSR_GPSR(IP0_11, DU0_DG3_C7_DATA11),
 495         PINMUX_IPSR_GPSR(IP0_12, DU0_DG4_Y0_DATA12),
 496         PINMUX_IPSR_GPSR(IP0_13, DU0_DG5_Y1_DATA13),
 497         PINMUX_IPSR_GPSR(IP0_14, DU0_DG6_Y2_DATA14),
 498         PINMUX_IPSR_GPSR(IP0_15, DU0_DG7_Y3_DATA15),
 499         PINMUX_IPSR_GPSR(IP0_16, DU0_DB0),
 500         PINMUX_IPSR_GPSR(IP0_17, DU0_DB1),
 501         PINMUX_IPSR_GPSR(IP0_18, DU0_DB2_C0),
 502         PINMUX_IPSR_GPSR(IP0_19, DU0_DB3_C1),
 503         PINMUX_IPSR_GPSR(IP0_20, DU0_DB4_C2),
 504         PINMUX_IPSR_GPSR(IP0_21, DU0_DB5_C3),
 505         PINMUX_IPSR_GPSR(IP0_22, DU0_DB6_C4),
 506         PINMUX_IPSR_GPSR(IP0_23, DU0_DB7_C5),
 507
 508         /* IPSR1 */
 509         PINMUX_IPSR_GPSR(IP1_0, DU0_EXHSYNC_DU0_HSYNC),
 510         PINMUX_IPSR_GPSR(IP1_1, DU0_EXVSYNC_DU0_VSYNC),
 511         PINMUX_IPSR_GPSR(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 512         PINMUX_IPSR_GPSR(IP1_3, DU0_DISP),
 513         PINMUX_IPSR_GPSR(IP1_4, DU0_CDE),
 514         PINMUX_IPSR_GPSR(IP1_5, DU1_DR2_Y4_DATA0),
 515         PINMUX_IPSR_GPSR(IP1_6, DU1_DR3_Y5_DATA1),
 516         PINMUX_IPSR_GPSR(IP1_7, DU1_DR4_Y6_DATA2),
 517         PINMUX_IPSR_GPSR(IP1_8, DU1_DR5_Y7_DATA3),
 518         PINMUX_IPSR_GPSR(IP1_9, DU1_DR6_DATA4),
 519         PINMUX_IPSR_GPSR(IP1_10, DU1_DR7_DATA5),
 520         PINMUX_IPSR_GPSR(IP1_11, DU1_DG2_C6_DATA6),
 521         PINMUX_IPSR_GPSR(IP1_12, DU1_DG3_C7_DATA7),
 522         PINMUX_IPSR_GPSR(IP1_13, DU1_DG4_Y0_DATA8),
 523         PINMUX_IPSR_GPSR(IP1_14, DU1_DG5_Y1_DATA9),
 524         PINMUX_IPSR_GPSR(IP1_15, DU1_DG6_Y2_DATA10),
 525         PINMUX_IPSR_GPSR(IP1_16, DU1_DG7_Y3_DATA11),
 526         PINMUX_IPSR_GPSR(IP1_17, A20),
 527         PINMUX_IPSR_GPSR(IP1_17, MOSI_IO0),
 528         PINMUX_IPSR_GPSR(IP1_18, A21),
 529         PINMUX_IPSR_GPSR(IP1_18, MISO_IO1),
 530         PINMUX_IPSR_GPSR(IP1_19, A22),
 531         PINMUX_IPSR_GPSR(IP1_19, IO2),
 532         PINMUX_IPSR_GPSR(IP1_20, A23),
 533         PINMUX_IPSR_GPSR(IP1_20, IO3),
 534         PINMUX_IPSR_GPSR(IP1_21, A24),
 535         PINMUX_IPSR_GPSR(IP1_21, SPCLK),
 536         PINMUX_IPSR_GPSR(IP1_22, A25),
 537         PINMUX_IPSR_GPSR(IP1_22, SSL),
 538
 539         /* IPSR2 */
 540         PINMUX_IPSR_GPSR(IP2_0, VI2_CLK),
 541         PINMUX_IPSR_GPSR(IP2_0, AVB_RX_CLK),
 542         PINMUX_IPSR_GPSR(IP2_1, VI2_CLKENB),
 543         PINMUX_IPSR_GPSR(IP2_1, AVB_RX_DV),
 544         PINMUX_IPSR_GPSR(IP2_2, VI2_HSYNC_N),
 545         PINMUX_IPSR_GPSR(IP2_2, AVB_RXD0),
 546         PINMUX_IPSR_GPSR(IP2_3, VI2_VSYNC_N),
 547         PINMUX_IPSR_GPSR(IP2_3, AVB_RXD1),
 548         PINMUX_IPSR_GPSR(IP2_4, VI2_D0_C0),
 549         PINMUX_IPSR_GPSR(IP2_4, AVB_RXD2),
 550         PINMUX_IPSR_GPSR(IP2_5, VI2_D1_C1),
 551         PINMUX_IPSR_GPSR(IP2_5, AVB_RXD3),
 552         PINMUX_IPSR_GPSR(IP2_6, VI2_D2_C2),
 553         PINMUX_IPSR_GPSR(IP2_6, AVB_RXD4),
 554         PINMUX_IPSR_GPSR(IP2_7, VI2_D3_C3),
 555         PINMUX_IPSR_GPSR(IP2_7, AVB_RXD5),
 556         PINMUX_IPSR_GPSR(IP2_8, VI2_D4_C4),
 557         PINMUX_IPSR_GPSR(IP2_8, AVB_RXD6),
 558         PINMUX_IPSR_GPSR(IP2_9, VI2_D5_C5),
 559         PINMUX_IPSR_GPSR(IP2_9, AVB_RXD7),
 560         PINMUX_IPSR_GPSR(IP2_10, VI2_D6_C6),
 561         PINMUX_IPSR_GPSR(IP2_10, AVB_RX_ER),
 562         PINMUX_IPSR_GPSR(IP2_11, VI2_D7_C7),
 563         PINMUX_IPSR_GPSR(IP2_11, AVB_COL),
 564         PINMUX_IPSR_GPSR(IP2_12, VI2_D8_Y0),
 565         PINMUX_IPSR_GPSR(IP2_12, AVB_TXD3),
 566         PINMUX_IPSR_GPSR(IP2_13, VI2_D9_Y1),
 567         PINMUX_IPSR_GPSR(IP2_13, AVB_TX_EN),
 568         PINMUX_IPSR_GPSR(IP2_14, VI2_D10_Y2),
 569         PINMUX_IPSR_GPSR(IP2_14, AVB_TXD0),
 570         PINMUX_IPSR_GPSR(IP2_15, VI2_D11_Y3),
 571         PINMUX_IPSR_GPSR(IP2_15, AVB_TXD1),
 572         PINMUX_IPSR_GPSR(IP2_16, VI2_FIELD),
 573         PINMUX_IPSR_GPSR(IP2_16, AVB_TXD2),
 574
 575         /* IPSR3 */
 576         PINMUX_IPSR_GPSR(IP3_0, VI3_CLK),
 577         PINMUX_IPSR_GPSR(IP3_0, AVB_TX_CLK),
 578         PINMUX_IPSR_GPSR(IP3_1, VI3_CLKENB),
 579         PINMUX_IPSR_GPSR(IP3_1, AVB_TXD4),
 580         PINMUX_IPSR_GPSR(IP3_2, VI3_HSYNC_N),
 581         PINMUX_IPSR_GPSR(IP3_2, AVB_TXD5),
 582         PINMUX_IPSR_GPSR(IP3_3, VI3_VSYNC_N),
 583         PINMUX_IPSR_GPSR(IP3_3, AVB_TXD6),
 584         PINMUX_IPSR_GPSR(IP3_4, VI3_D0_C0),
 585         PINMUX_IPSR_GPSR(IP3_4, AVB_TXD7),
 586         PINMUX_IPSR_GPSR(IP3_5, VI3_D1_C1),
 587         PINMUX_IPSR_GPSR(IP3_5, AVB_TX_ER),
 588         PINMUX_IPSR_GPSR(IP3_6, VI3_D2_C2),
 589         PINMUX_IPSR_GPSR(IP3_6, AVB_GTX_CLK),
 590         PINMUX_IPSR_GPSR(IP3_7, VI3_D3_C3),
 591         PINMUX_IPSR_GPSR(IP3_7, AVB_MDC),
 592         PINMUX_IPSR_GPSR(IP3_8, VI3_D4_C4),
 593         PINMUX_IPSR_GPSR(IP3_8, AVB_MDIO),
 594         PINMUX_IPSR_GPSR(IP3_9, VI3_D5_C5),
 595         PINMUX_IPSR_GPSR(IP3_9, AVB_LINK),
 596         PINMUX_IPSR_GPSR(IP3_10, VI3_D6_C6),
 597         PINMUX_IPSR_GPSR(IP3_10, AVB_MAGIC),
 598         PINMUX_IPSR_GPSR(IP3_11, VI3_D7_C7),
 599         PINMUX_IPSR_GPSR(IP3_11, AVB_PHY_INT),
 600         PINMUX_IPSR_GPSR(IP3_12, VI3_D8_Y0),
 601         PINMUX_IPSR_GPSR(IP3_12, AVB_CRS),
 602         PINMUX_IPSR_GPSR(IP3_13, VI3_D9_Y1),
 603         PINMUX_IPSR_GPSR(IP3_13, AVB_GTXREFCLK),
 604         PINMUX_IPSR_GPSR(IP3_14, VI3_D11_Y3),
 605         PINMUX_IPSR_GPSR(IP3_14, AVB_AVTP_MATCH),
 606
 607         /* IPSR4 */
 608         PINMUX_IPSR_GPSR(IP4_0, VI4_CLKENB),
 609         PINMUX_IPSR_GPSR(IP4_0, VI0_D12_G4_Y4),
 610         PINMUX_IPSR_GPSR(IP4_1, VI4_HSYNC_N),
 611         PINMUX_IPSR_GPSR(IP4_1, VI0_D13_G5_Y5),
 612         PINMUX_IPSR_GPSR(IP4_3_2, VI4_VSYNC_N),
 613         PINMUX_IPSR_GPSR(IP4_3_2, VI0_D14_G6_Y6),
 614         PINMUX_IPSR_GPSR(IP4_4, VI4_D0_C0),
 615         PINMUX_IPSR_GPSR(IP4_4, VI0_D15_G7_Y7),
 616         PINMUX_IPSR_GPSR(IP4_6_5, VI4_D1_C1),
 617         PINMUX_IPSR_GPSR(IP4_6_5, VI0_D16_R0),
 618         PINMUX_IPSR_MSEL(IP4_6_5, VI1_D12_G4_Y4, SEL_VI1_0),
 619         PINMUX_IPSR_GPSR(IP4_8_7, VI4_D2_C2),
 620         PINMUX_IPSR_GPSR(IP4_8_7, VI0_D17_R1),
 621         PINMUX_IPSR_MSEL(IP4_8_7, VI1_D13_G5_Y5, SEL_VI1_0),
 622         PINMUX_IPSR_GPSR(IP4_10_9, VI4_D3_C3),
 623         PINMUX_IPSR_GPSR(IP4_10_9, VI0_D18_R2),
 624         PINMUX_IPSR_MSEL(IP4_10_9, VI1_D14_G6_Y6, SEL_VI1_0),
 625         PINMUX_IPSR_GPSR(IP4_12_11, VI4_D4_C4),
 626         PINMUX_IPSR_GPSR(IP4_12_11, VI0_D19_R3),
 627         PINMUX_IPSR_MSEL(IP4_12_11, VI1_D15_G7_Y7, SEL_VI1_0),
 628         PINMUX_IPSR_GPSR(IP4_14_13, VI4_D5_C5),
 629         PINMUX_IPSR_GPSR(IP4_14_13, VI0_D20_R4),
 630         PINMUX_IPSR_GPSR(IP4_14_13, VI2_D12_Y4),
 631         PINMUX_IPSR_GPSR(IP4_16_15, VI4_D6_C6),
 632         PINMUX_IPSR_GPSR(IP4_16_15, VI0_D21_R5),
 633         PINMUX_IPSR_GPSR(IP4_16_15, VI2_D13_Y5),
 634         PINMUX_IPSR_GPSR(IP4_18_17, VI4_D7_C7),
 635         PINMUX_IPSR_GPSR(IP4_18_17, VI0_D22_R6),
 636         PINMUX_IPSR_GPSR(IP4_18_17, VI2_D14_Y6),
 637         PINMUX_IPSR_GPSR(IP4_20_19, VI4_D8_Y0),
 638         PINMUX_IPSR_GPSR(IP4_20_19, VI0_D23_R7),
 639         PINMUX_IPSR_GPSR(IP4_20_19, VI2_D15_Y7),
 640         PINMUX_IPSR_GPSR(IP4_21, VI4_D9_Y1),
 641         PINMUX_IPSR_GPSR(IP4_21, VI3_D12_Y4),
 642         PINMUX_IPSR_GPSR(IP4_22, VI4_D10_Y2),
 643         PINMUX_IPSR_GPSR(IP4_22, VI3_D13_Y5),
 644         PINMUX_IPSR_GPSR(IP4_23, VI4_D11_Y3),
 645         PINMUX_IPSR_GPSR(IP4_23, VI3_D14_Y6),
 646         PINMUX_IPSR_GPSR(IP4_24, VI4_FIELD),
 647         PINMUX_IPSR_GPSR(IP4_24, VI3_D15_Y7),
 648
 649         /* IPSR5 */
 650         PINMUX_IPSR_GPSR(IP5_0, VI5_CLKENB),
 651         PINMUX_IPSR_MSEL(IP5_0, VI1_D12_G4_Y4_B, SEL_VI1_1),
 652         PINMUX_IPSR_GPSR(IP5_1, VI5_HSYNC_N),
 653         PINMUX_IPSR_MSEL(IP5_1, VI1_D13_G5_Y5_B, SEL_VI1_1),
 654         PINMUX_IPSR_GPSR(IP5_2, VI5_VSYNC_N),
 655         PINMUX_IPSR_MSEL(IP5_2, VI1_D14_G6_Y6_B, SEL_VI1_1),
 656         PINMUX_IPSR_GPSR(IP5_3, VI5_D0_C0),
 657         PINMUX_IPSR_MSEL(IP5_3, VI1_D15_G7_Y7_B, SEL_VI1_1),
 658         PINMUX_IPSR_GPSR(IP5_4, VI5_D1_C1),
 659         PINMUX_IPSR_GPSR(IP5_4, VI1_D16_R0),
 660         PINMUX_IPSR_GPSR(IP5_5, VI5_D2_C2),
 661         PINMUX_IPSR_GPSR(IP5_5, VI1_D17_R1),
 662         PINMUX_IPSR_GPSR(IP5_6, VI5_D3_C3),
 663         PINMUX_IPSR_GPSR(IP5_6, VI1_D18_R2),
 664         PINMUX_IPSR_GPSR(IP5_7, VI5_D4_C4),
 665         PINMUX_IPSR_GPSR(IP5_7, VI1_D19_R3),
 666         PINMUX_IPSR_GPSR(IP5_8, VI5_D5_C5),
 667         PINMUX_IPSR_GPSR(IP5_8, VI1_D20_R4),
 668         PINMUX_IPSR_GPSR(IP5_9, VI5_D6_C6),
 669         PINMUX_IPSR_GPSR(IP5_9, VI1_D21_R5),
 670         PINMUX_IPSR_GPSR(IP5_10, VI5_D7_C7),
 671         PINMUX_IPSR_GPSR(IP5_10, VI1_D22_R6),
 672         PINMUX_IPSR_GPSR(IP5_11, VI5_D8_Y0),
 673         PINMUX_IPSR_GPSR(IP5_11, VI1_D23_R7),
 674
 675         /* IPSR6 */
 676         PINMUX_IPSR_GPSR(IP6_0, MSIOF0_SCK),
 677         PINMUX_IPSR_GPSR(IP6_0, HSCK0),
 678         PINMUX_IPSR_GPSR(IP6_1, MSIOF0_SYNC),
 679         PINMUX_IPSR_GPSR(IP6_1, HCTS0_N),
 680         PINMUX_IPSR_GPSR(IP6_2, MSIOF0_TXD),
 681         PINMUX_IPSR_GPSR(IP6_2, HTX0),
 682         PINMUX_IPSR_GPSR(IP6_3, MSIOF0_RXD),
 683         PINMUX_IPSR_GPSR(IP6_3, HRX0),
 684         PINMUX_IPSR_GPSR(IP6_4, MSIOF1_SCK),
 685         PINMUX_IPSR_GPSR(IP6_4, HSCK1),
 686         PINMUX_IPSR_GPSR(IP6_5, MSIOF1_SYNC),
 687         PINMUX_IPSR_GPSR(IP6_5, HRTS1_N),
 688         PINMUX_IPSR_GPSR(IP6_6, MSIOF1_TXD),
 689         PINMUX_IPSR_GPSR(IP6_6, HTX1),
 690         PINMUX_IPSR_GPSR(IP6_7, MSIOF1_RXD),
 691         PINMUX_IPSR_GPSR(IP6_7, HRX1),
 692         PINMUX_IPSR_GPSR(IP6_9_8, DRACK0),
 693         PINMUX_IPSR_GPSR(IP6_9_8, SCK2),
 694         PINMUX_IPSR_GPSR(IP6_11_10, DACK0),
 695         PINMUX_IPSR_GPSR(IP6_11_10, TX2),
 696         PINMUX_IPSR_GPSR(IP6_13_12, DREQ0_N),
 697         PINMUX_IPSR_GPSR(IP6_13_12, RX2),
 698         PINMUX_IPSR_GPSR(IP6_15_14, DACK1),
 699         PINMUX_IPSR_GPSR(IP6_15_14, SCK3),
 700         PINMUX_IPSR_GPSR(IP6_16, TX3),
 701         PINMUX_IPSR_GPSR(IP6_18_17, DREQ1_N),
 702         PINMUX_IPSR_GPSR(IP6_18_17, RX3),
 703
 704         /* IPSR7 */
 705         PINMUX_IPSR_GPSR(IP7_1_0, PWM0),
 706         PINMUX_IPSR_GPSR(IP7_1_0, TCLK1),
 707         PINMUX_IPSR_GPSR(IP7_1_0, FSO_CFE_0),
 708         PINMUX_IPSR_GPSR(IP7_3_2, PWM1),
 709         PINMUX_IPSR_GPSR(IP7_3_2, TCLK2),
 710         PINMUX_IPSR_GPSR(IP7_3_2, FSO_CFE_1),
 711         PINMUX_IPSR_GPSR(IP7_5_4, PWM2),
 712         PINMUX_IPSR_GPSR(IP7_5_4, TCLK3),
 713         PINMUX_IPSR_GPSR(IP7_5_4, FSO_TOE),
 714         PINMUX_IPSR_GPSR(IP7_6, PWM3),
 715         PINMUX_IPSR_GPSR(IP7_7, PWM4),
 716         PINMUX_IPSR_GPSR(IP7_9_8, SSI_SCK34),
 717         PINMUX_IPSR_GPSR(IP7_9_8, TPU0TO0),
 718         PINMUX_IPSR_GPSR(IP7_11_10, SSI_WS34),
 719         PINMUX_IPSR_GPSR(IP7_11_10, TPU0TO1),
 720         PINMUX_IPSR_GPSR(IP7_13_12, SSI_SDATA3),
 721         PINMUX_IPSR_GPSR(IP7_13_12, TPU0TO2),
 722         PINMUX_IPSR_GPSR(IP7_15_14, SSI_SCK4),
 723         PINMUX_IPSR_GPSR(IP7_15_14, TPU0TO3),
 724         PINMUX_IPSR_GPSR(IP7_16, SSI_WS4),
 725         PINMUX_IPSR_GPSR(IP7_17, SSI_SDATA4),
 726         PINMUX_IPSR_GPSR(IP7_18, AUDIO_CLKOUT),
 727         PINMUX_IPSR_GPSR(IP7_19, AUDIO_CLKA),
 728         PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB),
 729 };
 730
 731 static const struct sh_pfc_pin pinmux_pins[] = {
 732         PINMUX_GPIO_GP_ALL(),
 733 };
 734
 735 /* - AVB -------------------------------------------------------------------- */
 736 static const unsigned int avb_link_pins[] = {
 737         RCAR_GP_PIN(7, 9),
 738 };
 739 static const unsigned int avb_link_mux[] = {
 740         AVB_LINK_MARK,
 741 };
 742 static const unsigned int avb_magic_pins[] = {
 743         RCAR_GP_PIN(7, 10),
 744 };
 745 static const unsigned int avb_magic_mux[] = {
 746         AVB_MAGIC_MARK,
 747 };
 748 static const unsigned int avb_phy_int_pins[] = {
 749         RCAR_GP_PIN(7, 11),
 750 };
 751 static const unsigned int avb_phy_int_mux[] = {
 752         AVB_PHY_INT_MARK,
 753 };
 754 static const unsigned int avb_mdio_pins[] = {
 755         RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8),
 756 };
 757 static const unsigned int avb_mdio_mux[] = {
 758         AVB_MDC_MARK, AVB_MDIO_MARK,
 759 };
 760 static const unsigned int avb_mii_pins[] = {
 761         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
 762         RCAR_GP_PIN(6, 12),
 763
 764         RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 3),  RCAR_GP_PIN(6, 4),
 765         RCAR_GP_PIN(6, 5),
 766
 767         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0),  RCAR_GP_PIN(6, 1),
 768         RCAR_GP_PIN(7, 12), RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5),
 769         RCAR_GP_PIN(7, 0),  RCAR_GP_PIN(6, 11),
 770 };
 771 static const unsigned int avb_mii_mux[] = {
 772         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
 773         AVB_TXD3_MARK,
 774
 775         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
 776         AVB_RXD3_MARK,
 777
 778         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
 779         AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
 780         AVB_TX_CLK_MARK, AVB_COL_MARK,
 781 };
 782 static const unsigned int avb_gmii_pins[] = {
 783         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
 784         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(7, 1),  RCAR_GP_PIN(7, 2),
 785         RCAR_GP_PIN(7, 3),  RCAR_GP_PIN(7, 4),
 786
 787         RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
 788         RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
 789         RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 9),
 790
 791         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
 792         RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 13),
 793         RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 0),
 794         RCAR_GP_PIN(6, 11),
 795 };
 796 static const unsigned int avb_gmii_mux[] = {
 797         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
 798         AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
 799         AVB_TXD6_MARK, AVB_TXD7_MARK,
 800
 801         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
 802         AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
 803         AVB_RXD6_MARK, AVB_RXD7_MARK,
 804
 805         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
 806         AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
 807         AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
 808         AVB_COL_MARK,
 809 };
 810 static const unsigned int avb_avtp_match_pins[] = {
 811         RCAR_GP_PIN(7, 15),
 812 };
 813 static const unsigned int avb_avtp_match_mux[] = {
 814         AVB_AVTP_MATCH_MARK,
 815 };
 816 /* - CAN -------------------------------------------------------------------- */
 817 static const unsigned int can0_data_pins[] = {
 818         /* TX, RX */
 819         RCAR_GP_PIN(10, 27), RCAR_GP_PIN(10, 28),
 820 };
 821 static const unsigned int can0_data_mux[] = {
 822         CAN0_TX_MARK, CAN0_RX_MARK,
 823 };
 824 static const unsigned int can1_data_pins[] = {
 825         /* TX, RX */
 826         RCAR_GP_PIN(10, 30), RCAR_GP_PIN(10, 31),
 827 };
 828 static const unsigned int can1_data_mux[] = {
 829         CAN1_TX_MARK, CAN1_RX_MARK,
 830 };
 831 static const unsigned int can_clk_pins[] = {
 832         /* CAN_CLK */
 833         RCAR_GP_PIN(10, 29),
 834 };
 835 static const unsigned int can_clk_mux[] = {
 836         CAN_CLK_MARK,
 837 };
 838 /* - DU --------------------------------------------------------------------- */
 839 static const unsigned int du0_rgb666_pins[] = {
 840         /* R[7:2], G[7:2], B[7:2] */
 841         RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
 842         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
 843         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
 844         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
 845         RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
 846         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
 847 };
 848 static const unsigned int du0_rgb666_mux[] = {
 849         DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
 850         DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
 851         DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
 852         DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
 853         DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
 854         DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
 855 };
 856 static const unsigned int du0_rgb888_pins[] = {
 857         /* R[7:0], G[7:0], B[7:0] */
 858         RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
 859         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
 860         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
 861         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
 862         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
 863         RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
 864         RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
 865         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
 866         RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
 867 };
 868 static const unsigned int du0_rgb888_mux[] = {
 869         DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
 870         DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
 871         DU0_DR1_DATA1_MARK, DU0_DR0_DATA0_MARK,
 872         DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
 873         DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
 874         DU0_DG1_DATA9_MARK, DU0_DG0_DATA8_MARK,
 875         DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
 876         DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
 877         DU0_DB1_MARK, DU0_DB0_MARK,
 878 };
 879 static const unsigned int du0_sync_pins[] = {
 880         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
 881         RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 24),
 882 };
 883 static const unsigned int du0_sync_mux[] = {
 884         DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
 885 };
 886 static const unsigned int du0_oddf_pins[] = {
 887         /* EXODDF/ODDF/DISP/CDE */
 888         RCAR_GP_PIN(0, 26),
 889 };
 890 static const unsigned int du0_oddf_mux[] = {
 891         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
 892 };
 893 static const unsigned int du0_disp_pins[] = {
 894         /* DISP */
 895         RCAR_GP_PIN(0, 27),
 896 };
 897 static const unsigned int du0_disp_mux[] = {
 898         DU0_DISP_MARK,
 899 };
 900 static const unsigned int du0_cde_pins[] = {
 901         /* CDE */
 902         RCAR_GP_PIN(0, 28),
 903 };
 904 static const unsigned int du0_cde_mux[] = {
 905         DU0_CDE_MARK,
 906 };
 907 static const unsigned int du1_rgb666_pins[] = {
 908         /* R[7:2], G[7:2], B[7:2] */
 909         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
 910         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
 911         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
 912         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
 913         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
 914         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
 915 };
 916 static const unsigned int du1_rgb666_mux[] = {
 917         DU1_DR7_DATA5_MARK, DU1_DR6_DATA4_MARK, DU1_DR5_Y7_DATA3_MARK,
 918         DU1_DR4_Y6_DATA2_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR2_Y4_DATA0_MARK,
 919         DU1_DG7_Y3_DATA11_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG5_Y1_DATA9_MARK,
 920         DU1_DG4_Y0_DATA8_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG2_C6_DATA6_MARK,
 921         DU1_DB7_C5_MARK, DU1_DB6_C4_MARK, DU1_DB5_C3_DATA15_MARK,
 922         DU1_DB4_C2_DATA14_MARK, DU1_DB3_C1_DATA13_MARK, DU1_DB2_C0_DATA12_MARK,
 923 };
 924 static const unsigned int du1_sync_pins[] = {
 925         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
 926         RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
 927 };
 928 static const unsigned int du1_sync_mux[] = {
 929         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
 930 };
 931 static const unsigned int du1_oddf_pins[] = {
 932         /* EXODDF/ODDF/DISP/CDE */
 933         RCAR_GP_PIN(1, 20),
 934 };
 935 static const unsigned int du1_oddf_mux[] = {
 936         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
 937 };
 938 static const unsigned int du1_disp_pins[] = {
 939         /* DISP */
 940         RCAR_GP_PIN(1, 21),
 941 };
 942 static const unsigned int du1_disp_mux[] = {
 943         DU1_DISP_MARK,
 944 };
 945 static const unsigned int du1_cde_pins[] = {
 946         /* CDE */
 947         RCAR_GP_PIN(1, 22),
 948 };
 949 static const unsigned int du1_cde_mux[] = {
 950         DU1_CDE_MARK,
 951 };
 952 /* - INTC ------------------------------------------------------------------- */
 953 static const unsigned int intc_irq0_pins[] = {
 954         /* IRQ0 */
 955         RCAR_GP_PIN(3, 19),
 956 };
 957 static const unsigned int intc_irq0_mux[] = {
 958         IRQ0_MARK,
 959 };
 960 static const unsigned int intc_irq1_pins[] = {
 961         /* IRQ1 */
 962         RCAR_GP_PIN(3, 20),
 963 };
 964 static const unsigned int intc_irq1_mux[] = {
 965         IRQ1_MARK,
 966 };
 967 static const unsigned int intc_irq2_pins[] = {
 968         /* IRQ2 */
 969         RCAR_GP_PIN(3, 21),
 970 };
 971 static const unsigned int intc_irq2_mux[] = {
 972         IRQ2_MARK,
 973 };
 974 static const unsigned int intc_irq3_pins[] = {
 975         /* IRQ3 */
 976         RCAR_GP_PIN(3, 22),
 977 };
 978 static const unsigned int intc_irq3_mux[] = {
 979         IRQ3_MARK,
 980 };
 981 /* - LBSC ------------------------------------------------------------------- */
 982 static const unsigned int lbsc_cs0_pins[] = {
 983         /* CS0# */
 984         RCAR_GP_PIN(3, 27),
 985 };
 986 static const unsigned int lbsc_cs0_mux[] = {
 987         CS0_N_MARK,
 988 };
 989 static const unsigned int lbsc_cs1_pins[] = {
 990         /* CS1#_A26 */
 991         RCAR_GP_PIN(3, 6),
 992 };
 993 static const unsigned int lbsc_cs1_mux[] = {
 994         CS1_N_A26_MARK,
 995 };
 996 static const unsigned int lbsc_ex_cs0_pins[] = {
 997         /* EX_CS0# */
 998         RCAR_GP_PIN(3, 7),
 999 };
1000 static const unsigned int lbsc_ex_cs0_mux[] = {
1001         EX_CS0_N_MARK,
1002 };
1003 static const unsigned int lbsc_ex_cs1_pins[] = {
1004         /* EX_CS1# */
1005         RCAR_GP_PIN(3, 8),
1006 };
1007 static const unsigned int lbsc_ex_cs1_mux[] = {
1008         EX_CS1_N_MARK,
1009 };
1010 static const unsigned int lbsc_ex_cs2_pins[] = {
1011         /* EX_CS2# */
1012         RCAR_GP_PIN(3, 9),
1013 };
1014 static const unsigned int lbsc_ex_cs2_mux[] = {
1015         EX_CS2_N_MARK,
1016 };
1017 static const unsigned int lbsc_ex_cs3_pins[] = {
1018         /* EX_CS3# */
1019         RCAR_GP_PIN(3, 10),
1020 };
1021 static const unsigned int lbsc_ex_cs3_mux[] = {
1022         EX_CS3_N_MARK,
1023 };
1024 static const unsigned int lbsc_ex_cs4_pins[] = {
1025         /* EX_CS4# */
1026         RCAR_GP_PIN(3, 11),
1027 };
1028 static const unsigned int lbsc_ex_cs4_mux[] = {
1029         EX_CS4_N_MARK,
1030 };
1031 static const unsigned int lbsc_ex_cs5_pins[] = {
1032         /* EX_CS5# */
1033         RCAR_GP_PIN(3, 12),
1034 };
1035 static const unsigned int lbsc_ex_cs5_mux[] = {
1036         EX_CS5_N_MARK,
1037 };
1038 /* - MSIOF0 ----------------------------------------------------------------- */
1039 static const unsigned int msiof0_clk_pins[] = {
1040         /* SCK */
1041         RCAR_GP_PIN(10, 0),
1042 };
1043 static const unsigned int msiof0_clk_mux[] = {
1044         MSIOF0_SCK_MARK,
1045 };
1046 static const unsigned int msiof0_sync_pins[] = {
1047         /* SYNC */
1048         RCAR_GP_PIN(10, 1),
1049 };
1050 static const unsigned int msiof0_sync_mux[] = {
1051         MSIOF0_SYNC_MARK,
1052 };
1053 static const unsigned int msiof0_rx_pins[] = {
1054         /* RXD */
1055         RCAR_GP_PIN(10, 4),
1056 };
1057 static const unsigned int msiof0_rx_mux[] = {
1058         MSIOF0_RXD_MARK,
1059 };
1060 static const unsigned int msiof0_tx_pins[] = {
1061         /* TXD */
1062         RCAR_GP_PIN(10, 3),
1063 };
1064 static const unsigned int msiof0_tx_mux[] = {
1065         MSIOF0_TXD_MARK,
1066 };
1067 /* - MSIOF1 ----------------------------------------------------------------- */
1068 static const unsigned int msiof1_clk_pins[] = {
1069         /* SCK */
1070         RCAR_GP_PIN(10, 5),
1071 };
1072 static const unsigned int msiof1_clk_mux[] = {
1073         MSIOF1_SCK_MARK,
1074 };
1075 static const unsigned int msiof1_sync_pins[] = {
1076         /* SYNC */
1077         RCAR_GP_PIN(10, 6),
1078 };
1079 static const unsigned int msiof1_sync_mux[] = {
1080         MSIOF1_SYNC_MARK,
1081 };
1082 static const unsigned int msiof1_rx_pins[] = {
1083         /* RXD */
1084         RCAR_GP_PIN(10, 9),
1085 };
1086 static const unsigned int msiof1_rx_mux[] = {
1087         MSIOF1_RXD_MARK,
1088 };
1089 static const unsigned int msiof1_tx_pins[] = {
1090         /* TXD */
1091         RCAR_GP_PIN(10, 8),
1092 };
1093 static const unsigned int msiof1_tx_mux[] = {
1094         MSIOF1_TXD_MARK,
1095 };
1096 /* - QSPI ------------------------------------------------------------------- */
1097 static const unsigned int qspi_ctrl_pins[] = {
1098         /* SPCLK, SSL */
1099         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1100 };
1101 static const unsigned int qspi_ctrl_mux[] = {
1102         SPCLK_MARK, SSL_MARK,
1103 };
1104 static const unsigned int qspi_data2_pins[] = {
1105         /* MOSI_IO0, MISO_IO1 */
1106         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1107 };
1108 static const unsigned int qspi_data2_mux[] = {
1109         MOSI_IO0_MARK, MISO_IO1_MARK,
1110 };
1111 static const unsigned int qspi_data4_pins[] = {
1112         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1113         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
1114         RCAR_GP_PIN(3, 24),
1115 };
1116 static const unsigned int qspi_data4_mux[] = {
1117         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
1118 };
1119 /* - SCIF0 ------------------------------------------------------------------ */
1120 static const unsigned int scif0_data_pins[] = {
1121         /* RX, TX */
1122         RCAR_GP_PIN(10, 14), RCAR_GP_PIN(10, 13),
1123 };
1124 static const unsigned int scif0_data_mux[] = {
1125         RX0_MARK, TX0_MARK,
1126 };
1127 static const unsigned int scif0_clk_pins[] = {
1128         /* SCK */
1129         RCAR_GP_PIN(10, 10),
1130 };
1131 static const unsigned int scif0_clk_mux[] = {
1132         SCK0_MARK,
1133 };
1134 static const unsigned int scif0_ctrl_pins[] = {
1135         /* RTS, CTS */
1136         RCAR_GP_PIN(10, 12), RCAR_GP_PIN(10, 11),
1137 };
1138 static const unsigned int scif0_ctrl_mux[] = {
1139         RTS0_N_MARK, CTS0_N_MARK,
1140 };
1141 /* - SCIF1 ------------------------------------------------------------------ */
1142 static const unsigned int scif1_data_pins[] = {
1143         /* RX, TX */
1144         RCAR_GP_PIN(10, 19), RCAR_GP_PIN(10, 18),
1145 };
1146 static const unsigned int scif1_data_mux[] = {
1147         RX1_MARK, TX1_MARK,
1148 };
1149 static const unsigned int scif1_clk_pins[] = {
1150         /* SCK */
1151         RCAR_GP_PIN(10, 15),
1152 };
1153 static const unsigned int scif1_clk_mux[] = {
1154         SCK1_MARK,
1155 };
1156 static const unsigned int scif1_ctrl_pins[] = {
1157         /* RTS, CTS */
1158         RCAR_GP_PIN(10, 17), RCAR_GP_PIN(10, 16),
1159 };
1160 static const unsigned int scif1_ctrl_mux[] = {
1161         RTS1_N_MARK, CTS1_N_MARK,
1162 };
1163 /* - SCIF2 ------------------------------------------------------------------ */
1164 static const unsigned int scif2_data_pins[] = {
1165         /* RX, TX */
1166         RCAR_GP_PIN(10, 22), RCAR_GP_PIN(10, 21),
1167 };
1168 static const unsigned int scif2_data_mux[] = {
1169         RX2_MARK, TX2_MARK,
1170 };
1171 static const unsigned int scif2_clk_pins[] = {
1172         /* SCK */
1173         RCAR_GP_PIN(10, 20),
1174 };
1175 static const unsigned int scif2_clk_mux[] = {
1176         SCK2_MARK,
1177 };
1178 /* - SCIF3 ------------------------------------------------------------------ */
1179 static const unsigned int scif3_data_pins[] = {
1180         /* RX, TX */
1181         RCAR_GP_PIN(10, 25), RCAR_GP_PIN(10, 24),
1182 };
1183 static const unsigned int scif3_data_mux[] = {
1184         RX3_MARK, TX3_MARK,
1185 };
1186 static const unsigned int scif3_clk_pins[] = {
1187         /* SCK */
1188         RCAR_GP_PIN(10, 23),
1189 };
1190 static const unsigned int scif3_clk_mux[] = {
1191         SCK3_MARK,
1192 };
1193 /* - SDHI0 ------------------------------------------------------------------ */
1194 static const unsigned int sdhi0_data1_pins[] = {
1195         /* DAT0 */
1196         RCAR_GP_PIN(11, 7),
1197 };
1198 static const unsigned int sdhi0_data1_mux[] = {
1199         SD0_DAT0_MARK,
1200 };
1201 static const unsigned int sdhi0_data4_pins[] = {
1202         /* DAT[0-3] */
1203         RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
1204         RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
1205 };
1206 static const unsigned int sdhi0_data4_mux[] = {
1207         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
1208 };
1209 static const unsigned int sdhi0_ctrl_pins[] = {
1210         /* CLK, CMD */
1211         RCAR_GP_PIN(11, 5), RCAR_GP_PIN(11, 6),
1212 };
1213 static const unsigned int sdhi0_ctrl_mux[] = {
1214         SD0_CLK_MARK, SD0_CMD_MARK,
1215 };
1216 static const unsigned int sdhi0_cd_pins[] = {
1217         /* CD */
1218         RCAR_GP_PIN(11, 11),
1219 };
1220 static const unsigned int sdhi0_cd_mux[] = {
1221         SD0_CD_MARK,
1222 };
1223 static const unsigned int sdhi0_wp_pins[] = {
1224         /* WP */
1225         RCAR_GP_PIN(11, 12),
1226 };
1227 static const unsigned int sdhi0_wp_mux[] = {
1228         SD0_WP_MARK,
1229 };
1230 /* - VIN0 ------------------------------------------------------------------- */
1231 static const union vin_data vin0_data_pins = {
1232         .data24 = {
1233                 /* B */
1234                 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1235                 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1236                 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1237                 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1238                 /* G */
1239                 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1240                 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1241                 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1242                 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1243                 /* R */
1244                 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1245                 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1246                 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1247                 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1248         },
1249 };
1250 static const union vin_data vin0_data_mux = {
1251         .data24 = {
1252                 /* B */
1253                 VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
1254                 VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1255                 VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1256                 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1257                 /* G */
1258                 VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
1259                 VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1260                 VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1261                 VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1262                 /* R */
1263                 VI0_D16_R0_MARK, VI0_D17_R1_MARK,
1264                 VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1265                 VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1266                 VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1267         },
1268 };
1269 static const unsigned int vin0_data18_pins[] = {
1270         /* B */
1271         RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1272         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1273         RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1274         /* G */
1275         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1276         RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1277         RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1278         /* R */
1279         RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1280         RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1281         RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1282 };
1283 static const unsigned int vin0_data18_mux[] = {
1284         /* B */
1285         VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1286         VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1287         VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1288         /* G */
1289         VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1290         VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1291         VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1292         /* R */
1293         VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1294         VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1295         VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1296 };
1297 static const unsigned int vin0_sync_pins[] = {
1298         /* HSYNC#, VSYNC# */
1299         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1300 };
1301 static const unsigned int vin0_sync_mux[] = {
1302         VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1303 };
1304 static const unsigned int vin0_field_pins[] = {
1305         RCAR_GP_PIN(4, 16),
1306 };
1307 static const unsigned int vin0_field_mux[] = {
1308         VI0_FIELD_MARK,
1309 };
1310 static const unsigned int vin0_clkenb_pins[] = {
1311         RCAR_GP_PIN(4, 1),
1312 };
1313 static const unsigned int vin0_clkenb_mux[] = {
1314         VI0_CLKENB_MARK,
1315 };
1316 static const unsigned int vin0_clk_pins[] = {
1317         RCAR_GP_PIN(4, 0),
1318 };
1319 static const unsigned int vin0_clk_mux[] = {
1320         VI0_CLK_MARK,
1321 };
1322 /* - VIN1 ------------------------------------------------------------------- */
1323 static const union vin_data vin1_data_pins = {
1324         .data24 = {
1325                 /* B */
1326                 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1327                 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1328                 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1329                 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1330                 /* G */
1331                 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1332                 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1333                 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1334                 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1335                 /* R */
1336                 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1337                 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1338                 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1339                 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1340         },
1341 };
1342 static const union vin_data vin1_data_mux = {
1343         .data24 = {
1344                 /* B */
1345                 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1346                 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1347                 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1348                 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1349                 /* G */
1350                 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1351                 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1352                 VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1353                 VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1354                 /* R */
1355                 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1356                 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1357                 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1358                 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1359         },
1360 };
1361 static const unsigned int vin1_data18_pins[] = {
1362         /* B */
1363         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1364         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1365         RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1366         /* G */
1367         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1368         RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1369         RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1370         /* R */
1371         RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1372         RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1373         RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1374 };
1375 static const unsigned int vin1_data18_mux[] = {
1376         /* B */
1377         VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1378         VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1379         VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1380         /* G */
1381         VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1382         VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1383         VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1384         /* R */
1385         VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1386         VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1387         VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1388 };
1389 static const union vin_data vin1_data_b_pins = {
1390         .data24 = {
1391                 /* B */
1392                 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1393                 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1394                 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1395                 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1396                 /* G */
1397                 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1398                 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1399                 RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1400                 RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1401                 /* R */
1402                 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1403                 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1404                 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1405                 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1406         },
1407 };
1408 static const union vin_data vin1_data_b_mux = {
1409         .data24 = {
1410                 /* B */
1411                 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1412                 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1413                 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1414                 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1415                 /* G */
1416                 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1417                 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1418                 VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1419                 VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1420                 /* R */
1421                 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1422                 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1423                 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1424                 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1425         },
1426 };
1427 static const unsigned int vin1_data18_b_pins[] = {
1428         /* B */
1429         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1430         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1431         RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1432         /* G */
1433         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1434         RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1435         RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1436         /* R */
1437         RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1438         RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1439         RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1440 };
1441 static const unsigned int vin1_data18_b_mux[] = {
1442         /* B */
1443         VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1444         VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1445         VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1446         /* G */
1447         VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1448         VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1449         VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1450         /* R */
1451         VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1452         VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1453         VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1454 };
1455 static const unsigned int vin1_sync_pins[] = {
1456         /* HSYNC#, VSYNC# */
1457         RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
1458 };
1459 static const unsigned int vin1_sync_mux[] = {
1460         VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1461 };
1462 static const unsigned int vin1_field_pins[] = {
1463         RCAR_GP_PIN(5, 16),
1464 };
1465 static const unsigned int vin1_field_mux[] = {
1466         VI1_FIELD_MARK,
1467 };
1468 static const unsigned int vin1_clkenb_pins[] = {
1469         RCAR_GP_PIN(5, 1),
1470 };
1471 static const unsigned int vin1_clkenb_mux[] = {
1472         VI1_CLKENB_MARK,
1473 };
1474 static const unsigned int vin1_clk_pins[] = {
1475         RCAR_GP_PIN(5, 0),
1476 };
1477 static const unsigned int vin1_clk_mux[] = {
1478         VI1_CLK_MARK,
1479 };
1480 /* - VIN2 ------------------------------------------------------------------- */
1481 static const union vin_data vin2_data_pins = {
1482         .data16 = {
1483                 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1484                 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
1485                 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1486                 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
1487                 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
1488                 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1489                 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1490                 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1491         },
1492 };
1493 static const union vin_data vin2_data_mux = {
1494         .data16 = {
1495                 VI2_D0_C0_MARK, VI2_D1_C1_MARK,
1496                 VI2_D2_C2_MARK, VI2_D3_C3_MARK,
1497                 VI2_D4_C4_MARK, VI2_D5_C5_MARK,
1498                 VI2_D6_C6_MARK, VI2_D7_C7_MARK,
1499                 VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
1500                 VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
1501                 VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
1502                 VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
1503         },
1504 };
1505 static const unsigned int vin2_sync_pins[] = {
1506         /* HSYNC#, VSYNC# */
1507         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
1508 };
1509 static const unsigned int vin2_sync_mux[] = {
1510         VI2_HSYNC_N_MARK, VI2_VSYNC_N_MARK,
1511 };
1512 static const unsigned int vin2_field_pins[] = {
1513         RCAR_GP_PIN(6, 16),
1514 };
1515 static const unsigned int vin2_field_mux[] = {
1516         VI2_FIELD_MARK,
1517 };
1518 static const unsigned int vin2_clkenb_pins[] = {
1519         RCAR_GP_PIN(6, 1),
1520 };
1521 static const unsigned int vin2_clkenb_mux[] = {
1522         VI2_CLKENB_MARK,
1523 };
1524 static const unsigned int vin2_clk_pins[] = {
1525         RCAR_GP_PIN(6, 0),
1526 };
1527 static const unsigned int vin2_clk_mux[] = {
1528         VI2_CLK_MARK,
1529 };
1530 /* - VIN3 ------------------------------------------------------------------- */
1531 static const union vin_data vin3_data_pins = {
1532         .data16 = {
1533                 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1534                 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1535                 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1536                 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1537                 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
1538                 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
1539                 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
1540                 RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
1541         },
1542 };
1543 static const union vin_data vin3_data_mux = {
1544         .data16 = {
1545                 VI3_D0_C0_MARK, VI3_D1_C1_MARK,
1546                 VI3_D2_C2_MARK, VI3_D3_C3_MARK,
1547                 VI3_D4_C4_MARK, VI3_D5_C5_MARK,
1548                 VI3_D6_C6_MARK, VI3_D7_C7_MARK,
1549                 VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
1550                 VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
1551                 VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
1552                 VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
1553         },
1554 };
1555 static const unsigned int vin3_sync_pins[] = {
1556         /* HSYNC#, VSYNC# */
1557         RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
1558 };
1559 static const unsigned int vin3_sync_mux[] = {
1560         VI3_HSYNC_N_MARK, VI3_VSYNC_N_MARK,
1561 };
1562 static const unsigned int vin3_field_pins[] = {
1563         RCAR_GP_PIN(7, 16),
1564 };
1565 static const unsigned int vin3_field_mux[] = {
1566         VI3_FIELD_MARK,
1567 };
1568 static const unsigned int vin3_clkenb_pins[] = {
1569         RCAR_GP_PIN(7, 1),
1570 };
1571 static const unsigned int vin3_clkenb_mux[] = {
1572         VI3_CLKENB_MARK,
1573 };
1574 static const unsigned int vin3_clk_pins[] = {
1575         RCAR_GP_PIN(7, 0),
1576 };
1577 static const unsigned int vin3_clk_mux[] = {
1578         VI3_CLK_MARK,
1579 };
1580 /* - VIN4 ------------------------------------------------------------------- */
1581 static const union vin_data vin4_data_pins = {
1582         .data12 = {
1583                 RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1584                 RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
1585                 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1586                 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
1587                 RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
1588                 RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
1589         },
1590 };
1591 static const union vin_data vin4_data_mux = {
1592         .data12 = {
1593                 VI4_D0_C0_MARK, VI4_D1_C1_MARK,
1594                 VI4_D2_C2_MARK, VI4_D3_C3_MARK,
1595                 VI4_D4_C4_MARK, VI4_D5_C5_MARK,
1596                 VI4_D6_C6_MARK, VI4_D7_C7_MARK,
1597                 VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
1598                 VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
1599         },
1600 };
1601 static const unsigned int vin4_sync_pins[] = {
1602          /* HSYNC#, VSYNC# */
1603         RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
1604 };
1605 static const unsigned int vin4_sync_mux[] = {
1606         VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
1607 };
1608 static const unsigned int vin4_field_pins[] = {
1609         RCAR_GP_PIN(8, 16),
1610 };
1611 static const unsigned int vin4_field_mux[] = {
1612         VI4_FIELD_MARK,
1613 };
1614 static const unsigned int vin4_clkenb_pins[] = {
1615         RCAR_GP_PIN(8, 1),
1616 };
1617 static const unsigned int vin4_clkenb_mux[] = {
1618         VI4_CLKENB_MARK,
1619 };
1620 static const unsigned int vin4_clk_pins[] = {
1621         RCAR_GP_PIN(8, 0),
1622 };
1623 static const unsigned int vin4_clk_mux[] = {
1624         VI4_CLK_MARK,
1625 };
1626 /* - VIN5 ------------------------------------------------------------------- */
1627 static const union vin_data vin5_data_pins = {
1628         .data12 = {
1629                 RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1630                 RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1631                 RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1632                 RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1633                 RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
1634                 RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
1635         },
1636 };
1637 static const union vin_data vin5_data_mux = {
1638         .data12 = {
1639                 VI5_D0_C0_MARK, VI5_D1_C1_MARK,
1640                 VI5_D2_C2_MARK, VI5_D3_C3_MARK,
1641                 VI5_D4_C4_MARK, VI5_D5_C5_MARK,
1642                 VI5_D6_C6_MARK, VI5_D7_C7_MARK,
1643                 VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
1644                 VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
1645         },
1646 };
1647 static const unsigned int vin5_sync_pins[] = {
1648         /* HSYNC#, VSYNC# */
1649         RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
1650 };
1651 static const unsigned int vin5_sync_mux[] = {
1652         VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
1653 };
1654 static const unsigned int vin5_field_pins[] = {
1655         RCAR_GP_PIN(9, 16),
1656 };
1657 static const unsigned int vin5_field_mux[] = {
1658         VI5_FIELD_MARK,
1659 };
1660 static const unsigned int vin5_clkenb_pins[] = {
1661         RCAR_GP_PIN(9, 1),
1662 };
1663 static const unsigned int vin5_clkenb_mux[] = {
1664         VI5_CLKENB_MARK,
1665 };
1666 static const unsigned int vin5_clk_pins[] = {
1667         RCAR_GP_PIN(9, 0),
1668 };
1669 static const unsigned int vin5_clk_mux[] = {
1670         VI5_CLK_MARK,
1671 };
1672
1673 static const struct sh_pfc_pin_group pinmux_groups[] = {
1674         SH_PFC_PIN_GROUP(avb_link),
1675         SH_PFC_PIN_GROUP(avb_magic),
1676         SH_PFC_PIN_GROUP(avb_phy_int),
1677         SH_PFC_PIN_GROUP(avb_mdio),
1678         SH_PFC_PIN_GROUP(avb_mii),
1679         SH_PFC_PIN_GROUP(avb_gmii),
1680         SH_PFC_PIN_GROUP(avb_avtp_match),
1681         SH_PFC_PIN_GROUP(can0_data),
1682         SH_PFC_PIN_GROUP(can1_data),
1683         SH_PFC_PIN_GROUP(can_clk),
1684         SH_PFC_PIN_GROUP(du0_rgb666),
1685         SH_PFC_PIN_GROUP(du0_rgb888),
1686         SH_PFC_PIN_GROUP(du0_sync),
1687         SH_PFC_PIN_GROUP(du0_oddf),
1688         SH_PFC_PIN_GROUP(du0_disp),
1689         SH_PFC_PIN_GROUP(du0_cde),
1690         SH_PFC_PIN_GROUP(du1_rgb666),
1691         SH_PFC_PIN_GROUP(du1_sync),
1692         SH_PFC_PIN_GROUP(du1_oddf),
1693         SH_PFC_PIN_GROUP(du1_disp),
1694         SH_PFC_PIN_GROUP(du1_cde),
1695         SH_PFC_PIN_GROUP(intc_irq0),
1696         SH_PFC_PIN_GROUP(intc_irq1),
1697         SH_PFC_PIN_GROUP(intc_irq2),
1698         SH_PFC_PIN_GROUP(intc_irq3),
1699         SH_PFC_PIN_GROUP(lbsc_cs0),
1700         SH_PFC_PIN_GROUP(lbsc_cs1),
1701         SH_PFC_PIN_GROUP(lbsc_ex_cs0),
1702         SH_PFC_PIN_GROUP(lbsc_ex_cs1),
1703         SH_PFC_PIN_GROUP(lbsc_ex_cs2),
1704         SH_PFC_PIN_GROUP(lbsc_ex_cs3),
1705         SH_PFC_PIN_GROUP(lbsc_ex_cs4),
1706         SH_PFC_PIN_GROUP(lbsc_ex_cs5),
1707         SH_PFC_PIN_GROUP(msiof0_clk),
1708         SH_PFC_PIN_GROUP(msiof0_sync),
1709         SH_PFC_PIN_GROUP(msiof0_rx),
1710         SH_PFC_PIN_GROUP(msiof0_tx),
1711         SH_PFC_PIN_GROUP(msiof1_clk),
1712         SH_PFC_PIN_GROUP(msiof1_sync),
1713         SH_PFC_PIN_GROUP(msiof1_rx),
1714         SH_PFC_PIN_GROUP(msiof1_tx),
1715         SH_PFC_PIN_GROUP(qspi_ctrl),
1716         SH_PFC_PIN_GROUP(qspi_data2),
1717         SH_PFC_PIN_GROUP(qspi_data4),
1718         SH_PFC_PIN_GROUP(scif0_data),
1719         SH_PFC_PIN_GROUP(scif0_clk),
1720         SH_PFC_PIN_GROUP(scif0_ctrl),
1721         SH_PFC_PIN_GROUP(scif1_data),
1722         SH_PFC_PIN_GROUP(scif1_clk),
1723         SH_PFC_PIN_GROUP(scif1_ctrl),
1724         SH_PFC_PIN_GROUP(scif2_data),
1725         SH_PFC_PIN_GROUP(scif2_clk),
1726         SH_PFC_PIN_GROUP(scif3_data),
1727         SH_PFC_PIN_GROUP(scif3_clk),
1728         SH_PFC_PIN_GROUP(sdhi0_data1),
1729         SH_PFC_PIN_GROUP(sdhi0_data4),
1730         SH_PFC_PIN_GROUP(sdhi0_ctrl),
1731         SH_PFC_PIN_GROUP(sdhi0_cd),
1732         SH_PFC_PIN_GROUP(sdhi0_wp),
1733         VIN_DATA_PIN_GROUP(vin0_data, 24),
1734         VIN_DATA_PIN_GROUP(vin0_data, 20),
1735         SH_PFC_PIN_GROUP(vin0_data18),
1736         VIN_DATA_PIN_GROUP(vin0_data, 16),
1737         VIN_DATA_PIN_GROUP(vin0_data, 12),
1738         VIN_DATA_PIN_GROUP(vin0_data, 10),
1739         VIN_DATA_PIN_GROUP(vin0_data, 8),
1740         SH_PFC_PIN_GROUP(vin0_sync),
1741         SH_PFC_PIN_GROUP(vin0_field),
1742         SH_PFC_PIN_GROUP(vin0_clkenb),
1743         SH_PFC_PIN_GROUP(vin0_clk),
1744         VIN_DATA_PIN_GROUP(vin1_data, 24),
1745         VIN_DATA_PIN_GROUP(vin1_data, 20),
1746         SH_PFC_PIN_GROUP(vin1_data18),
1747         VIN_DATA_PIN_GROUP(vin1_data, 16),
1748         VIN_DATA_PIN_GROUP(vin1_data, 12),
1749         VIN_DATA_PIN_GROUP(vin1_data, 10),
1750         VIN_DATA_PIN_GROUP(vin1_data, 8),
1751         VIN_DATA_PIN_GROUP(vin1_data_b, 24),
1752         VIN_DATA_PIN_GROUP(vin1_data_b, 20),
1753         SH_PFC_PIN_GROUP(vin1_data18_b),
1754         VIN_DATA_PIN_GROUP(vin1_data_b, 16),
1755         SH_PFC_PIN_GROUP(vin1_sync),
1756         SH_PFC_PIN_GROUP(vin1_field),
1757         SH_PFC_PIN_GROUP(vin1_clkenb),
1758         SH_PFC_PIN_GROUP(vin1_clk),
1759         VIN_DATA_PIN_GROUP(vin2_data, 16),
1760         VIN_DATA_PIN_GROUP(vin2_data, 12),
1761         VIN_DATA_PIN_GROUP(vin2_data, 10),
1762         VIN_DATA_PIN_GROUP(vin2_data, 8),
1763         SH_PFC_PIN_GROUP(vin2_sync),
1764         SH_PFC_PIN_GROUP(vin2_field),
1765         SH_PFC_PIN_GROUP(vin2_clkenb),
1766         SH_PFC_PIN_GROUP(vin2_clk),
1767         VIN_DATA_PIN_GROUP(vin3_data, 16),
1768         VIN_DATA_PIN_GROUP(vin3_data, 12),
1769         VIN_DATA_PIN_GROUP(vin3_data, 10),
1770         VIN_DATA_PIN_GROUP(vin3_data, 8),
1771         SH_PFC_PIN_GROUP(vin3_sync),
1772         SH_PFC_PIN_GROUP(vin3_field),
1773         SH_PFC_PIN_GROUP(vin3_clkenb),
1774         SH_PFC_PIN_GROUP(vin3_clk),
1775         VIN_DATA_PIN_GROUP(vin4_data, 12),
1776         VIN_DATA_PIN_GROUP(vin4_data, 10),
1777         VIN_DATA_PIN_GROUP(vin4_data, 8),
1778         SH_PFC_PIN_GROUP(vin4_sync),
1779         SH_PFC_PIN_GROUP(vin4_field),
1780         SH_PFC_PIN_GROUP(vin4_clkenb),
1781         SH_PFC_PIN_GROUP(vin4_clk),
1782         VIN_DATA_PIN_GROUP(vin5_data, 12),
1783         VIN_DATA_PIN_GROUP(vin5_data, 10),
1784         VIN_DATA_PIN_GROUP(vin5_data, 8),
1785         SH_PFC_PIN_GROUP(vin5_sync),
1786         SH_PFC_PIN_GROUP(vin5_field),
1787         SH_PFC_PIN_GROUP(vin5_clkenb),
1788         SH_PFC_PIN_GROUP(vin5_clk),
1789 };
1790
1791 static const char * const avb_groups[] = {
1792         "avb_link",
1793         "avb_magic",
1794         "avb_phy_int",
1795         "avb_mdio",
1796         "avb_mii",
1797         "avb_gmii",
1798         "avb_avtp_match",
1799 };
1800
1801 static const char * const can0_groups[] = {
1802         "can0_data",
1803         "can_clk",
1804 };
1805
1806 static const char * const can1_groups[] = {
1807         "can1_data",
1808         "can_clk",
1809 };
1810
1811 static const char * const du0_groups[] = {
1812         "du0_rgb666",
1813         "du0_rgb888",
1814         "du0_sync",
1815         "du0_oddf",
1816         "du0_disp",
1817         "du0_cde",
1818 };
1819
1820 static const char * const du1_groups[] = {
1821         "du1_rgb666",
1822         "du1_sync",
1823         "du1_oddf",
1824         "du1_disp",
1825         "du1_cde",
1826 };
1827
1828 static const char * const intc_groups[] = {
1829         "intc_irq0",
1830         "intc_irq1",
1831         "intc_irq2",
1832         "intc_irq3",
1833 };
1834
1835 static const char * const lbsc_groups[] = {
1836         "lbsc_cs0",
1837         "lbsc_cs1",
1838         "lbsc_ex_cs0",
1839         "lbsc_ex_cs1",
1840         "lbsc_ex_cs2",
1841         "lbsc_ex_cs3",
1842         "lbsc_ex_cs4",
1843         "lbsc_ex_cs5",
1844 };
1845
1846 static const char * const msiof0_groups[] = {
1847         "msiof0_clk",
1848         "msiof0_sync",
1849         "msiof0_rx",
1850         "msiof0_tx",
1851 };
1852
1853 static const char * const msiof1_groups[] = {
1854         "msiof1_clk",
1855         "msiof1_sync",
1856         "msiof1_rx",
1857         "msiof1_tx",
1858 };
1859
1860 static const char * const qspi_groups[] = {
1861         "qspi_ctrl",
1862         "qspi_data2",
1863         "qspi_data4",
1864 };
1865
1866 static const char * const scif0_groups[] = {
1867         "scif0_data",
1868         "scif0_clk",
1869         "scif0_ctrl",
1870 };
1871
1872 static const char * const scif1_groups[] = {
1873         "scif1_data",
1874         "scif1_clk",
1875         "scif1_ctrl",
1876 };
1877
1878 static const char * const scif2_groups[] = {
1879         "scif2_data",
1880         "scif2_clk",
1881 };
1882
1883 static const char * const scif3_groups[] = {
1884         "scif3_data",
1885         "scif3_clk",
1886 };
1887
1888 static const char * const sdhi0_groups[] = {
1889         "sdhi0_data1",
1890         "sdhi0_data4",
1891         "sdhi0_ctrl",
1892         "sdhi0_cd",
1893         "sdhi0_wp",
1894 };
1895
1896 static const char * const vin0_groups[] = {
1897         "vin0_data24",
1898         "vin0_data20",
1899         "vin0_data18",
1900         "vin0_data16",
1901         "vin0_data12",
1902         "vin0_data10",
1903         "vin0_data8",
1904         "vin0_sync",
1905         "vin0_field",
1906         "vin0_clkenb",
1907         "vin0_clk",
1908 };
1909
1910 static const char * const vin1_groups[] = {
1911         "vin1_data24",
1912         "vin1_data20",
1913         "vin1_data18",
1914         "vin1_data16",
1915         "vin1_data12",
1916         "vin1_data10",
1917         "vin1_data8",
1918         "vin1_data24_b",
1919         "vin1_data20_b",
1920         "vin1_data16_b",
1921         "vin1_sync",
1922         "vin1_field",
1923         "vin1_clkenb",
1924         "vin1_clk",
1925 };
1926
1927 static const char * const vin2_groups[] = {
1928         "vin2_data16",
1929         "vin2_data12",
1930         "vin2_data10",
1931         "vin2_data8",
1932         "vin2_sync",
1933         "vin2_field",
1934         "vin2_clkenb",
1935         "vin2_clk",
1936 };
1937
1938 static const char * const vin3_groups[] = {
1939         "vin3_data16",
1940         "vin3_data12",
1941         "vin3_data10",
1942         "vin3_data8",
1943         "vin3_sync",
1944         "vin3_field",
1945         "vin3_clkenb",
1946         "vin3_clk",
1947 };
1948
1949 static const char * const vin4_groups[] = {
1950         "vin4_data12",
1951         "vin4_data10",
1952         "vin4_data8",
1953         "vin4_sync",
1954         "vin4_field",
1955         "vin4_clkenb",
1956         "vin4_clk",
1957 };
1958
1959 static const char * const vin5_groups[] = {
1960         "vin5_data12",
1961         "vin5_data10",
1962         "vin5_data8",
1963         "vin5_sync",
1964         "vin5_field",
1965         "vin5_clkenb",
1966         "vin5_clk",
1967 };
1968
1969 static const struct sh_pfc_function pinmux_functions[] = {
1970         SH_PFC_FUNCTION(avb),
1971         SH_PFC_FUNCTION(can0),
1972         SH_PFC_FUNCTION(can1),
1973         SH_PFC_FUNCTION(du0),
1974         SH_PFC_FUNCTION(du1),
1975         SH_PFC_FUNCTION(intc),
1976         SH_PFC_FUNCTION(lbsc),
1977         SH_PFC_FUNCTION(msiof0),
1978         SH_PFC_FUNCTION(msiof1),
1979         SH_PFC_FUNCTION(qspi),
1980         SH_PFC_FUNCTION(scif0),
1981         SH_PFC_FUNCTION(scif1),
1982         SH_PFC_FUNCTION(scif2),
1983         SH_PFC_FUNCTION(scif3),
1984         SH_PFC_FUNCTION(sdhi0),
1985         SH_PFC_FUNCTION(vin0),
1986         SH_PFC_FUNCTION(vin1),
1987         SH_PFC_FUNCTION(vin2),
1988         SH_PFC_FUNCTION(vin3),
1989         SH_PFC_FUNCTION(vin4),
1990         SH_PFC_FUNCTION(vin5),
1991 };
1992
1993 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1994         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
1995                 0, 0,
1996                 0, 0,
1997                 0, 0,
1998                 GP_0_28_FN, FN_IP1_4,
1999                 GP_0_27_FN, FN_IP1_3,
2000                 GP_0_26_FN, FN_IP1_2,
2001                 GP_0_25_FN, FN_IP1_1,
2002                 GP_0_24_FN, FN_IP1_0,
2003                 GP_0_23_FN, FN_IP0_23,
2004                 GP_0_22_FN, FN_IP0_22,
2005                 GP_0_21_FN, FN_IP0_21,
2006                 GP_0_20_FN, FN_IP0_20,
2007                 GP_0_19_FN, FN_IP0_19,
2008                 GP_0_18_FN, FN_IP0_18,
2009                 GP_0_17_FN, FN_IP0_17,
2010                 GP_0_16_FN, FN_IP0_16,
2011                 GP_0_15_FN, FN_IP0_15,
2012                 GP_0_14_FN, FN_IP0_14,
2013                 GP_0_13_FN, FN_IP0_13,
2014                 GP_0_12_FN, FN_IP0_12,
2015                 GP_0_11_FN, FN_IP0_11,
2016                 GP_0_10_FN, FN_IP0_10,
2017                 GP_0_9_FN, FN_IP0_9,
2018                 GP_0_8_FN, FN_IP0_8,
2019                 GP_0_7_FN, FN_IP0_7,
2020                 GP_0_6_FN, FN_IP0_6,
2021                 GP_0_5_FN, FN_IP0_5,
2022                 GP_0_4_FN, FN_IP0_4,
2023                 GP_0_3_FN, FN_IP0_3,
2024                 GP_0_2_FN, FN_IP0_2,
2025                 GP_0_1_FN, FN_IP0_1,
2026                 GP_0_0_FN, FN_IP0_0 }
2027         },
2028         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
2029                 0, 0,
2030                 0, 0,
2031                 0, 0,
2032                 0, 0,
2033                 0, 0,
2034                 0, 0,
2035                 0, 0,
2036                 0, 0,
2037                 0, 0,
2038                 GP_1_22_FN, FN_DU1_CDE,
2039                 GP_1_21_FN, FN_DU1_DISP,
2040                 GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
2041                 GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,
2042                 GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,
2043                 GP_1_17_FN, FN_DU1_DB7_C5,
2044                 GP_1_16_FN, FN_DU1_DB6_C4,
2045                 GP_1_15_FN, FN_DU1_DB5_C3_DATA15,
2046                 GP_1_14_FN, FN_DU1_DB4_C2_DATA14,
2047                 GP_1_13_FN, FN_DU1_DB3_C1_DATA13,
2048                 GP_1_12_FN, FN_DU1_DB2_C0_DATA12,
2049                 GP_1_11_FN, FN_IP1_16,
2050                 GP_1_10_FN, FN_IP1_15,
2051                 GP_1_9_FN, FN_IP1_14,
2052                 GP_1_8_FN, FN_IP1_13,
2053                 GP_1_7_FN, FN_IP1_12,
2054                 GP_1_6_FN, FN_IP1_11,
2055                 GP_1_5_FN, FN_IP1_10,
2056                 GP_1_4_FN, FN_IP1_9,
2057                 GP_1_3_FN, FN_IP1_8,
2058                 GP_1_2_FN, FN_IP1_7,
2059                 GP_1_1_FN, FN_IP1_6,
2060                 GP_1_0_FN, FN_IP1_5, }
2061         },
2062         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
2063                 GP_2_31_FN, FN_A15,
2064                 GP_2_30_FN, FN_A14,
2065                 GP_2_29_FN, FN_A13,
2066                 GP_2_28_FN, FN_A12,
2067                 GP_2_27_FN, FN_A11,
2068                 GP_2_26_FN, FN_A10,
2069                 GP_2_25_FN, FN_A9,
2070                 GP_2_24_FN, FN_A8,
2071                 GP_2_23_FN, FN_A7,
2072                 GP_2_22_FN, FN_A6,
2073                 GP_2_21_FN, FN_A5,
2074                 GP_2_20_FN, FN_A4,
2075                 GP_2_19_FN, FN_A3,
2076                 GP_2_18_FN, FN_A2,
2077                 GP_2_17_FN, FN_A1,
2078                 GP_2_16_FN, FN_A0,
2079                 GP_2_15_FN, FN_D15,
2080                 GP_2_14_FN, FN_D14,
2081                 GP_2_13_FN, FN_D13,
2082                 GP_2_12_FN, FN_D12,
2083                 GP_2_11_FN, FN_D11,
2084                 GP_2_10_FN, FN_D10,
2085                 GP_2_9_FN, FN_D9,
2086                 GP_2_8_FN, FN_D8,
2087                 GP_2_7_FN, FN_D7,
2088                 GP_2_6_FN, FN_D6,
2089                 GP_2_5_FN, FN_D5,
2090                 GP_2_4_FN, FN_D4,
2091                 GP_2_3_FN, FN_D3,
2092                 GP_2_2_FN, FN_D2,
2093                 GP_2_1_FN, FN_D1,
2094                 GP_2_0_FN, FN_D0 }
2095         },
2096         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
2097                 0, 0,
2098                 0, 0,
2099                 0, 0,
2100                 0, 0,
2101                 GP_3_27_FN, FN_CS0_N,
2102                 GP_3_26_FN, FN_IP1_22,
2103                 GP_3_25_FN, FN_IP1_21,
2104                 GP_3_24_FN, FN_IP1_20,
2105                 GP_3_23_FN, FN_IP1_19,
2106                 GP_3_22_FN, FN_IRQ3,
2107                 GP_3_21_FN, FN_IRQ2,
2108                 GP_3_20_FN, FN_IRQ1,
2109                 GP_3_19_FN, FN_IRQ0,
2110                 GP_3_18_FN, FN_EX_WAIT0,
2111                 GP_3_17_FN, FN_WE1_N,
2112                 GP_3_16_FN, FN_WE0_N,
2113                 GP_3_15_FN, FN_RD_WR_N,
2114                 GP_3_14_FN, FN_RD_N,
2115                 GP_3_13_FN, FN_BS_N,
2116                 GP_3_12_FN, FN_EX_CS5_N,
2117                 GP_3_11_FN, FN_EX_CS4_N,
2118                 GP_3_10_FN, FN_EX_CS3_N,
2119                 GP_3_9_FN, FN_EX_CS2_N,
2120                 GP_3_8_FN, FN_EX_CS1_N,
2121                 GP_3_7_FN, FN_EX_CS0_N,
2122                 GP_3_6_FN, FN_CS1_N_A26,
2123                 GP_3_5_FN, FN_IP1_18,
2124                 GP_3_4_FN, FN_IP1_17,
2125                 GP_3_3_FN, FN_A19,
2126                 GP_3_2_FN, FN_A18,
2127                 GP_3_1_FN, FN_A17,
2128                 GP_3_0_FN, FN_A16 }
2129         },
2130         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
2131                 0, 0,
2132                 0, 0,
2133                 0, 0,
2134                 0, 0,
2135                 0, 0,
2136                 0, 0,
2137                 0, 0,
2138                 0, 0,
2139                 0, 0,
2140                 0, 0,
2141                 0, 0,
2142                 0, 0,
2143                 0, 0,
2144                 0, 0,
2145                 0, 0,
2146                 GP_4_16_FN, FN_VI0_FIELD,
2147                 GP_4_15_FN, FN_VI0_D11_G3_Y3,
2148                 GP_4_14_FN, FN_VI0_D10_G2_Y2,
2149                 GP_4_13_FN, FN_VI0_D9_G1_Y1,
2150                 GP_4_12_FN, FN_VI0_D8_G0_Y0,
2151                 GP_4_11_FN, FN_VI0_D7_B7_C7,
2152                 GP_4_10_FN, FN_VI0_D6_B6_C6,
2153                 GP_4_9_FN, FN_VI0_D5_B5_C5,
2154                 GP_4_8_FN, FN_VI0_D4_B4_C4,
2155                 GP_4_7_FN, FN_VI0_D3_B3_C3,
2156                 GP_4_6_FN, FN_VI0_D2_B2_C2,
2157                 GP_4_5_FN, FN_VI0_D1_B1_C1,
2158                 GP_4_4_FN, FN_VI0_D0_B0_C0,
2159                 GP_4_3_FN, FN_VI0_VSYNC_N,
2160                 GP_4_2_FN, FN_VI0_HSYNC_N,
2161                 GP_4_1_FN, FN_VI0_CLKENB,
2162                 GP_4_0_FN, FN_VI0_CLK }
2163         },
2164         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
2165                 0, 0,
2166                 0, 0,
2167                 0, 0,
2168                 0, 0,
2169                 0, 0,
2170                 0, 0,
2171                 0, 0,
2172                 0, 0,
2173                 0, 0,
2174                 0, 0,
2175                 0, 0,
2176                 0, 0,
2177                 0, 0,
2178                 0, 0,
2179                 0, 0,
2180                 GP_5_16_FN, FN_VI1_FIELD,
2181                 GP_5_15_FN, FN_VI1_D11_G3_Y3,
2182                 GP_5_14_FN, FN_VI1_D10_G2_Y2,
2183                 GP_5_13_FN, FN_VI1_D9_G1_Y1,
2184                 GP_5_12_FN, FN_VI1_D8_G0_Y0,
2185                 GP_5_11_FN, FN_VI1_D7_B7_C7,
2186                 GP_5_10_FN, FN_VI1_D6_B6_C6,
2187                 GP_5_9_FN, FN_VI1_D5_B5_C5,
2188                 GP_5_8_FN, FN_VI1_D4_B4_C4,
2189                 GP_5_7_FN, FN_VI1_D3_B3_C3,
2190                 GP_5_6_FN, FN_VI1_D2_B2_C2,
2191                 GP_5_5_FN, FN_VI1_D1_B1_C1,
2192                 GP_5_4_FN, FN_VI1_D0_B0_C0,
2193                 GP_5_3_FN, FN_VI1_VSYNC_N,
2194                 GP_5_2_FN, FN_VI1_HSYNC_N,
2195                 GP_5_1_FN, FN_VI1_CLKENB,
2196                 GP_5_0_FN, FN_VI1_CLK }
2197         },
2198         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
2199                 0, 0,
2200                 0, 0,
2201                 0, 0,
2202                 0, 0,
2203                 0, 0,
2204                 0, 0,
2205                 0, 0,
2206                 0, 0,
2207                 0, 0,
2208                 0, 0,
2209                 0, 0,
2210                 0, 0,
2211                 0, 0,
2212                 0, 0,
2213                 0, 0,
2214                 GP_6_16_FN, FN_IP2_16,
2215                 GP_6_15_FN, FN_IP2_15,
2216                 GP_6_14_FN, FN_IP2_14,
2217                 GP_6_13_FN, FN_IP2_13,
2218                 GP_6_12_FN, FN_IP2_12,
2219                 GP_6_11_FN, FN_IP2_11,
2220                 GP_6_10_FN, FN_IP2_10,
2221                 GP_6_9_FN, FN_IP2_9,
2222                 GP_6_8_FN, FN_IP2_8,
2223                 GP_6_7_FN, FN_IP2_7,
2224                 GP_6_6_FN, FN_IP2_6,
2225                 GP_6_5_FN, FN_IP2_5,
2226                 GP_6_4_FN, FN_IP2_4,
2227                 GP_6_3_FN, FN_IP2_3,
2228                 GP_6_2_FN, FN_IP2_2,
2229                 GP_6_1_FN, FN_IP2_1,
2230                 GP_6_0_FN, FN_IP2_0 }
2231         },
2232         { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) {
2233                 0, 0,
2234                 0, 0,
2235                 0, 0,
2236                 0, 0,
2237                 0, 0,
2238                 0, 0,
2239                 0, 0,
2240                 0, 0,
2241                 0, 0,
2242                 0, 0,
2243                 0, 0,
2244                 0, 0,
2245                 0, 0,
2246                 0, 0,
2247                 0, 0,
2248                 GP_7_16_FN, FN_VI3_FIELD,
2249                 GP_7_15_FN, FN_IP3_14,
2250                 GP_7_14_FN, FN_VI3_D10_Y2,
2251                 GP_7_13_FN, FN_IP3_13,
2252                 GP_7_12_FN, FN_IP3_12,
2253                 GP_7_11_FN, FN_IP3_11,
2254                 GP_7_10_FN, FN_IP3_10,
2255                 GP_7_9_FN, FN_IP3_9,
2256                 GP_7_8_FN, FN_IP3_8,
2257                 GP_7_7_FN, FN_IP3_7,
2258                 GP_7_6_FN, FN_IP3_6,
2259                 GP_7_5_FN, FN_IP3_5,
2260                 GP_7_4_FN, FN_IP3_4,
2261                 GP_7_3_FN, FN_IP3_3,
2262                 GP_7_2_FN, FN_IP3_2,
2263                 GP_7_1_FN, FN_IP3_1,
2264                 GP_7_0_FN, FN_IP3_0 }
2265         },
2266         { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) {
2267                 0, 0,
2268                 0, 0,
2269                 0, 0,
2270                 0, 0,
2271                 0, 0,
2272                 0, 0,
2273                 0, 0,
2274                 0, 0,
2275                 0, 0,
2276                 0, 0,
2277                 0, 0,
2278                 0, 0,
2279                 0, 0,
2280                 0, 0,
2281                 0, 0,
2282                 GP_8_16_FN, FN_IP4_24,
2283                 GP_8_15_FN, FN_IP4_23,
2284                 GP_8_14_FN, FN_IP4_22,
2285                 GP_8_13_FN, FN_IP4_21,
2286                 GP_8_12_FN, FN_IP4_20_19,
2287                 GP_8_11_FN, FN_IP4_18_17,
2288                 GP_8_10_FN, FN_IP4_16_15,
2289                 GP_8_9_FN, FN_IP4_14_13,
2290                 GP_8_8_FN, FN_IP4_12_11,
2291                 GP_8_7_FN, FN_IP4_10_9,
2292                 GP_8_6_FN, FN_IP4_8_7,
2293                 GP_8_5_FN, FN_IP4_6_5,
2294                 GP_8_4_FN, FN_IP4_4,
2295                 GP_8_3_FN, FN_IP4_3_2,
2296                 GP_8_2_FN, FN_IP4_1,
2297                 GP_8_1_FN, FN_IP4_0,
2298                 GP_8_0_FN, FN_VI4_CLK }
2299         },
2300         { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) {
2301                 0, 0,
2302                 0, 0,
2303                 0, 0,
2304                 0, 0,
2305                 0, 0,
2306                 0, 0,
2307                 0, 0,
2308                 0, 0,
2309                 0, 0,
2310                 0, 0,
2311                 0, 0,
2312                 0, 0,
2313                 0, 0,
2314                 0, 0,
2315                 0, 0,
2316                 GP_9_16_FN, FN_VI5_FIELD,
2317                 GP_9_15_FN, FN_VI5_D11_Y3,
2318                 GP_9_14_FN, FN_VI5_D10_Y2,
2319                 GP_9_13_FN, FN_VI5_D9_Y1,
2320                 GP_9_12_FN, FN_IP5_11,
2321                 GP_9_11_FN, FN_IP5_10,
2322                 GP_9_10_FN, FN_IP5_9,
2323                 GP_9_9_FN, FN_IP5_8,
2324                 GP_9_8_FN, FN_IP5_7,
2325                 GP_9_7_FN, FN_IP5_6,
2326                 GP_9_6_FN, FN_IP5_5,
2327                 GP_9_5_FN, FN_IP5_4,
2328                 GP_9_4_FN, FN_IP5_3,
2329                 GP_9_3_FN, FN_IP5_2,
2330                 GP_9_2_FN, FN_IP5_1,
2331                 GP_9_1_FN, FN_IP5_0,
2332                 GP_9_0_FN, FN_VI5_CLK }
2333         },
2334         { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) {
2335                 GP_10_31_FN, FN_CAN1_RX,
2336                 GP_10_30_FN, FN_CAN1_TX,
2337                 GP_10_29_FN, FN_CAN_CLK,
2338                 GP_10_28_FN, FN_CAN0_RX,
2339                 GP_10_27_FN, FN_CAN0_TX,
2340                 GP_10_26_FN, FN_SCIF_CLK,
2341                 GP_10_25_FN, FN_IP6_18_17,
2342                 GP_10_24_FN, FN_IP6_16,
2343                 GP_10_23_FN, FN_IP6_15_14,
2344                 GP_10_22_FN, FN_IP6_13_12,
2345                 GP_10_21_FN, FN_IP6_11_10,
2346                 GP_10_20_FN, FN_IP6_9_8,
2347                 GP_10_19_FN, FN_RX1,
2348                 GP_10_18_FN, FN_TX1,
2349                 GP_10_17_FN, FN_RTS1_N,
2350                 GP_10_16_FN, FN_CTS1_N,
2351                 GP_10_15_FN, FN_SCK1,
2352                 GP_10_14_FN, FN_RX0,
2353                 GP_10_13_FN, FN_TX0,
2354                 GP_10_12_FN, FN_RTS0_N,
2355                 GP_10_11_FN, FN_CTS0_N,
2356                 GP_10_10_FN, FN_SCK0,
2357                 GP_10_9_FN, FN_IP6_7,
2358                 GP_10_8_FN, FN_IP6_6,
2359                 GP_10_7_FN, FN_HCTS1_N,
2360                 GP_10_6_FN, FN_IP6_5,
2361                 GP_10_5_FN, FN_IP6_4,
2362                 GP_10_4_FN, FN_IP6_3,
2363                 GP_10_3_FN, FN_IP6_2,
2364                 GP_10_2_FN, FN_HRTS0_N,
2365                 GP_10_1_FN, FN_IP6_1,
2366                 GP_10_0_FN, FN_IP6_0 }
2367         },
2368         { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) {
2369                 0, 0,
2370                 0, 0,
2371                 GP_11_29_FN, FN_AVS2,
2372                 GP_11_28_FN, FN_AVS1,
2373                 GP_11_27_FN, FN_ADICHS2,
2374                 GP_11_26_FN, FN_ADICHS1,
2375                 GP_11_25_FN, FN_ADICHS0,
2376                 GP_11_24_FN, FN_ADIDATA,
2377                 GP_11_23_FN, FN_ADICS_SAMP,
2378                 GP_11_22_FN, FN_ADICLK,
2379                 GP_11_21_FN, FN_IP7_20,
2380                 GP_11_20_FN, FN_IP7_19,
2381                 GP_11_19_FN, FN_IP7_18,
2382                 GP_11_18_FN, FN_IP7_17,
2383                 GP_11_17_FN, FN_IP7_16,
2384                 GP_11_16_FN, FN_IP7_15_14,
2385                 GP_11_15_FN, FN_IP7_13_12,
2386                 GP_11_14_FN, FN_IP7_11_10,
2387                 GP_11_13_FN, FN_IP7_9_8,
2388                 GP_11_12_FN, FN_SD0_WP,
2389                 GP_11_11_FN, FN_SD0_CD,
2390                 GP_11_10_FN, FN_SD0_DAT3,
2391                 GP_11_9_FN, FN_SD0_DAT2,
2392                 GP_11_8_FN, FN_SD0_DAT1,
2393                 GP_11_7_FN, FN_SD0_DAT0,
2394                 GP_11_6_FN, FN_SD0_CMD,
2395                 GP_11_5_FN, FN_SD0_CLK,
2396                 GP_11_4_FN, FN_IP7_7,
2397                 GP_11_3_FN, FN_IP7_6,
2398                 GP_11_2_FN, FN_IP7_5_4,
2399                 GP_11_1_FN, FN_IP7_3_2,
2400                 GP_11_0_FN, FN_IP7_1_0 }
2401         },
2402         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2403                              4, 4,
2404                              1, 1, 1, 1, 1, 1, 1, 1,
2405                              1, 1, 1, 1, 1, 1, 1, 1,
2406                              1, 1, 1, 1, 1, 1, 1, 1) {
2407                 /* IP0_31_28 [4] */
2408                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2409                 /* IP0_27_24 [4] */
2410                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2411                 /* IP0_23 [1] */
2412                 FN_DU0_DB7_C5, 0,
2413                 /* IP0_22 [1] */
2414                 FN_DU0_DB6_C4, 0,
2415                 /* IP0_21 [1] */
2416                 FN_DU0_DB5_C3, 0,
2417                 /* IP0_20 [1] */
2418                 FN_DU0_DB4_C2, 0,
2419                 /* IP0_19 [1] */
2420                 FN_DU0_DB3_C1, 0,
2421                 /* IP0_18 [1] */
2422                 FN_DU0_DB2_C0, 0,
2423                 /* IP0_17 [1] */
2424                 FN_DU0_DB1, 0,
2425                 /* IP0_16 [1] */
2426                 FN_DU0_DB0, 0,
2427                 /* IP0_15 [1] */
2428                 FN_DU0_DG7_Y3_DATA15, 0,
2429                 /* IP0_14 [1] */
2430                 FN_DU0_DG6_Y2_DATA14, 0,
2431                 /* IP0_13 [1] */
2432                 FN_DU0_DG5_Y1_DATA13, 0,
2433                 /* IP0_12 [1] */
2434                 FN_DU0_DG4_Y0_DATA12, 0,
2435                 /* IP0_11 [1] */
2436                 FN_DU0_DG3_C7_DATA11, 0,
2437                 /* IP0_10 [1] */
2438                 FN_DU0_DG2_C6_DATA10, 0,
2439                 /* IP0_9 [1] */
2440                 FN_DU0_DG1_DATA9, 0,
2441                 /* IP0_8 [1] */
2442                 FN_DU0_DG0_DATA8, 0,
2443                 /* IP0_7 [1] */
2444                 FN_DU0_DR7_Y9_DATA7, 0,
2445                 /* IP0_6 [1] */
2446                 FN_DU0_DR6_Y8_DATA6, 0,
2447                 /* IP0_5 [1] */
2448                 FN_DU0_DR5_Y7_DATA5, 0,
2449                 /* IP0_4 [1] */
2450                 FN_DU0_DR4_Y6_DATA4, 0,
2451                 /* IP0_3 [1] */
2452                 FN_DU0_DR3_Y5_DATA3, 0,
2453                 /* IP0_2 [1] */
2454                 FN_DU0_DR2_Y4_DATA2, 0,
2455                 /* IP0_1 [1] */
2456                 FN_DU0_DR1_DATA1, 0,
2457                 /* IP0_0 [1] */
2458                 FN_DU0_DR0_DATA0, 0 }
2459         },
2460         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2461                              4, 4,
2462                              1, 1, 1, 1, 1, 1, 1, 1,
2463                              1, 1, 1, 1, 1, 1, 1, 1,
2464                              1, 1, 1, 1, 1, 1, 1, 1) {
2465                 /* IP1_31_28 [4] */
2466                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2467                 /* IP1_27_24 [4] */
2468                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2469                 /* IP1_23 [1] */
2470                 0, 0,
2471                 /* IP1_22 [1] */
2472                 FN_A25, FN_SSL,
2473                 /* IP1_21 [1] */
2474                 FN_A24, FN_SPCLK,
2475                 /* IP1_20 [1] */
2476                 FN_A23, FN_IO3,
2477                 /* IP1_19 [1] */
2478                 FN_A22, FN_IO2,
2479                 /* IP1_18 [1] */
2480                 FN_A21, FN_MISO_IO1,
2481                 /* IP1_17 [1] */
2482                 FN_A20, FN_MOSI_IO0,
2483                 /* IP1_16 [1] */
2484                 FN_DU1_DG7_Y3_DATA11, 0,
2485                 /* IP1_15 [1] */
2486                 FN_DU1_DG6_Y2_DATA10, 0,
2487                 /* IP1_14 [1] */
2488                 FN_DU1_DG5_Y1_DATA9, 0,
2489                 /* IP1_13 [1] */
2490                 FN_DU1_DG4_Y0_DATA8, 0,
2491                 /* IP1_12 [1] */
2492                 FN_DU1_DG3_C7_DATA7, 0,
2493                 /* IP1_11 [1] */
2494                 FN_DU1_DG2_C6_DATA6, 0,
2495                 /* IP1_10 [1] */
2496                 FN_DU1_DR7_DATA5, 0,
2497                 /* IP1_9 [1] */
2498                 FN_DU1_DR6_DATA4, 0,
2499                 /* IP1_8 [1] */
2500                 FN_DU1_DR5_Y7_DATA3, 0,
2501                 /* IP1_7 [1] */
2502                 FN_DU1_DR4_Y6_DATA2, 0,
2503                 /* IP1_6 [1] */
2504                 FN_DU1_DR3_Y5_DATA1, 0,
2505                 /* IP1_5 [1] */
2506                 FN_DU1_DR2_Y4_DATA0, 0,
2507                 /* IP1_4 [1] */
2508                 FN_DU0_CDE, 0,
2509                 /* IP1_3 [1] */
2510                 FN_DU0_DISP, 0,
2511                 /* IP1_2 [1] */
2512                 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
2513                 /* IP1_1 [1] */
2514                 FN_DU0_EXVSYNC_DU0_VSYNC, 0,
2515                 /* IP1_0 [1] */
2516                 FN_DU0_EXHSYNC_DU0_HSYNC, 0 }
2517         },
2518         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2519                              4, 4,
2520                              4, 3, 1,
2521                              1, 1, 1, 1, 1, 1, 1, 1,
2522                              1, 1, 1, 1, 1, 1, 1, 1) {
2523                 /* IP2_31_28 [4] */
2524                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2525                 /* IP2_27_24 [4] */
2526                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2527                 /* IP2_23_20 [4] */
2528                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2529                 /* IP2_19_17 [3] */
2530                 0, 0, 0, 0, 0, 0, 0, 0,
2531                 /* IP2_16 [1] */
2532                 FN_VI2_FIELD, FN_AVB_TXD2,
2533                 /* IP2_15 [1] */
2534                 FN_VI2_D11_Y3, FN_AVB_TXD1,
2535                 /* IP2_14 [1] */
2536                 FN_VI2_D10_Y2, FN_AVB_TXD0,
2537                 /* IP2_13 [1] */
2538                 FN_VI2_D9_Y1, FN_AVB_TX_EN,
2539                 /* IP2_12 [1] */
2540                 FN_VI2_D8_Y0, FN_AVB_TXD3,
2541                 /* IP2_11 [1] */
2542                 FN_VI2_D7_C7, FN_AVB_COL,
2543                 /* IP2_10 [1] */
2544                 FN_VI2_D6_C6, FN_AVB_RX_ER,
2545                 /* IP2_9 [1] */
2546                 FN_VI2_D5_C5, FN_AVB_RXD7,
2547                 /* IP2_8 [1] */
2548                 FN_VI2_D4_C4, FN_AVB_RXD6,
2549                 /* IP2_7 [1] */
2550                 FN_VI2_D3_C3, FN_AVB_RXD5,
2551                 /* IP2_6 [1] */
2552                 FN_VI2_D2_C2, FN_AVB_RXD4,
2553                 /* IP2_5 [1] */
2554                 FN_VI2_D1_C1, FN_AVB_RXD3,
2555                 /* IP2_4 [1] */
2556                 FN_VI2_D0_C0, FN_AVB_RXD2,
2557                 /* IP2_3 [1] */
2558                 FN_VI2_VSYNC_N, FN_AVB_RXD1,
2559                 /* IP2_2 [1] */
2560                 FN_VI2_HSYNC_N, FN_AVB_RXD0,
2561                 /* IP2_1 [1] */
2562                 FN_VI2_CLKENB, FN_AVB_RX_DV,
2563                 /* IP2_0 [1] */
2564                 FN_VI2_CLK, FN_AVB_RX_CLK }
2565         },
2566         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2567                              4, 4,
2568                              4, 4,
2569                              1, 1, 1, 1, 1, 1, 1, 1,
2570                              1, 1, 1, 1, 1, 1, 1, 1) {
2571                 /* IP3_31_28 [4] */
2572                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2573                 /* IP3_27_24 [4] */
2574                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2575                 /* IP3_23_20 [4] */
2576                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2577                 /* IP3_19_16 [4] */
2578                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2579                 /* IP3_15 [1] */
2580                 0, 0,
2581                 /* IP3_14 [1] */
2582                 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
2583                 /* IP3_13 [1] */
2584                 FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
2585                 /* IP3_12 [1] */
2586                 FN_VI3_D8_Y0, FN_AVB_CRS,
2587                 /* IP3_11 [1] */
2588                 FN_VI3_D7_C7, FN_AVB_PHY_INT,
2589                 /* IP3_10 [1] */
2590                 FN_VI3_D6_C6, FN_AVB_MAGIC,
2591                 /* IP3_9 [1] */
2592                 FN_VI3_D5_C5, FN_AVB_LINK,
2593                 /* IP3_8 [1] */
2594                 FN_VI3_D4_C4, FN_AVB_MDIO,
2595                 /* IP3_7 [1] */
2596                 FN_VI3_D3_C3, FN_AVB_MDC,
2597                 /* IP3_6 [1] */
2598                 FN_VI3_D2_C2, FN_AVB_GTX_CLK,
2599                 /* IP3_5 [1] */
2600                 FN_VI3_D1_C1, FN_AVB_TX_ER,
2601                 /* IP3_4 [1] */
2602                 FN_VI3_D0_C0, FN_AVB_TXD7,
2603                 /* IP3_3 [1] */
2604                 FN_VI3_VSYNC_N, FN_AVB_TXD6,
2605                 /* IP3_2 [1] */
2606                 FN_VI3_HSYNC_N, FN_AVB_TXD5,
2607                 /* IP3_1 [1] */
2608                 FN_VI3_CLKENB, FN_AVB_TXD4,
2609                 /* IP3_0 [1] */
2610                 FN_VI3_CLK, FN_AVB_TX_CLK }
2611         },
2612         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2613                              4, 3, 1,
2614                              1, 1, 1, 2, 2, 2,
2615                              2, 2, 2, 2, 2, 1, 2, 1, 1) {
2616                 /* IP4_31_28 [4] */
2617                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2618                 /* IP4_27_25 [3] */
2619                 0, 0, 0, 0, 0, 0, 0, 0,
2620                 /* IP4_24 [1] */
2621                 FN_VI4_FIELD, FN_VI3_D15_Y7,
2622                 /* IP4_23 [1] */
2623                 FN_VI4_D11_Y3, FN_VI3_D14_Y6,
2624                 /* IP4_22 [1] */
2625                 FN_VI4_D10_Y2, FN_VI3_D13_Y5,
2626                 /* IP4_21 [1] */
2627                 FN_VI4_D9_Y1, FN_VI3_D12_Y4,
2628                 /* IP4_20_19 [2] */
2629                 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
2630                 /* IP4_18_17 [2] */
2631                 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
2632                 /* IP4_16_15 [2] */
2633                 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
2634                 /* IP4_14_13 [2] */
2635                 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
2636                 /* IP4_12_11 [2] */
2637                 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, 0,
2638                 /* IP4_10_9 [2] */
2639                 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, 0,
2640                 /* IP4_8_7 [2] */
2641                 FN_VI4_D2_C2, 0, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
2642                 /* IP4_6_5 [2] */
2643                 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, 0,
2644                 /* IP4_4 [1] */
2645                 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
2646                 /* IP4_3_2 [2] */
2647                 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, 0, 0,
2648                 /* IP4_1 [1] */
2649                 FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
2650                 /* IP4_0 [1] */
2651                 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 }
2652         },
2653         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2654                              4, 4,
2655                              4, 4,
2656                              4, 1, 1, 1, 1,
2657                              1, 1, 1, 1, 1, 1, 1, 1) {
2658                 /* IP5_31_28 [4] */
2659                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2660                 /* IP5_27_24 [4] */
2661                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2662                 /* IP5_23_20 [4] */
2663                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2664                 /* IP5_19_16 [4] */
2665                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2666                 /* IP5_15_12 [4] */
2667                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2668                 /* IP5_11 [1] */
2669                 FN_VI5_D8_Y0, FN_VI1_D23_R7,
2670                 /* IP5_10 [1] */
2671                 FN_VI5_D7_C7, FN_VI1_D22_R6,
2672                 /* IP5_9 [1] */
2673                 FN_VI5_D6_C6, FN_VI1_D21_R5,
2674                 /* IP5_8 [1] */
2675                 FN_VI5_D5_C5, FN_VI1_D20_R4,
2676                 /* IP5_7 [1] */
2677                 FN_VI5_D4_C4, FN_VI1_D19_R3,
2678                 /* IP5_6 [1] */
2679                 FN_VI5_D3_C3, FN_VI1_D18_R2,
2680                 /* IP5_5 [1] */
2681                 FN_VI5_D2_C2, FN_VI1_D17_R1,
2682                 /* IP5_4 [1] */
2683                 FN_VI5_D1_C1, FN_VI1_D16_R0,
2684                 /* IP5_3 [1] */
2685                 FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
2686                 /* IP5_2 [1] */
2687                 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B,
2688                 /* IP5_1 [1] */
2689                 FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
2690                 /* IP5_0 [1] */
2691                 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B }
2692         },
2693         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2694                              4, 4,
2695                              4, 1, 2, 1,
2696                              2, 2, 2, 2,
2697                              1, 1, 1, 1, 1, 1, 1, 1) {
2698                 /* IP6_31_28 [4] */
2699                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2700                 /* IP6_27_24 [4] */
2701                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2702                 /* IP6_23_20 [4] */
2703                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2704                 /* IP6_19 [1] */
2705                 0, 0,
2706                 /* IP6_18_17 [2] */
2707                 FN_DREQ1_N, FN_RX3, 0, 0,
2708                 /* IP6_16 [1] */
2709                 FN_TX3, 0,
2710                 /* IP6_15_14 [2] */
2711                 FN_DACK1, FN_SCK3, 0, 0,
2712                 /* IP6_13_12 [2] */
2713                 FN_DREQ0_N, FN_RX2, 0, 0,
2714                 /* IP6_11_10 [2] */
2715                 FN_DACK0, FN_TX2, 0, 0,
2716                 /* IP6_9_8 [2] */
2717                 FN_DRACK0, FN_SCK2, 0, 0,
2718                 /* IP6_7 [1] */
2719                 FN_MSIOF1_RXD, FN_HRX1,
2720                 /* IP6_6 [1] */
2721                 FN_MSIOF1_TXD, FN_HTX1,
2722                 /* IP6_5 [1] */
2723                 FN_MSIOF1_SYNC, FN_HRTS1_N,
2724                 /* IP6_4 [1] */
2725                 FN_MSIOF1_SCK, FN_HSCK1,
2726                 /* IP6_3 [1] */
2727                 FN_MSIOF0_RXD, FN_HRX0,
2728                 /* IP6_2 [1] */
2729                 FN_MSIOF0_TXD, FN_HTX0,
2730                 /* IP6_1 [1] */
2731                 FN_MSIOF0_SYNC, FN_HCTS0_N,
2732                 /* IP6_0 [1] */
2733                 FN_MSIOF0_SCK, FN_HSCK0 }
2734         },
2735         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
2736                              4, 4,
2737                              3, 1, 1, 1, 1, 1,
2738                              2, 2, 2, 2,
2739                              1, 1, 2, 2, 2) {
2740                 /* IP7_31_28 [4] */
2741                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2742                 /* IP7_27_24 [4] */
2743                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2744                 /* IP7_23_21 [3] */
2745                 0, 0, 0, 0, 0, 0, 0, 0,
2746                 /* IP7_20 [1] */
2747                 FN_AUDIO_CLKB, 0,
2748                 /* IP7_19 [1] */
2749                 FN_AUDIO_CLKA, 0,
2750                 /* IP7_18 [1] */
2751                 FN_AUDIO_CLKOUT, 0,
2752                 /* IP7_17 [1] */
2753                 FN_SSI_SDATA4, 0,
2754                 /* IP7_16 [1] */
2755                 FN_SSI_WS4, 0,
2756                 /* IP7_15_14 [2] */
2757                 FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
2758                 /* IP7_13_12 [2] */
2759                 FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
2760                 /* IP7_11_10 [2] */
2761                 FN_SSI_WS34, FN_TPU0TO1, 0, 0,
2762                 /* IP7_9_8 [2] */
2763                 FN_SSI_SCK34, FN_TPU0TO0, 0, 0,
2764                 /* IP7_7 [1] */
2765                 FN_PWM4, 0,
2766                 /* IP7_6 [1] */
2767                 FN_PWM3, 0,
2768                 /* IP7_5_4 [2] */
2769                 FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
2770                 /* IP7_3_2 [2] */
2771                 FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
2772                 /* IP7_1_0 [2] */
2773                 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 }
2774         },
2775         { },
2776 };
2777
2778 const struct sh_pfc_soc_info r8a7792_pinmux_info = {
2779         .name = "r8a77920_pfc",
2780         .unlock_reg = 0xe6060000, /* PMMR */
2781
2782         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2783
2784         .pins = pinmux_pins,
2785         .nr_pins = ARRAY_SIZE(pinmux_pins),
2786         .groups = pinmux_groups,
2787         .nr_groups = ARRAY_SIZE(pinmux_groups),
2788         .functions = pinmux_functions,
2789         .nr_functions = ARRAY_SIZE(pinmux_functions),
2790
2791         .cfg_regs = pinmux_config_regs,
2792
2793         .pinmux_data = pinmux_data,
2794         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2795 };