git.sur5r.net Git - u-boot/blob - drivers/pinctrl/renesas/pfc.c

   1 /*
   2  * Pin Control driver for SuperH Pin Function Controller.
   3  *
   4  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
   5  *
   6  * Copyright (C) 2008 Magnus Damm
   7  * Copyright (C) 2009 - 2012 Paul Mundt
   8  * Copyright (C) 2017 Marek Vasut
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0
  11  */
  12
  13 #define DRV_NAME "sh-pfc"
  14
  15 #include <common.h>
  16 #include <dm.h>
  17 #include <errno.h>
  18 #include <dm/pinctrl.h>
  19 #include <linux/io.h>
  20 #include <linux/sizes.h>
  21
  22 #include "sh_pfc.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 enum sh_pfc_model {
  27         SH_PFC_R8A7790 = 0,
  28         SH_PFC_R8A7791,
  29         SH_PFC_R8A7792,
  30         SH_PFC_R8A7793,
  31         SH_PFC_R8A7795,
  32         SH_PFC_R8A7796,
  33         SH_PFC_R8A77970,
  34         SH_PFC_R8A77995,
  35 };
  36
  37 struct sh_pfc_pin_config {
  38         u32 type;
  39 };
  40
  41 struct sh_pfc_pinctrl {
  42         struct sh_pfc *pfc;
  43
  44         struct sh_pfc_pin_config *configs;
  45
  46         const char *func_prop_name;
  47         const char *groups_prop_name;
  48         const char *pins_prop_name;
  49 };
  50
  51 struct sh_pfc_pin_range {
  52         u16 start;
  53         u16 end;
  54 };
  55
  56 struct sh_pfc_pinctrl_priv {
  57         struct sh_pfc                   pfc;
  58         struct sh_pfc_pinctrl           pmx;
  59 };
  60
  61 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
  62 {
  63         unsigned int offset;
  64         unsigned int i;
  65
  66         for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
  67                 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
  68
  69                 if (pin <= range->end)
  70                         return pin >= range->start
  71                              ? offset + pin - range->start : -1;
  72
  73                 offset += range->end - range->start + 1;
  74         }
  75
  76         return -EINVAL;
  77 }
  78
  79 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
  80 {
  81         if (enum_id < r->begin)
  82                 return 0;
  83
  84         if (enum_id > r->end)
  85                 return 0;
  86
  87         return 1;
  88 }
  89
  90 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
  91 {
  92         switch (reg_width) {
  93         case 8:
  94                 return readb(mapped_reg);
  95         case 16:
  96                 return readw(mapped_reg);
  97         case 32:
  98                 return readl(mapped_reg);
  99         }
 100
 101         BUG();
 102         return 0;
 103 }
 104
 105 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
 106                           u32 data)
 107 {
 108         switch (reg_width) {
 109         case 8:
 110                 writeb(data, mapped_reg);
 111                 return;
 112         case 16:
 113                 writew(data, mapped_reg);
 114                 return;
 115         case 32:
 116                 writel(data, mapped_reg);
 117                 return;
 118         }
 119
 120         BUG();
 121 }
 122
 123 u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width)
 124 {
 125         return sh_pfc_read_raw_reg(pfc->regs + reg, width);
 126 }
 127
 128 void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data)
 129 {
 130         void __iomem *unlock_reg =
 131                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 132
 133         if (pfc->info->unlock_reg)
 134                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 135
 136         sh_pfc_write_raw_reg(pfc->regs + reg, width, data);
 137 }
 138
 139 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
 140                                      const struct pinmux_cfg_reg *crp,
 141                                      unsigned int in_pos,
 142                                      void __iomem **mapped_regp, u32 *maskp,
 143                                      unsigned int *posp)
 144 {
 145         unsigned int k;
 146
 147         *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
 148
 149         if (crp->field_width) {
 150                 *maskp = (1 << crp->field_width) - 1;
 151                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 152         } else {
 153                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 154                 *posp = crp->reg_width;
 155                 for (k = 0; k <= in_pos; k++)
 156                         *posp -= crp->var_field_width[k];
 157         }
 158 }
 159
 160 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
 161                                     const struct pinmux_cfg_reg *crp,
 162                                     unsigned int field, u32 value)
 163 {
 164         void __iomem *mapped_reg;
 165         void __iomem *unlock_reg =
 166                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 167         unsigned int pos;
 168         u32 mask, data;
 169
 170         sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 171
 172         dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
 173                 "r_width = %u, f_width = %u\n",
 174                 crp->reg, value, field, crp->reg_width, crp->field_width);
 175
 176         mask = ~(mask << pos);
 177         value = value << pos;
 178
 179         data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
 180         data &= mask;
 181         data |= value;
 182
 183         if (pfc->info->unlock_reg)
 184                 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
 185
 186         sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
 187 }
 188
 189 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
 190                                  const struct pinmux_cfg_reg **crp,
 191                                  unsigned int *fieldp, u32 *valuep)
 192 {
 193         unsigned int k = 0;
 194
 195         while (1) {
 196                 const struct pinmux_cfg_reg *config_reg =
 197                         pfc->info->cfg_regs + k;
 198                 unsigned int r_width = config_reg->reg_width;
 199                 unsigned int f_width = config_reg->field_width;
 200                 unsigned int curr_width;
 201                 unsigned int bit_pos;
 202                 unsigned int pos = 0;
 203                 unsigned int m = 0;
 204
 205                 if (!r_width)
 206                         break;
 207
 208                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 209                         u32 ncomb;
 210                         u32 n;
 211
 212                         if (f_width)
 213                                 curr_width = f_width;
 214                         else
 215                                 curr_width = config_reg->var_field_width[m];
 216
 217                         ncomb = 1 << curr_width;
 218                         for (n = 0; n < ncomb; n++) {
 219                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 220                                         *crp = config_reg;
 221                                         *fieldp = m;
 222                                         *valuep = n;
 223                                         return 0;
 224                                 }
 225                         }
 226                         pos += ncomb;
 227                         m++;
 228                 }
 229                 k++;
 230         }
 231
 232         return -EINVAL;
 233 }
 234
 235 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
 236                               u16 *enum_idp)
 237 {
 238         const u16 *data = pfc->info->pinmux_data;
 239         unsigned int k;
 240
 241         if (pos) {
 242                 *enum_idp = data[pos + 1];
 243                 return pos + 1;
 244         }
 245
 246         for (k = 0; k < pfc->info->pinmux_data_size; k++) {
 247                 if (data[k] == mark) {
 248                         *enum_idp = data[k + 1];
 249                         return k + 1;
 250                 }
 251         }
 252
 253         dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
 254                 mark);
 255         return -EINVAL;
 256 }
 257
 258 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
 259 {
 260         const struct pinmux_range *range;
 261         int pos = 0;
 262
 263         switch (pinmux_type) {
 264         case PINMUX_TYPE_GPIO:
 265         case PINMUX_TYPE_FUNCTION:
 266                 range = NULL;
 267                 break;
 268
 269         case PINMUX_TYPE_OUTPUT:
 270                 range = &pfc->info->output;
 271                 break;
 272
 273         case PINMUX_TYPE_INPUT:
 274                 range = &pfc->info->input;
 275                 break;
 276
 277         default:
 278                 return -EINVAL;
 279         }
 280
 281         /* Iterate over all the configuration fields we need to update. */
 282         while (1) {
 283                 const struct pinmux_cfg_reg *cr;
 284                 unsigned int field;
 285                 u16 enum_id;
 286                 u32 value;
 287                 int in_range;
 288                 int ret;
 289
 290                 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
 291                 if (pos < 0)
 292                         return pos;
 293
 294                 if (!enum_id)
 295                         break;
 296
 297                 /* Check if the configuration field selects a function. If it
 298                  * doesn't, skip the field if it's not applicable to the
 299                  * requested pinmux type.
 300                  */
 301                 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
 302                 if (!in_range) {
 303                         if (pinmux_type == PINMUX_TYPE_FUNCTION) {
 304                                 /* Functions are allowed to modify all
 305                                  * fields.
 306                                  */
 307                                 in_range = 1;
 308                         } else if (pinmux_type != PINMUX_TYPE_GPIO) {
 309                                 /* Input/output types can only modify fields
 310                                  * that correspond to their respective ranges.
 311                                  */
 312                                 in_range = sh_pfc_enum_in_range(enum_id, range);
 313
 314                                 /*
 315                                  * special case pass through for fixed
 316                                  * input-only or output-only pins without
 317                                  * function enum register association.
 318                                  */
 319                                 if (in_range && enum_id == range->force)
 320                                         continue;
 321                         }
 322                         /* GPIOs are only allowed to modify function fields. */
 323                 }
 324
 325                 if (!in_range)
 326                         continue;
 327
 328                 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
 329                 if (ret < 0)
 330                         return ret;
 331
 332                 sh_pfc_write_config_reg(pfc, cr, field, value);
 333         }
 334
 335         return 0;
 336 }
 337
 338 const struct sh_pfc_bias_info *
 339 sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
 340                         unsigned int num, unsigned int pin)
 341 {
 342         unsigned int i;
 343
 344         for (i = 0; i < num; i++)
 345                 if (info[i].pin == pin)
 346                         return &info[i];
 347
 348         printf("Pin %u is not in bias info list\n", pin);
 349
 350         return NULL;
 351 }
 352
 353 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
 354 {
 355         struct sh_pfc_pin_range *range;
 356         unsigned int nr_ranges;
 357         unsigned int i;
 358
 359         if (pfc->info->pins[0].pin == (u16)-1) {
 360                 /* Pin number -1 denotes that the SoC doesn't report pin numbers
 361                  * in its pin arrays yet. Consider the pin numbers range as
 362                  * continuous and allocate a single range.
 363                  */
 364                 pfc->nr_ranges = 1;
 365                 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
 366                 if (pfc->ranges == NULL)
 367                         return -ENOMEM;
 368
 369                 pfc->ranges->start = 0;
 370                 pfc->ranges->end = pfc->info->nr_pins - 1;
 371                 pfc->nr_gpio_pins = pfc->info->nr_pins;
 372
 373                 return 0;
 374         }
 375
 376         /* Count, allocate and fill the ranges. The PFC SoC data pins array must
 377          * be sorted by pin numbers, and pins without a GPIO port must come
 378          * last.
 379          */
 380         for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
 381                 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
 382                         nr_ranges++;
 383         }
 384
 385         pfc->nr_ranges = nr_ranges;
 386         pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
 387         if (pfc->ranges == NULL)
 388                 return -ENOMEM;
 389
 390         range = pfc->ranges;
 391         range->start = pfc->info->pins[0].pin;
 392
 393         for (i = 1; i < pfc->info->nr_pins; ++i) {
 394                 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
 395                         continue;
 396
 397                 range->end = pfc->info->pins[i-1].pin;
 398                 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 399                         pfc->nr_gpio_pins = range->end + 1;
 400
 401                 range++;
 402                 range->start = pfc->info->pins[i].pin;
 403         }
 404
 405         range->end = pfc->info->pins[i-1].pin;
 406         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
 407                 pfc->nr_gpio_pins = range->end + 1;
 408
 409         return 0;
 410 }
 411
 412 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
 413 {
 414         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 415
 416         return priv->pfc.info->nr_pins;
 417 }
 418
 419 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
 420                                                   unsigned selector)
 421 {
 422         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 423
 424         return priv->pfc.info->pins[selector].name;
 425 }
 426
 427 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
 428 {
 429         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 430
 431         return priv->pfc.info->nr_groups;
 432 }
 433
 434 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
 435                                                   unsigned selector)
 436 {
 437         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 438
 439         return priv->pfc.info->groups[selector].name;
 440 }
 441
 442 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
 443 {
 444         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 445
 446         return priv->pfc.info->nr_functions;
 447 }
 448
 449 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
 450                                                   unsigned selector)
 451 {
 452         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 453
 454         return priv->pfc.info->functions[selector].name;
 455 }
 456
 457 int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector)
 458 {
 459         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 460         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 461         struct sh_pfc *pfc = &priv->pfc;
 462         struct sh_pfc_pin_config *cfg;
 463         const struct sh_pfc_pin *pin = NULL;
 464         int i, idx;
 465
 466         for (i = 1; i < pfc->info->nr_pins; i++) {
 467                 if (priv->pfc.info->pins[i].pin != pin_selector)
 468                         continue;
 469
 470                 pin = &priv->pfc.info->pins[i];
 471                 break;
 472         }
 473
 474         if (!pin)
 475                 return -EINVAL;
 476
 477         idx = sh_pfc_get_pin_index(pfc, pin->pin);
 478         cfg = &pmx->configs[idx];
 479
 480         if (cfg->type != PINMUX_TYPE_NONE)
 481                 return -EBUSY;
 482
 483         return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
 484 }
 485
 486 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
 487                                   unsigned func_selector)
 488 {
 489         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 490         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 491         struct sh_pfc *pfc = &priv->pfc;
 492         const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
 493         int idx = sh_pfc_get_pin_index(pfc, pin->pin);
 494         struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 495
 496         if (cfg->type != PINMUX_TYPE_NONE)
 497                 return -EBUSY;
 498
 499         return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
 500 }
 501
 502 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
 503                                      unsigned func_selector)
 504 {
 505         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 506         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 507         struct sh_pfc *pfc = &priv->pfc;
 508         const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
 509         unsigned int i;
 510         int ret = 0;
 511
 512         for (i = 0; i < grp->nr_pins; ++i) {
 513                 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
 514                 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
 515
 516                 if (cfg->type != PINMUX_TYPE_NONE) {
 517                         ret = -EBUSY;
 518                         goto done;
 519                 }
 520         }
 521
 522         for (i = 0; i < grp->nr_pins; ++i) {
 523                 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
 524                 if (ret < 0)
 525                         break;
 526         }
 527
 528 done:
 529         return ret;
 530 }
 531 #if CONFIG_IS_ENABLED(PINCONF)
 532 static const struct pinconf_param sh_pfc_pinconf_params[] = {
 533         { "bias-disable",       PIN_CONFIG_BIAS_DISABLE,        0 },
 534         { "bias-pull-up",       PIN_CONFIG_BIAS_PULL_UP,        1 },
 535         { "bias-pull-down",     PIN_CONFIG_BIAS_PULL_DOWN,      1 },
 536         { "drive-strength",     PIN_CONFIG_DRIVE_STRENGTH,      0 },
 537         { "power-source",       PIN_CONFIG_POWER_SOURCE,        3300 },
 538 };
 539
 540 static void __iomem *
 541 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
 542                                        unsigned int *offset, unsigned int *size)
 543 {
 544         const struct pinmux_drive_reg_field *field;
 545         const struct pinmux_drive_reg *reg;
 546         unsigned int i;
 547
 548         for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
 549                 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
 550                         field = &reg->fields[i];
 551
 552                         if (field->size && field->pin == pin) {
 553                                 *offset = field->offset;
 554                                 *size = field->size;
 555
 556                                 return (void __iomem *)(uintptr_t)reg->reg;
 557                         }
 558                 }
 559         }
 560
 561         return NULL;
 562 }
 563
 564 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
 565                                              unsigned int pin, u16 strength)
 566 {
 567         unsigned int offset;
 568         unsigned int size;
 569         unsigned int step;
 570         void __iomem *reg;
 571         void __iomem *unlock_reg =
 572                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 573         u32 val;
 574
 575         reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
 576         if (!reg)
 577                 return -EINVAL;
 578
 579         step = size == 2 ? 6 : 3;
 580
 581         if (strength < step || strength > 24)
 582                 return -EINVAL;
 583
 584         /* Convert the value from mA based on a full drive strength value of
 585          * 24mA. We can make the full value configurable later if needed.
 586          */
 587         strength = strength / step - 1;
 588
 589         val = sh_pfc_read_raw_reg(reg, 32);
 590         val &= ~GENMASK(offset + size - 1, offset);
 591         val |= strength << offset;
 592
 593         if (unlock_reg)
 594                 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 595
 596         sh_pfc_write_raw_reg(reg, 32, val);
 597
 598         return 0;
 599 }
 600
 601 /* Check whether the requested parameter is supported for a pin. */
 602 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
 603                                     unsigned int param)
 604 {
 605         int idx = sh_pfc_get_pin_index(pfc, _pin);
 606         const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
 607
 608         switch (param) {
 609         case PIN_CONFIG_BIAS_DISABLE:
 610                 return pin->configs &
 611                         (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
 612
 613         case PIN_CONFIG_BIAS_PULL_UP:
 614                 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
 615
 616         case PIN_CONFIG_BIAS_PULL_DOWN:
 617                 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
 618
 619         case PIN_CONFIG_DRIVE_STRENGTH:
 620                 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
 621
 622         case PIN_CONFIG_POWER_SOURCE:
 623                 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
 624
 625         default:
 626                 return false;
 627         }
 628 }
 629
 630 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
 631                               unsigned int param, unsigned int arg)
 632 {
 633         struct sh_pfc *pfc = pmx->pfc;
 634         void __iomem *pocctrl;
 635         void __iomem *unlock_reg =
 636                 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
 637         u32 addr, val;
 638         int bit, ret;
 639
 640         if (!sh_pfc_pinconf_validate(pfc, _pin, param))
 641                 return -ENOTSUPP;
 642
 643         switch (param) {
 644         case PIN_CONFIG_BIAS_PULL_UP:
 645         case PIN_CONFIG_BIAS_PULL_DOWN:
 646         case PIN_CONFIG_BIAS_DISABLE:
 647                 if (!pfc->info->ops || !pfc->info->ops->set_bias)
 648                         return -ENOTSUPP;
 649
 650                 pfc->info->ops->set_bias(pfc, _pin, param);
 651
 652                 break;
 653
 654         case PIN_CONFIG_DRIVE_STRENGTH:
 655                 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
 656                 if (ret < 0)
 657                         return ret;
 658
 659                 break;
 660
 661         case PIN_CONFIG_POWER_SOURCE:
 662                 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
 663                         return -ENOTSUPP;
 664
 665                 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
 666                 if (bit < 0) {
 667                         printf("invalid pin %#x", _pin);
 668                         return bit;
 669                 }
 670
 671                 if (arg != 1800 && arg != 3300)
 672                         return -EINVAL;
 673
 674                 pocctrl = (void __iomem *)(uintptr_t)addr;
 675
 676                 val = sh_pfc_read_raw_reg(pocctrl, 32);
 677                 if (arg == 3300)
 678                         val |= BIT(bit);
 679                 else
 680                         val &= ~BIT(bit);
 681
 682                 if (unlock_reg)
 683                         sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
 684
 685                 sh_pfc_write_raw_reg(pocctrl, 32, val);
 686
 687                 break;
 688
 689         default:
 690                 return -ENOTSUPP;
 691         }
 692
 693         return 0;
 694 }
 695
 696 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
 697                                   unsigned int pin_selector,
 698                                   unsigned int param, unsigned int arg)
 699 {
 700         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 701         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 702         struct sh_pfc *pfc = &priv->pfc;
 703         const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
 704
 705         sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
 706
 707         return 0;
 708 }
 709
 710 static int sh_pfc_pinconf_group_set(struct udevice *dev,
 711                                       unsigned int group_selector,
 712                                       unsigned int param, unsigned int arg)
 713 {
 714         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 715         struct sh_pfc_pinctrl *pmx = &priv->pmx;
 716         struct sh_pfc *pfc = &priv->pfc;
 717         const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
 718         unsigned int i;
 719
 720         for (i = 0; i < grp->nr_pins; i++)
 721                 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
 722
 723         return 0;
 724 }
 725 #endif
 726
 727 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
 728         .get_pins_count         = sh_pfc_pinctrl_get_pins_count,
 729         .get_pin_name           = sh_pfc_pinctrl_get_pin_name,
 730         .get_groups_count       = sh_pfc_pinctrl_get_groups_count,
 731         .get_group_name         = sh_pfc_pinctrl_get_group_name,
 732         .get_functions_count    = sh_pfc_pinctrl_get_functions_count,
 733         .get_function_name      = sh_pfc_pinctrl_get_function_name,
 734
 735 #if CONFIG_IS_ENABLED(PINCONF)
 736         .pinconf_num_params     = ARRAY_SIZE(sh_pfc_pinconf_params),
 737         .pinconf_params         = sh_pfc_pinconf_params,
 738         .pinconf_set            = sh_pfc_pinconf_pin_set,
 739         .pinconf_group_set      = sh_pfc_pinconf_group_set,
 740 #endif
 741         .pinmux_set             = sh_pfc_pinctrl_pin_set,
 742         .pinmux_group_set       = sh_pfc_pinctrl_group_set,
 743         .set_state              = pinctrl_generic_set_state,
 744 };
 745
 746 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
 747 {
 748         unsigned int i;
 749
 750         /* Allocate and initialize the pins and configs arrays. */
 751         pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
 752                                     GFP_KERNEL);
 753         if (unlikely(!pmx->configs))
 754                 return -ENOMEM;
 755
 756         for (i = 0; i < pfc->info->nr_pins; ++i) {
 757                 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
 758                 cfg->type = PINMUX_TYPE_NONE;
 759         }
 760
 761         return 0;
 762 }
 763
 764
 765 static int sh_pfc_pinctrl_probe(struct udevice *dev)
 766 {
 767         struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
 768         enum sh_pfc_model model = dev_get_driver_data(dev);
 769         fdt_addr_t base;
 770
 771         base = devfdt_get_addr(dev);
 772         if (base == FDT_ADDR_T_NONE)
 773                 return -EINVAL;
 774
 775         priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
 776         if (!priv->pfc.regs)
 777                 return -ENOMEM;
 778
 779 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 780         if (model == SH_PFC_R8A7790)
 781                 priv->pfc.info = &r8a7790_pinmux_info;
 782 #endif
 783 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 784         if (model == SH_PFC_R8A7791)
 785                 priv->pfc.info = &r8a7791_pinmux_info;
 786 #endif
 787 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 788         if (model == SH_PFC_R8A7792)
 789                 priv->pfc.info = &r8a7792_pinmux_info;
 790 #endif
 791 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 792         if (model == SH_PFC_R8A7793)
 793                 priv->pfc.info = &r8a7793_pinmux_info;
 794 #endif
 795 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 796         if (model == SH_PFC_R8A7795)
 797                 priv->pfc.info = &r8a7795_pinmux_info;
 798 #endif
 799 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 800         if (model == SH_PFC_R8A7796)
 801                 priv->pfc.info = &r8a7796_pinmux_info;
 802 #endif
 803 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 804         if (model == SH_PFC_R8A77970)
 805                 priv->pfc.info = &r8a77970_pinmux_info;
 806 #endif
 807 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 808         if (model == SH_PFC_R8A77995)
 809                 priv->pfc.info = &r8a77995_pinmux_info;
 810 #endif
 811
 812         priv->pmx.pfc = &priv->pfc;
 813         sh_pfc_init_ranges(&priv->pfc);
 814         sh_pfc_map_pins(&priv->pfc, &priv->pmx);
 815
 816         return 0;
 817 }
 818
 819 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
 820 #ifdef CONFIG_PINCTRL_PFC_R8A7790
 821         {
 822                 .compatible = "renesas,pfc-r8a7790",
 823                 .data = SH_PFC_R8A7790,
 824         },
 825 #endif
 826 #ifdef CONFIG_PINCTRL_PFC_R8A7791
 827         {
 828                 .compatible = "renesas,pfc-r8a7791",
 829                 .data = SH_PFC_R8A7791,
 830         },
 831 #endif
 832 #ifdef CONFIG_PINCTRL_PFC_R8A7792
 833         {
 834                 .compatible = "renesas,pfc-r8a7792",
 835                 .data = SH_PFC_R8A7792,
 836         },
 837 #endif
 838 #ifdef CONFIG_PINCTRL_PFC_R8A7793
 839         {
 840                 .compatible = "renesas,pfc-r8a7793",
 841                 .data = SH_PFC_R8A7793,
 842         },
 843 #endif
 844 #ifdef CONFIG_PINCTRL_PFC_R8A7795
 845         {
 846                 .compatible = "renesas,pfc-r8a7795",
 847                 .data = SH_PFC_R8A7795,
 848         },
 849 #endif
 850 #ifdef CONFIG_PINCTRL_PFC_R8A7796
 851         {
 852                 .compatible = "renesas,pfc-r8a7796",
 853                 .data = SH_PFC_R8A7796,
 854         },
 855 #endif
 856 #ifdef CONFIG_PINCTRL_PFC_R8A77970
 857         {
 858                 .compatible = "renesas,pfc-r8a77970",
 859                 .data = SH_PFC_R8A77970,
 860         },
 861 #endif
 862 #ifdef CONFIG_PINCTRL_PFC_R8A77995
 863         {
 864                 .compatible = "renesas,pfc-r8a77995",
 865                 .data = SH_PFC_R8A77995,
 866         },
 867 #endif
 868         { },
 869 };
 870
 871 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
 872         .name           = "sh_pfc_pinctrl",
 873         .id             = UCLASS_PINCTRL,
 874         .of_match       = sh_pfc_pinctrl_ids,
 875         .priv_auto_alloc_size = sizeof(struct sh_pfc_pinctrl_priv),
 876         .ops            = &sh_pfc_pinctrl_ops,
 877         .probe          = sh_pfc_pinctrl_probe,
 878 };