git.sur5r.net Git - u-boot/blob - drivers/pinctrl/rockchip/pinctrl_rk3188.c

   1 /*
   2  * Pinctrl driver for Rockchip RK3188 SoCs
   3  * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <syscon.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/grf_rk3188.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/periph.h>
  17 #include <asm/arch/pmu_rk3188.h>
  18 #include <dm/pinctrl.h>
  19 #include <dm/root.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 struct rk3188_pinctrl_priv {
  24         struct rk3188_grf *grf;
  25         struct rk3188_pmu *pmu;
  26         int num_banks;
  27 };
  28
  29 /**
  30  * Encode variants of iomux registers into a type variable
  31  */
  32 #define IOMUX_GPIO_ONLY         BIT(0)
  33
  34 /**
  35  * @type: iomux variant using IOMUX_* constants
  36  * @offset: if initialized to -1 it will be autocalculated, by specifying
  37  *          an initial offset value the relevant source offset can be reset
  38  *          to a new value for autocalculating the following iomux registers.
  39  */
  40 struct rockchip_iomux {
  41         u8 type;
  42         s16 offset;
  43 };
  44
  45 /**
  46  * @reg: register offset of the gpio bank
  47  * @nr_pins: number of pins in this bank
  48  * @bank_num: number of the bank, to account for holes
  49  * @name: name of the bank
  50  * @iomux: array describing the 4 iomux sources of the bank
  51  */
  52 struct rockchip_pin_bank {
  53         u16 reg;
  54         u8 nr_pins;
  55         u8 bank_num;
  56         char *name;
  57         struct rockchip_iomux iomux[4];
  58 };
  59
  60 #define PIN_BANK(id, pins, label)                       \
  61         {                                               \
  62                 .bank_num       = id,                   \
  63                 .nr_pins        = pins,                 \
  64                 .name           = label,                \
  65                 .iomux          = {                     \
  66                         { .offset = -1 },               \
  67                         { .offset = -1 },               \
  68                         { .offset = -1 },               \
  69                         { .offset = -1 },               \
  70                 },                                      \
  71         }
  72
  73 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
  74         {                                                               \
  75                 .bank_num       = id,                                   \
  76                 .nr_pins        = pins,                                 \
  77                 .name           = label,                                \
  78                 .iomux          = {                                     \
  79                         { .type = iom0, .offset = -1 },                 \
  80                         { .type = iom1, .offset = -1 },                 \
  81                         { .type = iom2, .offset = -1 },                 \
  82                         { .type = iom3, .offset = -1 },                 \
  83                 },                                                      \
  84         }
  85
  86 #ifndef CONFIG_SPL_BUILD
  87 static struct rockchip_pin_bank rk3188_pin_banks[] = {
  88         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
  89         PIN_BANK(1, 32, "gpio1"),
  90         PIN_BANK(2, 32, "gpio2"),
  91         PIN_BANK(3, 32, "gpio3"),
  92 };
  93 #endif
  94
  95 static void pinctrl_rk3188_pwm_config(struct rk3188_grf *grf, int pwm_id)
  96 {
  97         switch (pwm_id) {
  98         case PERIPH_ID_PWM0:
  99                 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D3_MASK << GPIO3D3_SHIFT,
 100                              GPIO3D3_PWM_0 << GPIO3D3_SHIFT);
 101                 break;
 102         case PERIPH_ID_PWM1:
 103                 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D4_MASK << GPIO3D4_SHIFT,
 104                              GPIO3D4_PWM_1 << GPIO3D4_SHIFT);
 105                 break;
 106         case PERIPH_ID_PWM2:
 107                 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D5_MASK << GPIO3D5_SHIFT,
 108                              GPIO3D5_PWM_2 << GPIO3D5_SHIFT);
 109                 break;
 110         case PERIPH_ID_PWM3:
 111                 rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D6_MASK << GPIO3D6_SHIFT,
 112                              GPIO3D6_PWM_3 << GPIO3D6_SHIFT);
 113                 break;
 114         default:
 115                 debug("pwm id = %d iomux error!\n", pwm_id);
 116                 break;
 117         }
 118 }
 119
 120 static void pinctrl_rk3188_i2c_config(struct rk3188_grf *grf,
 121                                       struct rk3188_pmu *pmu, int i2c_id)
 122 {
 123         switch (i2c_id) {
 124         case PERIPH_ID_I2C0:
 125                 rk_clrsetreg(&grf->gpio1d_iomux,
 126                                 GPIO1D1_MASK << GPIO1D1_SHIFT |
 127                                 GPIO1D0_MASK << GPIO1D0_SHIFT,
 128                                 GPIO1D1_I2C0_SCL << GPIO1D1_SHIFT |
 129                                 GPIO1D0_I2C0_SDA << GPIO1D0_SHIFT);
 130                 /* enable new i2c controller */
 131                 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C0_SEL_SHIFT,
 132                                              1 << RKI2C0_SEL_SHIFT);
 133                 break;
 134         case PERIPH_ID_I2C1:
 135                 rk_clrsetreg(&grf->gpio1d_iomux,
 136                                 GPIO1D3_MASK << GPIO1D3_SHIFT |
 137                                 GPIO1D2_MASK << GPIO1D2_SHIFT,
 138                                 GPIO1D3_I2C1_SCL << GPIO1D2_SHIFT |
 139                                 GPIO1D2_I2C1_SDA << GPIO1D2_SHIFT);
 140                 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C1_SEL_SHIFT,
 141                                              1 << RKI2C1_SEL_SHIFT);
 142                 break;
 143         case PERIPH_ID_I2C2:
 144                 rk_clrsetreg(&grf->gpio1d_iomux,
 145                                 GPIO1D5_MASK << GPIO1D5_SHIFT |
 146                                 GPIO1D4_MASK << GPIO1D4_SHIFT,
 147                                 GPIO1D5_I2C2_SCL << GPIO1D5_SHIFT |
 148                                 GPIO1D4_I2C2_SDA << GPIO1D4_SHIFT);
 149                 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C2_SEL_SHIFT,
 150                                              1 << RKI2C2_SEL_SHIFT);
 151                 break;
 152         case PERIPH_ID_I2C3:
 153                 rk_clrsetreg(&grf->gpio3b_iomux,
 154                                 GPIO3B7_MASK << GPIO3B7_SHIFT |
 155                                 GPIO3B6_MASK << GPIO3B6_SHIFT,
 156                                 GPIO3B7_I2C3_SCL << GPIO3B7_SHIFT |
 157                                 GPIO3B6_I2C3_SDA << GPIO3B6_SHIFT);
 158                 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C3_SEL_SHIFT,
 159                                              1 << RKI2C3_SEL_SHIFT);
 160                 break;
 161         case PERIPH_ID_I2C4:
 162                 rk_clrsetreg(&grf->gpio1d_iomux,
 163                                 GPIO1D7_MASK << GPIO1D7_SHIFT |
 164                                 GPIO1D6_MASK << GPIO1D6_SHIFT,
 165                                 GPIO1D7_I2C4_SCL << GPIO1D7_SHIFT |
 166                                 GPIO1D6_I2C4_SDA << GPIO1D6_SHIFT);
 167                 rk_clrsetreg(&grf->soc_con1, 1 << RKI2C4_SEL_SHIFT,
 168                                              1 << RKI2C4_SEL_SHIFT);
 169                 break;
 170         default:
 171                 debug("i2c id = %d iomux error!\n", i2c_id);
 172                 break;
 173         }
 174 }
 175
 176 static int pinctrl_rk3188_spi_config(struct rk3188_grf *grf,
 177                                      enum periph_id spi_id, int cs)
 178 {
 179         switch (spi_id) {
 180         case PERIPH_ID_SPI0:
 181                 switch (cs) {
 182                 case 0:
 183                         rk_clrsetreg(&grf->gpio1a_iomux,
 184                                      GPIO1A7_MASK << GPIO1A7_SHIFT,
 185                                      GPIO1A7_SPI0_CSN0 << GPIO1A7_SHIFT);
 186                         break;
 187                 case 1:
 188                         rk_clrsetreg(&grf->gpio1b_iomux,
 189                                      GPIO1B7_MASK << GPIO1B7_SHIFT,
 190                                      GPIO1B7_SPI0_CSN1 << GPIO1B7_SHIFT);
 191                         break;
 192                 default:
 193                         goto err;
 194                 }
 195                 rk_clrsetreg(&grf->gpio1a_iomux,
 196                              GPIO1A4_MASK << GPIO1A4_SHIFT |
 197                              GPIO1A5_MASK << GPIO1A5_SHIFT |
 198                              GPIO1A6_MASK << GPIO1A6_SHIFT,
 199                              GPIO1A4_SPI0_RXD << GPIO1A4_SHIFT |
 200                              GPIO1A5_SPI0_TXD << GPIO1A5_SHIFT |
 201                              GPIO1A6_SPI0_CLK << GPIO1A6_SHIFT);
 202                 break;
 203         case PERIPH_ID_SPI1:
 204                 switch (cs) {
 205                 case 0:
 206                         rk_clrsetreg(&grf->gpio0d_iomux,
 207                                      GPIO0D7_MASK << GPIO0D7_SHIFT,
 208                                      GPIO0D7_SPI1_CSN0 << GPIO0D7_SHIFT);
 209                         break;
 210                 case 1:
 211                         rk_clrsetreg(&grf->gpio1b_iomux,
 212                                      GPIO1B6_MASK << GPIO1B6_SHIFT,
 213                                      GPIO1B6_SPI1_CSN1 << GPIO1B6_SHIFT);
 214                         break;
 215                 default:
 216                         goto err;
 217                 }
 218                 rk_clrsetreg(&grf->gpio0d_iomux,
 219                              GPIO0D4_MASK << GPIO0D4_SHIFT |
 220                              GPIO0D5_MASK << GPIO0D5_SHIFT |
 221                              GPIO0D6_MASK << GPIO0D6_SHIFT,
 222                              GPIO0D4_SPI0_RXD << GPIO0D4_SHIFT |
 223                              GPIO0D5_SPI1_TXD << GPIO0D5_SHIFT |
 224                              GPIO0D6_SPI1_CLK << GPIO0D6_SHIFT);
 225                 break;
 226         default:
 227                 goto err;
 228         }
 229
 230         return 0;
 231 err:
 232         debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
 233         return -ENOENT;
 234 }
 235
 236 static void pinctrl_rk3188_uart_config(struct rk3188_grf *grf, int uart_id)
 237 {
 238         switch (uart_id) {
 239         case PERIPH_ID_UART0:
 240                 rk_clrsetreg(&grf->gpio1a_iomux,
 241                              GPIO1A3_MASK << GPIO1A3_SHIFT |
 242                              GPIO1A2_MASK << GPIO1A2_SHIFT |
 243                              GPIO1A1_MASK << GPIO1A1_SHIFT |
 244                              GPIO1A0_MASK << GPIO1A0_SHIFT,
 245                              GPIO1A3_UART0_RTS_N << GPIO1A3_SHIFT |
 246                              GPIO1A2_UART0_CTS_N << GPIO1A2_SHIFT |
 247                              GPIO1A1_UART0_SOUT << GPIO1A1_SHIFT |
 248                              GPIO1A0_UART0_SIN << GPIO1A0_SHIFT);
 249                 break;
 250         case PERIPH_ID_UART1:
 251                 rk_clrsetreg(&grf->gpio1a_iomux,
 252                              GPIO1A7_MASK << GPIO1A7_SHIFT |
 253                              GPIO1A6_MASK << GPIO1A6_SHIFT |
 254                              GPIO1A5_MASK << GPIO1A5_SHIFT |
 255                              GPIO1A4_MASK << GPIO1A4_SHIFT,
 256                              GPIO1A7_UART1_RTS_N << GPIO1A7_SHIFT |
 257                              GPIO1A6_UART1_CTS_N << GPIO1A6_SHIFT |
 258                              GPIO1A5_UART1_SOUT << GPIO1A5_SHIFT |
 259                              GPIO1A4_UART1_SIN << GPIO1A4_SHIFT);
 260                 break;
 261         case PERIPH_ID_UART2:
 262                 rk_clrsetreg(&grf->gpio1b_iomux,
 263                              GPIO1B1_MASK << GPIO1B1_SHIFT |
 264                              GPIO1B0_MASK << GPIO1B0_SHIFT,
 265                              GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
 266                              GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
 267                 break;
 268         case PERIPH_ID_UART3:
 269                 rk_clrsetreg(&grf->gpio1b_iomux,
 270                              GPIO1B5_MASK << GPIO1B5_SHIFT |
 271                              GPIO1B4_MASK << GPIO1B4_SHIFT |
 272                              GPIO1B3_MASK << GPIO1B3_SHIFT |
 273                              GPIO1B2_MASK << GPIO1B2_SHIFT,
 274                              GPIO1B5_UART3_RTS_N << GPIO1B5_SHIFT |
 275                              GPIO1B4_UART3_CTS_N << GPIO1B4_SHIFT |
 276                              GPIO1B3_UART3_SOUT << GPIO1B3_SHIFT |
 277                              GPIO1B2_UART3_SIN << GPIO1B2_SHIFT);
 278                 break;
 279         default:
 280                 debug("uart id = %d iomux error!\n", uart_id);
 281                 break;
 282         }
 283 }
 284
 285 static void pinctrl_rk3188_sdmmc_config(struct rk3188_grf *grf, int mmc_id)
 286 {
 287         switch (mmc_id) {
 288         case PERIPH_ID_EMMC:
 289                 rk_clrsetreg(&grf->soc_con0, 1 << EMMC_FLASH_SEL_SHIFT,
 290                                              1 << EMMC_FLASH_SEL_SHIFT);
 291                 rk_clrsetreg(&grf->gpio0d_iomux,
 292                              GPIO0D2_MASK << GPIO0D2_SHIFT |
 293                              GPIO0D0_MASK << GPIO0D0_SHIFT,
 294                              GPIO0D2_EMMC_CMD << GPIO0D2_SHIFT |
 295                              GPIO0D0_EMMC_CLKOUT << GPIO0D0_SHIFT);
 296                 break;
 297         case PERIPH_ID_SDCARD:
 298                 rk_clrsetreg(&grf->gpio3b_iomux,
 299                              GPIO3B0_MASK << GPIO3B0_SHIFT,
 300                              GPIO3B0_SDMMC_DETECT_N << GPIO3B0_SHIFT);
 301                 rk_clrsetreg(&grf->gpio3a_iomux,
 302                              GPIO3A7_MASK << GPIO3A7_SHIFT |
 303                              GPIO3A6_MASK << GPIO3A6_SHIFT |
 304                              GPIO3A5_MASK << GPIO3A5_SHIFT |
 305                              GPIO3A4_MASK << GPIO3A4_SHIFT |
 306                              GPIO3A3_MASK << GPIO3A3_SHIFT |
 307                              GPIO3A3_MASK << GPIO3A2_SHIFT,
 308                              GPIO3A7_SDMMC0_DATA3 << GPIO3A7_SHIFT |
 309                              GPIO3A6_SDMMC0_DATA2 << GPIO3A6_SHIFT |
 310                              GPIO3A5_SDMMC0_DATA1 << GPIO3A5_SHIFT |
 311                              GPIO3A4_SDMMC0_DATA0 << GPIO3A4_SHIFT |
 312                              GPIO3A3_SDMMC0_CMD << GPIO3A3_SHIFT |
 313                              GPIO3A2_SDMMC0_CLKOUT << GPIO3A2_SHIFT);
 314                 break;
 315         default:
 316                 debug("mmc id = %d iomux error!\n", mmc_id);
 317                 break;
 318         }
 319 }
 320
 321 static int rk3188_pinctrl_request(struct udevice *dev, int func, int flags)
 322 {
 323         struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
 324
 325         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 326         switch (func) {
 327         case PERIPH_ID_PWM0:
 328         case PERIPH_ID_PWM1:
 329         case PERIPH_ID_PWM2:
 330         case PERIPH_ID_PWM3:
 331         case PERIPH_ID_PWM4:
 332                 pinctrl_rk3188_pwm_config(priv->grf, func);
 333                 break;
 334         case PERIPH_ID_I2C0:
 335         case PERIPH_ID_I2C1:
 336         case PERIPH_ID_I2C2:
 337         case PERIPH_ID_I2C3:
 338         case PERIPH_ID_I2C4:
 339         case PERIPH_ID_I2C5:
 340                 pinctrl_rk3188_i2c_config(priv->grf, priv->pmu, func);
 341                 break;
 342         case PERIPH_ID_SPI0:
 343         case PERIPH_ID_SPI1:
 344         case PERIPH_ID_SPI2:
 345                 pinctrl_rk3188_spi_config(priv->grf, func, flags);
 346                 break;
 347         case PERIPH_ID_UART0:
 348         case PERIPH_ID_UART1:
 349         case PERIPH_ID_UART2:
 350         case PERIPH_ID_UART3:
 351         case PERIPH_ID_UART4:
 352                 pinctrl_rk3188_uart_config(priv->grf, func);
 353                 break;
 354                 break;
 355         case PERIPH_ID_SDMMC0:
 356         case PERIPH_ID_SDMMC1:
 357                 pinctrl_rk3188_sdmmc_config(priv->grf, func);
 358                 break;
 359         default:
 360                 return -EINVAL;
 361         }
 362
 363         return 0;
 364 }
 365
 366 static int rk3188_pinctrl_get_periph_id(struct udevice *dev,
 367                                         struct udevice *periph)
 368 {
 369 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 370         u32 cell[3];
 371         int ret;
 372
 373         ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
 374         if (ret < 0)
 375                 return -EINVAL;
 376
 377         switch (cell[1]) {
 378         case 44:
 379                 return PERIPH_ID_SPI0;
 380         case 45:
 381                 return PERIPH_ID_SPI1;
 382         case 46:
 383                 return PERIPH_ID_SPI2;
 384         case 60:
 385                 return PERIPH_ID_I2C0;
 386         case 62: /* Note strange order */
 387                 return PERIPH_ID_I2C1;
 388         case 61:
 389                 return PERIPH_ID_I2C2;
 390         case 63:
 391                 return PERIPH_ID_I2C3;
 392         case 64:
 393                 return PERIPH_ID_I2C4;
 394         case 65:
 395                 return PERIPH_ID_I2C5;
 396         }
 397 #endif
 398
 399         return -ENOENT;
 400 }
 401
 402 static int rk3188_pinctrl_set_state_simple(struct udevice *dev,
 403                                            struct udevice *periph)
 404 {
 405         int func;
 406
 407         func = rk3188_pinctrl_get_periph_id(dev, periph);
 408         if (func < 0)
 409                 return func;
 410         return rk3188_pinctrl_request(dev, func, 0);
 411 }
 412
 413 #ifndef CONFIG_SPL_BUILD
 414 int rk3188_pinctrl_get_pin_info(struct rk3188_pinctrl_priv *priv,
 415                                 int banknum, int ind, u32 **addrp, uint *shiftp,
 416                                 uint *maskp)
 417 {
 418         struct rockchip_pin_bank *bank = &rk3188_pin_banks[banknum];
 419         uint muxnum;
 420         u32 *addr;
 421
 422         for (muxnum = 0; muxnum < 4; muxnum++) {
 423                 struct rockchip_iomux *mux = &bank->iomux[muxnum];
 424
 425                 if (ind >= 8) {
 426                         ind -= 8;
 427                         continue;
 428                 }
 429
 430                 addr = &priv->grf->gpio0c_iomux - 2;
 431                 addr += mux->offset;
 432                 *shiftp = ind & 7;
 433                 *maskp = 3;
 434                 *shiftp *= 2;
 435
 436                 debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
 437                       *maskp, *shiftp);
 438                 *addrp = addr;
 439                 return 0;
 440         }
 441
 442         return -EINVAL;
 443 }
 444
 445 static int rk3188_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
 446                                        int index)
 447 {
 448         struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
 449         uint shift;
 450         uint mask;
 451         u32 *addr;
 452         int ret;
 453
 454         ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
 455                                           &mask);
 456         if (ret)
 457                 return ret;
 458         return (readl(addr) & mask) >> shift;
 459 }
 460
 461 static int rk3188_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
 462                                    int muxval, int flags)
 463 {
 464         struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
 465         uint shift, ind = index;
 466         uint mask;
 467         u32 *addr;
 468         int ret;
 469
 470         debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
 471         ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
 472                                           &mask);
 473         if (ret)
 474                 return ret;
 475         rk_clrsetreg(addr, mask << shift, muxval << shift);
 476
 477         /* Handle pullup/pulldown */
 478         if (flags) {
 479                 uint val = 0;
 480
 481                 if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP))
 482                         val = 1;
 483                 else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
 484                         val = 2;
 485
 486                 ind = index >> 3;
 487
 488                 if (banknum == 0 && index < 12) {
 489                         addr = &priv->pmu->gpio0_p[ind];
 490                         shift = (index & 7) * 2;
 491                 } else if (banknum == 0 && index >= 12) {
 492                         addr = &priv->grf->gpio0_p[ind - 1];
 493                         /*
 494                          * The bits in the grf-registers have an inverse
 495                          * ordering with the lowest pin being in bits 15:14
 496                          * and the highest pin in bits 1:0 .
 497                          */
 498                         shift = (7 - (index & 7)) * 2;
 499                 } else {
 500                         addr = &priv->grf->gpio1_p[banknum - 1][ind];
 501                         shift = (7 - (index & 7)) * 2;
 502                 }
 503                 debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
 504                       shift);
 505                 rk_clrsetreg(addr, 3 << shift, val << shift);
 506         }
 507
 508         return 0;
 509 }
 510
 511 static int rk3188_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 512 {
 513         const void *blob = gd->fdt_blob;
 514         int pcfg_node, ret, flags, count, i;
 515         u32 cell[60], *ptr;
 516
 517         debug("%s: %s %s\n", __func__, dev->name, config->name);
 518         ret = fdtdec_get_int_array_count(blob, dev_of_offset(config),
 519                                          "rockchip,pins", cell,
 520                                          ARRAY_SIZE(cell));
 521         if (ret < 0) {
 522                 debug("%s: bad array %d\n", __func__, ret);
 523                 return -EINVAL;
 524         }
 525         count = ret;
 526         for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) {
 527                 pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]);
 528                 if (pcfg_node < 0)
 529                         return -EINVAL;
 530                 flags = pinctrl_decode_pin_config(blob, pcfg_node);
 531                 if (flags < 0)
 532                         return flags;
 533
 534                 ret = rk3188_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
 535                                               flags);
 536                 if (ret)
 537                         return ret;
 538         }
 539
 540         return 0;
 541 }
 542 #endif
 543
 544 static struct pinctrl_ops rk3188_pinctrl_ops = {
 545 #ifndef CONFIG_SPL_BUILD
 546         .set_state      = rk3188_pinctrl_set_state,
 547         .get_gpio_mux   = rk3188_pinctrl_get_gpio_mux,
 548 #endif
 549         .set_state_simple       = rk3188_pinctrl_set_state_simple,
 550         .request        = rk3188_pinctrl_request,
 551         .get_periph_id  = rk3188_pinctrl_get_periph_id,
 552 };
 553
 554 #ifndef CONFIG_SPL_BUILD
 555 static int rk3188_pinctrl_parse_tables(struct rk3188_pinctrl_priv *priv,
 556                                        struct rockchip_pin_bank *banks,
 557                                        int count)
 558 {
 559         struct rockchip_pin_bank *bank;
 560         uint reg, muxnum, banknum;
 561
 562         reg = 0;
 563         for (banknum = 0; banknum < count; banknum++) {
 564                 bank = &banks[banknum];
 565                 bank->reg = reg;
 566                 debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4);
 567                 for (muxnum = 0; muxnum < 4; muxnum++) {
 568                         struct rockchip_iomux *mux = &bank->iomux[muxnum];
 569
 570                         mux->offset = reg;
 571                         reg += 1;
 572                 }
 573         }
 574
 575         return 0;
 576 }
 577 #endif
 578
 579 static int rk3188_pinctrl_probe(struct udevice *dev)
 580 {
 581         struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
 582         int ret = 0;
 583
 584         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 585         priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 586         debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
 587 #ifndef CONFIG_SPL_BUILD
 588         ret = rk3188_pinctrl_parse_tables(priv, rk3188_pin_banks,
 589                                           ARRAY_SIZE(rk3188_pin_banks));
 590 #endif
 591
 592         return ret;
 593 }
 594
 595 static const struct udevice_id rk3188_pinctrl_ids[] = {
 596         { .compatible = "rockchip,rk3188-pinctrl" },
 597         { }
 598 };
 599
 600 U_BOOT_DRIVER(pinctrl_rk3188) = {
 601         .name           = "rockchip_rk3188_pinctrl",
 602         .id             = UCLASS_PINCTRL,
 603         .of_match       = rk3188_pinctrl_ids,
 604         .priv_auto_alloc_size = sizeof(struct rk3188_pinctrl_priv),
 605         .ops            = &rk3188_pinctrl_ops,
 606 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 607         .bind           = dm_scan_fdt_dev,
 608 #endif
 609         .probe          = rk3188_pinctrl_probe,
 610 };