git.sur5r.net Git - u-boot/blob - drivers/pinctrl/rockchip/pinctrl_rk3288.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Pinctrl driver for Rockchip SoCs
   4  * Copyright (c) 2015 Google, Inc
   5  * Written by Simon Glass <sjg@chromium.org>
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <syscon.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/grf_rk3288.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/periph.h>
  17 #include <asm/arch/pmu_rk3288.h>
  18 #include <dm/pinctrl.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 struct rk3288_pinctrl_priv {
  23         struct rk3288_grf *grf;
  24         struct rk3288_pmu *pmu;
  25         int num_banks;
  26 };
  27
  28 /**
  29  * Encode variants of iomux registers into a type variable
  30  */
  31 #define IOMUX_GPIO_ONLY         BIT(0)
  32 #define IOMUX_WIDTH_4BIT        BIT(1)
  33 #define IOMUX_SOURCE_PMU        BIT(2)
  34 #define IOMUX_UNROUTED          BIT(3)
  35
  36 /**
  37  * @type: iomux variant using IOMUX_* constants
  38  * @offset: if initialized to -1 it will be autocalculated, by specifying
  39  *          an initial offset value the relevant source offset can be reset
  40  *          to a new value for autocalculating the following iomux registers.
  41  */
  42 struct rockchip_iomux {
  43         u8 type;
  44         s16 offset;
  45 };
  46
  47 /**
  48  * @reg: register offset of the gpio bank
  49  * @nr_pins: number of pins in this bank
  50  * @bank_num: number of the bank, to account for holes
  51  * @name: name of the bank
  52  * @iomux: array describing the 4 iomux sources of the bank
  53  */
  54 struct rockchip_pin_bank {
  55         u16 reg;
  56         u8 nr_pins;
  57         u8 bank_num;
  58         char *name;
  59         struct rockchip_iomux iomux[4];
  60 };
  61
  62 #define PIN_BANK(id, pins, label)                       \
  63         {                                               \
  64                 .bank_num       = id,                   \
  65                 .nr_pins        = pins,                 \
  66                 .name           = label,                \
  67                 .iomux          = {                     \
  68                         { .offset = -1 },               \
  69                         { .offset = -1 },               \
  70                         { .offset = -1 },               \
  71                         { .offset = -1 },               \
  72                 },                                      \
  73         }
  74
  75 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
  76         {                                                               \
  77                 .bank_num       = id,                                   \
  78                 .nr_pins        = pins,                                 \
  79                 .name           = label,                                \
  80                 .iomux          = {                                     \
  81                         { .type = iom0, .offset = -1 },                 \
  82                         { .type = iom1, .offset = -1 },                 \
  83                         { .type = iom2, .offset = -1 },                 \
  84                         { .type = iom3, .offset = -1 },                 \
  85                 },                                                      \
  86         }
  87
  88 #ifndef CONFIG_SPL_BUILD
  89 static struct rockchip_pin_bank rk3288_pin_banks[] = {
  90         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
  91                                              IOMUX_SOURCE_PMU,
  92                                              IOMUX_SOURCE_PMU,
  93                                              IOMUX_UNROUTED
  94                             ),
  95         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
  96                                              IOMUX_UNROUTED,
  97                                              IOMUX_UNROUTED,
  98                                              0
  99                             ),
 100         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
 101         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
 102         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
 103                                              IOMUX_WIDTH_4BIT,
 104                                              0,
 105                                              0
 106                             ),
 107         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
 108                                              0,
 109                                              0,
 110                                              IOMUX_UNROUTED
 111                             ),
 112         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
 113         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
 114                                              0,
 115                                              IOMUX_WIDTH_4BIT,
 116                                              IOMUX_UNROUTED
 117                             ),
 118         PIN_BANK(8, 16, "gpio8"),
 119 };
 120 #endif
 121
 122 static void pinctrl_rk3288_pwm_config(struct rk3288_grf *grf, int pwm_id)
 123 {
 124         switch (pwm_id) {
 125         case PERIPH_ID_PWM0:
 126                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A0_MASK << GPIO7A0_SHIFT,
 127                              GPIO7A0_PWM_0 << GPIO7A0_SHIFT);
 128                 break;
 129         case PERIPH_ID_PWM1:
 130                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A1_MASK << GPIO7A1_SHIFT,
 131                              GPIO7A1_PWM_1 << GPIO7A1_SHIFT);
 132                 break;
 133         case PERIPH_ID_PWM2:
 134                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C6_MASK << GPIO7C6_SHIFT,
 135                              GPIO7C6_PWM_2 << GPIO7C6_SHIFT);
 136                 break;
 137         case PERIPH_ID_PWM3:
 138                 rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C7_MASK << GPIO7C6_SHIFT,
 139                              GPIO7C7_PWM_3 << GPIO7C7_SHIFT);
 140                 break;
 141         default:
 142                 debug("pwm id = %d iomux error!\n", pwm_id);
 143                 break;
 144         }
 145 }
 146
 147 static void pinctrl_rk3288_i2c_config(struct rk3288_grf *grf,
 148                                       struct rk3288_pmu *pmu, int i2c_id)
 149 {
 150         switch (i2c_id) {
 151         case PERIPH_ID_I2C0:
 152                 clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_B],
 153                                 GPIO0_B7_MASK << GPIO0_B7_SHIFT,
 154                                 GPIO0_B7_I2C0PMU_SDA << GPIO0_B7_SHIFT);
 155                 clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_C],
 156                                 GPIO0_C0_MASK << GPIO0_C0_SHIFT,
 157                                 GPIO0_C0_I2C0PMU_SCL << GPIO0_C0_SHIFT);
 158                 break;
 159 #ifndef CONFIG_SPL_BUILD
 160         case PERIPH_ID_I2C1:
 161                 rk_clrsetreg(&grf->gpio8a_iomux,
 162                              GPIO8A4_MASK << GPIO8A4_SHIFT |
 163                              GPIO8A5_MASK << GPIO8A5_SHIFT,
 164                              GPIO8A4_I2C2SENSOR_SDA << GPIO8A4_SHIFT |
 165                              GPIO8A5_I2C2SENSOR_SCL << GPIO8A5_SHIFT);
 166                 break;
 167         case PERIPH_ID_I2C2:
 168                 rk_clrsetreg(&grf->gpio6b_iomux,
 169                              GPIO6B1_MASK << GPIO6B1_SHIFT |
 170                              GPIO6B2_MASK << GPIO6B2_SHIFT,
 171                              GPIO6B1_I2C1AUDIO_SDA << GPIO6B1_SHIFT |
 172                              GPIO6B2_I2C1AUDIO_SCL << GPIO6B2_SHIFT);
 173                 break;
 174         case PERIPH_ID_I2C3:
 175                 rk_clrsetreg(&grf->gpio2c_iomux,
 176                              GPIO2C1_MASK << GPIO2C1_SHIFT |
 177                              GPIO2C0_MASK << GPIO2C0_SHIFT,
 178                              GPIO2C1_I2C3CAM_SDA << GPIO2C1_SHIFT |
 179                              GPIO2C0_I2C3CAM_SCL << GPIO2C0_SHIFT);
 180                 break;
 181         case PERIPH_ID_I2C4:
 182                 rk_clrsetreg(&grf->gpio7cl_iomux,
 183                              GPIO7C1_MASK << GPIO7C1_SHIFT |
 184                              GPIO7C2_MASK << GPIO7C2_SHIFT,
 185                              GPIO7C1_I2C4TP_SDA << GPIO7C1_SHIFT |
 186                              GPIO7C2_I2C4TP_SCL << GPIO7C2_SHIFT);
 187                 break;
 188         case PERIPH_ID_I2C5:
 189                 rk_clrsetreg(&grf->gpio7cl_iomux,
 190                              GPIO7C3_MASK << GPIO7C3_SHIFT,
 191                              GPIO7C3_I2C5HDMI_SDA << GPIO7C3_SHIFT);
 192                 rk_clrsetreg(&grf->gpio7ch_iomux,
 193                              GPIO7C4_MASK << GPIO7C4_SHIFT,
 194                              GPIO7C4_I2C5HDMI_SCL << GPIO7C4_SHIFT);
 195                 break;
 196 #endif
 197         default:
 198                 debug("i2c id = %d iomux error!\n", i2c_id);
 199                 break;
 200         }
 201 }
 202
 203 #ifndef CONFIG_SPL_BUILD
 204 static void pinctrl_rk3288_lcdc_config(struct rk3288_grf *grf, int lcd_id)
 205 {
 206         switch (lcd_id) {
 207         case PERIPH_ID_LCDC0:
 208                 rk_clrsetreg(&grf->gpio1d_iomux,
 209                              GPIO1D3_MASK << GPIO1D0_SHIFT |
 210                              GPIO1D2_MASK << GPIO1D2_SHIFT |
 211                              GPIO1D1_MASK << GPIO1D1_SHIFT |
 212                              GPIO1D0_MASK << GPIO1D0_SHIFT,
 213                              GPIO1D3_LCDC0_DCLK << GPIO1D3_SHIFT |
 214                              GPIO1D2_LCDC0_DEN << GPIO1D2_SHIFT |
 215                              GPIO1D1_LCDC0_VSYNC << GPIO1D1_SHIFT |
 216                              GPIO1D0_LCDC0_HSYNC << GPIO1D0_SHIFT);
 217                 break;
 218         default:
 219                 debug("lcdc id = %d iomux error!\n", lcd_id);
 220                 break;
 221         }
 222 }
 223 #endif
 224
 225 static int pinctrl_rk3288_spi_config(struct rk3288_grf *grf,
 226                                      enum periph_id spi_id, int cs)
 227 {
 228         switch (spi_id) {
 229 #ifndef CONFIG_SPL_BUILD
 230         case PERIPH_ID_SPI0:
 231                 switch (cs) {
 232                 case 0:
 233                         rk_clrsetreg(&grf->gpio5b_iomux,
 234                                      GPIO5B5_MASK << GPIO5B5_SHIFT,
 235                                      GPIO5B5_SPI0_CSN0 << GPIO5B5_SHIFT);
 236                         break;
 237                 case 1:
 238                         rk_clrsetreg(&grf->gpio5c_iomux,
 239                                      GPIO5C0_MASK << GPIO5C0_SHIFT,
 240                                      GPIO5C0_SPI0_CSN1 << GPIO5C0_SHIFT);
 241                         break;
 242                 default:
 243                         goto err;
 244                 }
 245                 rk_clrsetreg(&grf->gpio5b_iomux,
 246                              GPIO5B7_MASK << GPIO5B7_SHIFT |
 247                              GPIO5B6_MASK << GPIO5B6_SHIFT |
 248                              GPIO5B4_MASK << GPIO5B4_SHIFT,
 249                              GPIO5B7_SPI0_RXD << GPIO5B7_SHIFT |
 250                              GPIO5B6_SPI0_TXD << GPIO5B6_SHIFT |
 251                              GPIO5B4_SPI0_CLK << GPIO5B4_SHIFT);
 252                 break;
 253         case PERIPH_ID_SPI1:
 254                 if (cs != 0)
 255                         goto err;
 256                 rk_clrsetreg(&grf->gpio7b_iomux,
 257                              GPIO7B6_MASK << GPIO7B6_SHIFT |
 258                              GPIO7B7_MASK << GPIO7B7_SHIFT |
 259                              GPIO7B5_MASK << GPIO7B5_SHIFT |
 260                              GPIO7B4_MASK << GPIO7B4_SHIFT,
 261                              GPIO7B6_SPI1_RXD << GPIO7B6_SHIFT |
 262                              GPIO7B7_SPI1_TXD << GPIO7B7_SHIFT |
 263                              GPIO7B5_SPI1_CSN0 << GPIO7B5_SHIFT |
 264                              GPIO7B4_SPI1_CLK << GPIO7B4_SHIFT);
 265                 break;
 266 #endif
 267         case PERIPH_ID_SPI2:
 268                 switch (cs) {
 269                 case 0:
 270                         rk_clrsetreg(&grf->gpio8a_iomux,
 271                                      GPIO8A7_MASK << GPIO8A7_SHIFT,
 272                                      GPIO8A7_SPI2_CSN0 << GPIO8A7_SHIFT);
 273                         break;
 274                 case 1:
 275                         rk_clrsetreg(&grf->gpio8a_iomux,
 276                                      GPIO8A3_MASK << GPIO8A3_SHIFT,
 277                                      GPIO8A3_SPI2_CSN1 << GPIO8A3_SHIFT);
 278                         break;
 279                 default:
 280                         goto err;
 281                 }
 282                 rk_clrsetreg(&grf->gpio8b_iomux,
 283                              GPIO8B1_MASK << GPIO8B1_SHIFT |
 284                              GPIO8B0_MASK << GPIO8B0_SHIFT,
 285                              GPIO8B1_SPI2_TXD << GPIO8B1_SHIFT |
 286                              GPIO8B0_SPI2_RXD << GPIO8B0_SHIFT);
 287                 rk_clrsetreg(&grf->gpio8a_iomux,
 288                              GPIO8A6_MASK << GPIO8A6_SHIFT,
 289                              GPIO8A6_SPI2_CLK << GPIO8A6_SHIFT);
 290                 break;
 291         default:
 292                 goto err;
 293         }
 294
 295         return 0;
 296 err:
 297         debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
 298         return -ENOENT;
 299 }
 300
 301 static void pinctrl_rk3288_uart_config(struct rk3288_grf *grf, int uart_id)
 302 {
 303         switch (uart_id) {
 304 #ifndef CONFIG_SPL_BUILD
 305         case PERIPH_ID_UART_BT:
 306                 rk_clrsetreg(&grf->gpio4c_iomux,
 307                              GPIO4C3_MASK << GPIO4C3_SHIFT |
 308                              GPIO4C2_MASK << GPIO4C2_SHIFT |
 309                              GPIO4C1_MASK << GPIO4C1_SHIFT |
 310                              GPIO4C0_MASK << GPIO4C0_SHIFT,
 311                              GPIO4C3_UART0BT_RTSN << GPIO4C3_SHIFT |
 312                              GPIO4C2_UART0BT_CTSN << GPIO4C2_SHIFT |
 313                              GPIO4C1_UART0BT_SOUT << GPIO4C1_SHIFT |
 314                              GPIO4C0_UART0BT_SIN << GPIO4C0_SHIFT);
 315                 break;
 316         case PERIPH_ID_UART_BB:
 317                 rk_clrsetreg(&grf->gpio5b_iomux,
 318                              GPIO5B3_MASK << GPIO5B3_SHIFT |
 319                              GPIO5B2_MASK << GPIO5B2_SHIFT |
 320                              GPIO5B1_MASK << GPIO5B1_SHIFT |
 321                              GPIO5B0_MASK << GPIO5B0_SHIFT,
 322                              GPIO5B3_UART1BB_RTSN << GPIO5B3_SHIFT |
 323                              GPIO5B2_UART1BB_CTSN << GPIO5B2_SHIFT |
 324                              GPIO5B1_UART1BB_SOUT << GPIO5B1_SHIFT |
 325                              GPIO5B0_UART1BB_SIN << GPIO5B0_SHIFT);
 326                 break;
 327 #endif
 328         case PERIPH_ID_UART_DBG:
 329                 rk_clrsetreg(&grf->gpio7ch_iomux,
 330                              GPIO7C7_MASK << GPIO7C7_SHIFT |
 331                              GPIO7C6_MASK << GPIO7C6_SHIFT,
 332                              GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
 333                              GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
 334                 break;
 335 #ifndef CONFIG_SPL_BUILD
 336         case PERIPH_ID_UART_GPS:
 337                 rk_clrsetreg(&grf->gpio7b_iomux,
 338                              GPIO7B2_MASK << GPIO7B2_SHIFT |
 339                              GPIO7B1_MASK << GPIO7B1_SHIFT |
 340                              GPIO7B0_MASK << GPIO7B0_SHIFT,
 341                              GPIO7B2_UART3GPS_RTSN << GPIO7B2_SHIFT |
 342                              GPIO7B1_UART3GPS_CTSN << GPIO7B1_SHIFT |
 343                              GPIO7B0_UART3GPS_SOUT << GPIO7B0_SHIFT);
 344                 rk_clrsetreg(&grf->gpio7a_iomux,
 345                              GPIO7A7_MASK << GPIO7A7_SHIFT,
 346                              GPIO7A7_UART3GPS_SIN << GPIO7A7_SHIFT);
 347                 break;
 348         case PERIPH_ID_UART_EXP:
 349                 rk_clrsetreg(&grf->gpio5b_iomux,
 350                              GPIO5B5_MASK << GPIO5B5_SHIFT |
 351                              GPIO5B4_MASK << GPIO5B4_SHIFT |
 352                              GPIO5B6_MASK << GPIO5B6_SHIFT |
 353                              GPIO5B7_MASK << GPIO5B7_SHIFT,
 354                              GPIO5B5_UART4EXP_RTSN << GPIO5B5_SHIFT |
 355                              GPIO5B4_UART4EXP_CTSN << GPIO5B4_SHIFT |
 356                              GPIO5B6_UART4EXP_SOUT << GPIO5B6_SHIFT |
 357                              GPIO5B7_UART4EXP_SIN << GPIO5B7_SHIFT);
 358                 break;
 359 #endif
 360         default:
 361                 debug("uart id = %d iomux error!\n", uart_id);
 362                 break;
 363         }
 364 }
 365
 366 static void pinctrl_rk3288_sdmmc_config(struct rk3288_grf *grf, int mmc_id)
 367 {
 368         switch (mmc_id) {
 369         case PERIPH_ID_EMMC:
 370                 rk_clrsetreg(&grf->gpio3a_iomux, 0xffff,
 371                              GPIO3A7_EMMC_DATA7 << GPIO3A7_SHIFT |
 372                              GPIO3A6_EMMC_DATA6 << GPIO3A6_SHIFT |
 373                              GPIO3A5_EMMC_DATA5 << GPIO3A5_SHIFT |
 374                              GPIO3A4_EMMC_DATA4 << GPIO3A4_SHIFT |
 375                              GPIO3A3_EMMC_DATA3 << GPIO3A3_SHIFT |
 376                              GPIO3A2_EMMC_DATA2 << GPIO3A2_SHIFT |
 377                              GPIO3A1_EMMC_DATA1 << GPIO3A1_SHIFT |
 378                              GPIO3A0_EMMC_DATA0 << GPIO3A0_SHIFT);
 379                 rk_clrsetreg(&grf->gpio3b_iomux, GPIO3B1_MASK << GPIO3B1_SHIFT,
 380                              GPIO3B1_EMMC_PWREN << GPIO3B1_SHIFT);
 381                 rk_clrsetreg(&grf->gpio3c_iomux,
 382                              GPIO3C0_MASK << GPIO3C0_SHIFT,
 383                              GPIO3C0_EMMC_CMD << GPIO3C0_SHIFT);
 384                 break;
 385         case PERIPH_ID_SDCARD:
 386                 rk_clrsetreg(&grf->gpio6c_iomux, 0xffff,
 387                              GPIO6C6_SDMMC0_DECTN << GPIO6C6_SHIFT |
 388                              GPIO6C5_SDMMC0_CMD << GPIO6C5_SHIFT |
 389                              GPIO6C4_SDMMC0_CLKOUT << GPIO6C4_SHIFT |
 390                              GPIO6C3_SDMMC0_DATA3 << GPIO6C3_SHIFT |
 391                              GPIO6C2_SDMMC0_DATA2 << GPIO6C2_SHIFT |
 392                              GPIO6C1_SDMMC0_DATA1 << GPIO6C1_SHIFT |
 393                              GPIO6C0_SDMMC0_DATA0 << GPIO6C0_SHIFT);
 394
 395                 /* use sdmmc0 io, disable JTAG function */
 396                 rk_clrsetreg(&grf->soc_con0, 1 << GRF_FORCE_JTAG_SHIFT, 0);
 397                 break;
 398         default:
 399                 debug("mmc id = %d iomux error!\n", mmc_id);
 400                 break;
 401         }
 402 }
 403
 404 static void pinctrl_rk3288_gmac_config(struct rk3288_grf *grf, int gmac_id)
 405 {
 406         switch (gmac_id) {
 407         case PERIPH_ID_GMAC:
 408                 rk_clrsetreg(&grf->gpio3dl_iomux,
 409                              GPIO3D3_MASK << GPIO3D3_SHIFT |
 410                              GPIO3D2_MASK << GPIO3D2_SHIFT |
 411                              GPIO3D2_MASK << GPIO3D1_SHIFT |
 412                              GPIO3D0_MASK << GPIO3D0_SHIFT,
 413                              GPIO3D3_MAC_RXD3 << GPIO3D3_SHIFT |
 414                              GPIO3D2_MAC_RXD2 << GPIO3D2_SHIFT |
 415                              GPIO3D1_MAC_TXD3 << GPIO3D1_SHIFT |
 416                              GPIO3D0_MAC_TXD2 << GPIO3D0_SHIFT);
 417
 418                 rk_clrsetreg(&grf->gpio3dh_iomux,
 419                              GPIO3D7_MASK << GPIO3D7_SHIFT |
 420                              GPIO3D6_MASK << GPIO3D6_SHIFT |
 421                              GPIO3D5_MASK << GPIO3D5_SHIFT |
 422                              GPIO3D4_MASK << GPIO3D4_SHIFT,
 423                              GPIO3D7_MAC_RXD1 << GPIO3D7_SHIFT |
 424                              GPIO3D6_MAC_RXD0 << GPIO3D6_SHIFT |
 425                              GPIO3D5_MAC_TXD1 << GPIO3D5_SHIFT |
 426                              GPIO3D4_MAC_TXD0 << GPIO3D4_SHIFT);
 427
 428                 /* switch the Tx pins to 12ma drive-strength */
 429                 rk_clrsetreg(&grf->gpio1_e[2][3],
 430                              GPIO_BIAS_MASK |
 431                              (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1)) |
 432                              (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(4)) |
 433                              (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(5)),
 434                              (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(0)) |
 435                              (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1)) |
 436                              (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(4)) |
 437                              (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(5)));
 438
 439                 /* Set normal pull for all GPIO3D pins */
 440                 rk_clrsetreg(&grf->gpio1_p[2][3],
 441                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) |
 442                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)) |
 443                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(2)) |
 444                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(3)) |
 445                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(4)) |
 446                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
 447                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
 448                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(7)),
 449                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(0)) |
 450                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)) |
 451                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(2)) |
 452                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(3)) |
 453                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(4)) |
 454                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(5)) |
 455                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) |
 456                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7)));
 457
 458                 rk_clrsetreg(&grf->gpio4al_iomux,
 459                              GPIO4A3_MASK << GPIO4A3_SHIFT |
 460                              GPIO4A1_MASK << GPIO4A1_SHIFT |
 461                              GPIO4A0_MASK << GPIO4A0_SHIFT,
 462                              GPIO4A3_MAC_CLK << GPIO4A3_SHIFT |
 463                              GPIO4A1_MAC_TXDV << GPIO4A1_SHIFT |
 464                              GPIO4A0_MAC_MDC << GPIO4A0_SHIFT);
 465
 466                 rk_clrsetreg(&grf->gpio4ah_iomux,
 467                              GPIO4A6_MASK << GPIO4A6_SHIFT |
 468                              GPIO4A5_MASK << GPIO4A5_SHIFT |
 469                              GPIO4A4_MASK << GPIO4A4_SHIFT,
 470                              GPIO4A6_MAC_RXCLK << GPIO4A6_SHIFT |
 471                              GPIO4A5_MAC_MDIO << GPIO4A5_SHIFT |
 472                              GPIO4A4_MAC_TXEN << GPIO4A4_SHIFT);
 473
 474                 /* switch GPIO4A4 to 12ma drive-strength */
 475                 rk_clrsetreg(&grf->gpio1_e[3][0],
 476                              GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(4),
 477                              GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(4));
 478
 479                 /* Set normal pull for all GPIO4A pins */
 480                 rk_clrsetreg(&grf->gpio1_p[3][0],
 481                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) |
 482                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)) |
 483                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(2)) |
 484                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(3)) |
 485                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(4)) |
 486                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
 487                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
 488                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(7)),
 489                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(0)) |
 490                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)) |
 491                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(2)) |
 492                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(3)) |
 493                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(4)) |
 494                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(5)) |
 495                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) |
 496                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7)));
 497
 498                 rk_clrsetreg(&grf->gpio4bl_iomux,
 499                             GPIO4B1_MASK << GPIO4B1_SHIFT,
 500                             GPIO4B1_MAC_TXCLK << GPIO4B1_SHIFT);
 501
 502                 /* switch GPIO4B1 to 12ma drive-strength */
 503                 rk_clrsetreg(&grf->gpio1_e[3][1],
 504                              GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1),
 505                              GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1));
 506
 507                 /* Set pull normal for GPIO4B1 */
 508                 rk_clrsetreg(&grf->gpio1_p[3][1],
 509                              (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)),
 510                              (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)));
 511
 512                 break;
 513         default:
 514                 printf("gmac id = %d iomux error!\n", gmac_id);
 515                 break;
 516         }
 517 }
 518
 519 #ifndef CONFIG_SPL_BUILD
 520 static void pinctrl_rk3288_hdmi_config(struct rk3288_grf *grf, int hdmi_id)
 521 {
 522         switch (hdmi_id) {
 523         case PERIPH_ID_HDMI:
 524                 rk_clrsetreg(&grf->gpio7cl_iomux, GPIO7C3_MASK << GPIO7C3_SHIFT,
 525                              GPIO7C3_EDPHDMII2C_SDA << GPIO7C3_SHIFT);
 526                 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C4_MASK << GPIO7C4_SHIFT,
 527                              GPIO7C4_EDPHDMII2C_SCL << GPIO7C4_SHIFT);
 528                 break;
 529         default:
 530                 debug("hdmi id = %d iomux error!\n", hdmi_id);
 531                 break;
 532         }
 533 }
 534 #endif
 535
 536 static int rk3288_pinctrl_request(struct udevice *dev, int func, int flags)
 537 {
 538         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 539
 540         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 541         switch (func) {
 542         case PERIPH_ID_PWM0:
 543         case PERIPH_ID_PWM1:
 544         case PERIPH_ID_PWM2:
 545         case PERIPH_ID_PWM3:
 546         case PERIPH_ID_PWM4:
 547                 pinctrl_rk3288_pwm_config(priv->grf, func);
 548                 break;
 549         case PERIPH_ID_I2C0:
 550         case PERIPH_ID_I2C1:
 551         case PERIPH_ID_I2C2:
 552         case PERIPH_ID_I2C3:
 553         case PERIPH_ID_I2C4:
 554         case PERIPH_ID_I2C5:
 555                 pinctrl_rk3288_i2c_config(priv->grf, priv->pmu, func);
 556                 break;
 557         case PERIPH_ID_SPI0:
 558         case PERIPH_ID_SPI1:
 559         case PERIPH_ID_SPI2:
 560                 pinctrl_rk3288_spi_config(priv->grf, func, flags);
 561                 break;
 562         case PERIPH_ID_UART0:
 563         case PERIPH_ID_UART1:
 564         case PERIPH_ID_UART2:
 565         case PERIPH_ID_UART3:
 566         case PERIPH_ID_UART4:
 567                 pinctrl_rk3288_uart_config(priv->grf, func);
 568                 break;
 569 #ifndef CONFIG_SPL_BUILD
 570         case PERIPH_ID_LCDC0:
 571         case PERIPH_ID_LCDC1:
 572                 pinctrl_rk3288_lcdc_config(priv->grf, func);
 573                 break;
 574         case PERIPH_ID_HDMI:
 575                 pinctrl_rk3288_hdmi_config(priv->grf, func);
 576                 break;
 577 #endif
 578         case PERIPH_ID_SDMMC0:
 579         case PERIPH_ID_SDMMC1:
 580                 pinctrl_rk3288_sdmmc_config(priv->grf, func);
 581                 break;
 582         case PERIPH_ID_GMAC:
 583                 pinctrl_rk3288_gmac_config(priv->grf, func);
 584                 break;
 585         default:
 586                 return -EINVAL;
 587         }
 588
 589         return 0;
 590 }
 591
 592 static int rk3288_pinctrl_get_periph_id(struct udevice *dev,
 593                                         struct udevice *periph)
 594 {
 595 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 596         u32 cell[3];
 597         int ret;
 598
 599         ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
 600         if (ret < 0)
 601                 return -EINVAL;
 602
 603         switch (cell[1]) {
 604         case 27:
 605                 return PERIPH_ID_GMAC;
 606         case 44:
 607                 return PERIPH_ID_SPI0;
 608         case 45:
 609                 return PERIPH_ID_SPI1;
 610         case 46:
 611                 return PERIPH_ID_SPI2;
 612         case 60:
 613                 return PERIPH_ID_I2C0;
 614         case 62: /* Note strange order */
 615                 return PERIPH_ID_I2C1;
 616         case 61:
 617                 return PERIPH_ID_I2C2;
 618         case 63:
 619                 return PERIPH_ID_I2C3;
 620         case 64:
 621                 return PERIPH_ID_I2C4;
 622         case 65:
 623                 return PERIPH_ID_I2C5;
 624         case 103:
 625                 return PERIPH_ID_HDMI;
 626         }
 627 #endif
 628
 629         return -ENOENT;
 630 }
 631
 632 static int rk3288_pinctrl_set_state_simple(struct udevice *dev,
 633                                            struct udevice *periph)
 634 {
 635         int func;
 636
 637         func = rk3288_pinctrl_get_periph_id(dev, periph);
 638         if (func < 0)
 639                 return func;
 640         return rk3288_pinctrl_request(dev, func, 0);
 641 }
 642
 643 #ifndef CONFIG_SPL_BUILD
 644 int rk3288_pinctrl_get_pin_info(struct rk3288_pinctrl_priv *priv,
 645                                 int banknum, int ind, u32 **addrp, uint *shiftp,
 646                                 uint *maskp)
 647 {
 648         struct rockchip_pin_bank *bank = &rk3288_pin_banks[banknum];
 649         uint muxnum;
 650         u32 *addr;
 651
 652         for (muxnum = 0; muxnum < 4; muxnum++) {
 653                 struct rockchip_iomux *mux = &bank->iomux[muxnum];
 654
 655                 if (ind >= 8) {
 656                         ind -= 8;
 657                         continue;
 658                 }
 659
 660                 if (mux->type & IOMUX_SOURCE_PMU)
 661                         addr = priv->pmu->gpio0_iomux;
 662                 else
 663                         addr = (u32 *)priv->grf - 4;
 664                 addr += mux->offset;
 665                 *shiftp = ind & 7;
 666                 if (mux->type & IOMUX_WIDTH_4BIT) {
 667                         *maskp = 0xf;
 668                         *shiftp *= 4;
 669                         if (*shiftp >= 16) {
 670                                 *shiftp -= 16;
 671                                 addr++;
 672                         }
 673                 } else {
 674                         *maskp = 3;
 675                         *shiftp *= 2;
 676                 }
 677
 678                 debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
 679                       *maskp, *shiftp);
 680                 *addrp = addr;
 681                 return 0;
 682         }
 683
 684         return -EINVAL;
 685 }
 686
 687 static int rk3288_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
 688                                        int index)
 689 {
 690         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 691         uint shift;
 692         uint mask;
 693         u32 *addr;
 694         int ret;
 695
 696         ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
 697                                           &mask);
 698         if (ret)
 699                 return ret;
 700         return (readl(addr) & mask) >> shift;
 701 }
 702
 703 static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
 704                                    int muxval, int flags)
 705 {
 706         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 707         uint shift, ind = index;
 708         uint mask;
 709         uint value;
 710         u32 *addr;
 711         int ret;
 712
 713         debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
 714         ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
 715                                           &mask);
 716         if (ret)
 717                 return ret;
 718
 719         /*
 720          * PMU_GPIO0 registers cannot be selectively written so we cannot use
 721          * rk_clrsetreg() here.  However, the upper 16 bits are reserved and
 722          * are ignored when written, so we can use the same code as for the
 723          * other GPIO banks providing that we preserve the value of the other
 724          * bits.
 725          */
 726         value = readl(addr);
 727         value &= ~(mask << shift);
 728         value |= (mask << (shift + 16)) | (muxval << shift);
 729         writel(value, addr);
 730
 731         /* Handle pullup/pulldown/drive-strength */
 732         if (flags) {
 733                 uint val = 0;
 734
 735                 if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP))
 736                         val = 1;
 737                 else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
 738                         val = 2;
 739                 else if (flags & (1 << PIN_CONFIG_DRIVE_STRENGTH))
 740                         val = 3;
 741
 742                 shift = (index & 7) * 2;
 743                 ind = index >> 3;
 744                 if (banknum == 0)
 745                         addr = &priv->pmu->gpio0pull[ind];
 746                 else if (flags & (1 << PIN_CONFIG_DRIVE_STRENGTH))
 747                         addr = &priv->grf->gpio1_e[banknum - 1][ind];
 748                 else
 749                         addr = &priv->grf->gpio1_p[banknum - 1][ind];
 750                 debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
 751                       shift);
 752
 753                 /* As above, rk_clrsetreg() cannot be used here. */
 754                 value = readl(addr);
 755                 value &= ~(mask << shift);
 756                 value |= (3 << (shift + 16)) | (val << shift);
 757                 writel(value, addr);
 758         }
 759
 760         return 0;
 761 }
 762
 763 static int rk3288_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 764 {
 765         const void *blob = gd->fdt_blob;
 766         int pcfg_node, ret, flags, count, i;
 767         u32 cell[60], *ptr;
 768
 769         debug("%s: %s %s\n", __func__, dev->name, config->name);
 770         ret = fdtdec_get_int_array_count(blob, dev_of_offset(config),
 771                                          "rockchip,pins", cell,
 772                                          ARRAY_SIZE(cell));
 773         if (ret < 0) {
 774                 debug("%s: bad array %d\n", __func__, ret);
 775                 return -EINVAL;
 776         }
 777         count = ret;
 778         for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) {
 779                 pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]);
 780                 if (pcfg_node < 0)
 781                         return -EINVAL;
 782                 flags = pinctrl_decode_pin_config(blob, pcfg_node);
 783                 if (flags < 0)
 784                         return flags;
 785
 786                 if (fdtdec_get_int(blob, pcfg_node, "drive-strength", 0) == 12)
 787                         flags |= 1 << PIN_CONFIG_DRIVE_STRENGTH;
 788
 789                 ret = rk3288_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
 790                                               flags);
 791                 if (ret)
 792                         return ret;
 793         }
 794
 795         return 0;
 796 }
 797 #endif
 798
 799 static struct pinctrl_ops rk3288_pinctrl_ops = {
 800 #ifndef CONFIG_SPL_BUILD
 801         .set_state      = rk3288_pinctrl_set_state,
 802         .get_gpio_mux   = rk3288_pinctrl_get_gpio_mux,
 803 #endif
 804         .set_state_simple       = rk3288_pinctrl_set_state_simple,
 805         .request        = rk3288_pinctrl_request,
 806         .get_periph_id  = rk3288_pinctrl_get_periph_id,
 807 };
 808
 809 #ifndef CONFIG_SPL_BUILD
 810 static int rk3288_pinctrl_parse_tables(struct rk3288_pinctrl_priv *priv,
 811                                        struct rockchip_pin_bank *banks,
 812                                        int count)
 813 {
 814         struct rockchip_pin_bank *bank;
 815         uint reg, muxnum, banknum;
 816
 817         reg = 0;
 818         for (banknum = 0; banknum < count; banknum++) {
 819                 bank = &banks[banknum];
 820                 bank->reg = reg;
 821                 debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4);
 822                 for (muxnum = 0; muxnum < 4; muxnum++) {
 823                         struct rockchip_iomux *mux = &bank->iomux[muxnum];
 824
 825                         if (!(mux->type & IOMUX_UNROUTED))
 826                                 mux->offset = reg;
 827                         if (mux->type & IOMUX_WIDTH_4BIT)
 828                                 reg += 2;
 829                         else
 830                                 reg += 1;
 831                 }
 832         }
 833
 834         return 0;
 835 }
 836 #endif
 837
 838 static int rk3288_pinctrl_probe(struct udevice *dev)
 839 {
 840         struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
 841         int ret = 0;
 842
 843         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 844         priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 845         debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
 846 #ifndef CONFIG_SPL_BUILD
 847         ret = rk3288_pinctrl_parse_tables(priv, rk3288_pin_banks,
 848                                           ARRAY_SIZE(rk3288_pin_banks));
 849 #endif
 850
 851         return ret;
 852 }
 853
 854 static const struct udevice_id rk3288_pinctrl_ids[] = {
 855         { .compatible = "rockchip,rk3288-pinctrl" },
 856         { }
 857 };
 858
 859 U_BOOT_DRIVER(pinctrl_rk3288) = {
 860         .name           = "rockchip_rk3288_pinctrl",
 861         .id             = UCLASS_PINCTRL,
 862         .of_match       = rk3288_pinctrl_ids,
 863         .priv_auto_alloc_size = sizeof(struct rk3288_pinctrl_priv),
 864         .ops            = &rk3288_pinctrl_ops,
 865 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 866         .bind           = dm_scan_fdt_dev,
 867 #endif
 868         .probe          = rk3288_pinctrl_probe,
 869 };