git.sur5r.net Git - u-boot/blob - drivers/pinctrl/rockchip/pinctrl_rk3328.c

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <syscon.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/arch/grf_rk3328.h>
  14 #include <asm/arch/periph.h>
  15 #include <asm/io.h>
  16 #include <dm/pinctrl.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 enum {
  21         /* GPIO0A_IOMUX */
  22         GPIO0A5_SEL_SHIFT       = 10,
  23         GPIO0A5_SEL_MASK        = 3 << GPIO0A5_SEL_SHIFT,
  24         GPIO0A5_I2C3_SCL        = 2,
  25
  26         GPIO0A6_SEL_SHIFT       = 12,
  27         GPIO0A6_SEL_MASK        = 3 << GPIO0A6_SEL_SHIFT,
  28         GPIO0A6_I2C3_SDA        = 2,
  29
  30         GPIO0A7_SEL_SHIFT       = 14,
  31         GPIO0A7_SEL_MASK        = 3 << GPIO0A7_SEL_SHIFT,
  32         GPIO0A7_EMMC_DATA0      = 2,
  33
  34         GPIO0D6_SEL_SHIFT       = 12,
  35         GPIO0D6_SEL_MASK        = 3 << GPIO0D6_SEL_SHIFT,
  36         GPIO0D6_GPIO            = 0,
  37         GPIO0D6_SDMMC0_PWRENM1  = 3,
  38
  39         /* GPIO1A_IOMUX */
  40         GPIO1A0_SEL_SHIFT       = 0,
  41         GPIO1A0_SEL_MASK        = 0x3fff << GPIO1A0_SEL_SHIFT,
  42         GPIO1A0_CARD_DATA_CLK_CMD_DETN  = 0x1555,
  43
  44         /* GPIO2A_IOMUX */
  45         GPIO2A0_SEL_SHIFT       = 0,
  46         GPIO2A0_SEL_MASK        = 3 << GPIO2A0_SEL_SHIFT,
  47         GPIO2A0_UART2_TX_M1     = 1,
  48
  49         GPIO2A1_SEL_SHIFT       = 2,
  50         GPIO2A1_SEL_MASK        = 3 << GPIO2A1_SEL_SHIFT,
  51         GPIO2A1_UART2_RX_M1     = 1,
  52
  53         GPIO2A2_SEL_SHIFT       = 4,
  54         GPIO2A2_SEL_MASK        = 3 << GPIO2A2_SEL_SHIFT,
  55         GPIO2A2_PWM_IR          = 1,
  56
  57         GPIO2A4_SEL_SHIFT       = 8,
  58         GPIO2A4_SEL_MASK        = 3 << GPIO2A4_SEL_SHIFT,
  59         GPIO2A4_PWM_0           = 1,
  60         GPIO2A4_I2C1_SDA,
  61
  62         GPIO2A5_SEL_SHIFT       = 10,
  63         GPIO2A5_SEL_MASK        = 3 << GPIO2A5_SEL_SHIFT,
  64         GPIO2A5_PWM_1           = 1,
  65         GPIO2A5_I2C1_SCL,
  66
  67         GPIO2A6_SEL_SHIFT       = 12,
  68         GPIO2A6_SEL_MASK        = 3 << GPIO2A6_SEL_SHIFT,
  69         GPIO2A6_PWM_2           = 1,
  70
  71         GPIO2A7_SEL_SHIFT       = 14,
  72         GPIO2A7_SEL_MASK        = 3 << GPIO2A7_SEL_SHIFT,
  73         GPIO2A7_GPIO            = 0,
  74         GPIO2A7_SDMMC0_PWRENM0,
  75
  76         /* GPIO2BL_IOMUX */
  77         GPIO2BL0_SEL_SHIFT      = 0,
  78         GPIO2BL0_SEL_MASK       = 0x3f << GPIO2BL0_SEL_SHIFT,
  79         GPIO2BL0_SPI_CLK_TX_RX_M0       = 0x15,
  80
  81         GPIO2BL3_SEL_SHIFT      = 6,
  82         GPIO2BL3_SEL_MASK       = 3 << GPIO2BL3_SEL_SHIFT,
  83         GPIO2BL3_SPI_CSN0_M0    = 1,
  84
  85         GPIO2BL4_SEL_SHIFT      = 8,
  86         GPIO2BL4_SEL_MASK       = 3 << GPIO2BL4_SEL_SHIFT,
  87         GPIO2BL4_SPI_CSN1_M0    = 1,
  88
  89         GPIO2BL5_SEL_SHIFT      = 10,
  90         GPIO2BL5_SEL_MASK       = 3 << GPIO2BL5_SEL_SHIFT,
  91         GPIO2BL5_I2C2_SDA       = 1,
  92
  93         GPIO2BL6_SEL_SHIFT      = 12,
  94         GPIO2BL6_SEL_MASK       = 3 << GPIO2BL6_SEL_SHIFT,
  95         GPIO2BL6_I2C2_SCL       = 1,
  96
  97         /* GPIO2D_IOMUX */
  98         GPIO2D0_SEL_SHIFT       = 0,
  99         GPIO2D0_SEL_MASK        = 3 << GPIO2D0_SEL_SHIFT,
 100         GPIO2D0_I2C0_SCL        = 1,
 101
 102         GPIO2D1_SEL_SHIFT       = 2,
 103         GPIO2D1_SEL_MASK        = 3 << GPIO2D1_SEL_SHIFT,
 104         GPIO2D1_I2C0_SDA        = 1,
 105
 106         GPIO2D4_SEL_SHIFT       = 8,
 107         GPIO2D4_SEL_MASK        = 0xff << GPIO2D4_SEL_SHIFT,
 108         GPIO2D4_EMMC_DATA1234   = 0xaa,
 109
 110         /* GPIO3C_IOMUX */
 111         GPIO3C0_SEL_SHIFT       = 0,
 112         GPIO3C0_SEL_MASK        = 0x3fff << GPIO3C0_SEL_SHIFT,
 113         GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD   = 0x2aaa,
 114
 115         /* COM_IOMUX */
 116         IOMUX_SEL_UART2_SHIFT   = 0,
 117         IOMUX_SEL_UART2_MASK    = 3 << IOMUX_SEL_UART2_SHIFT,
 118         IOMUX_SEL_UART2_M0      = 0,
 119         IOMUX_SEL_UART2_M1,
 120
 121         IOMUX_SEL_SPI_SHIFT     = 4,
 122         IOMUX_SEL_SPI_MASK      = 3 << IOMUX_SEL_SPI_SHIFT,
 123         IOMUX_SEL_SPI_M0        = 0,
 124         IOMUX_SEL_SPI_M1,
 125         IOMUX_SEL_SPI_M2,
 126
 127         IOMUX_SEL_SDMMC_SHIFT   = 7,
 128         IOMUX_SEL_SDMMC_MASK    = 1 << IOMUX_SEL_SDMMC_SHIFT,
 129         IOMUX_SEL_SDMMC_M0      = 0,
 130         IOMUX_SEL_SDMMC_M1,
 131 };
 132
 133 struct rk3328_pinctrl_priv {
 134         struct rk3328_grf_regs *grf;
 135 };
 136
 137 static void pinctrl_rk3328_pwm_config(struct rk3328_grf_regs *grf, int pwm_id)
 138 {
 139         switch (pwm_id) {
 140         case PERIPH_ID_PWM0:
 141                 rk_clrsetreg(&grf->gpio2a_iomux,
 142                              GPIO2A4_SEL_MASK,
 143                              GPIO2A4_PWM_0 << GPIO2A4_SEL_SHIFT);
 144                 break;
 145         case PERIPH_ID_PWM1:
 146                 rk_clrsetreg(&grf->gpio2a_iomux,
 147                              GPIO2A5_SEL_MASK,
 148                              GPIO2A5_PWM_1 << GPIO2A5_SEL_SHIFT);
 149                 break;
 150         case PERIPH_ID_PWM2:
 151                 rk_clrsetreg(&grf->gpio2a_iomux,
 152                              GPIO2A6_SEL_MASK,
 153                              GPIO2A6_PWM_2 << GPIO2A6_SEL_SHIFT);
 154                 break;
 155         case PERIPH_ID_PWM3:
 156                 rk_clrsetreg(&grf->gpio2a_iomux,
 157                              GPIO2A2_SEL_MASK,
 158                              GPIO2A2_PWM_IR << GPIO2A2_SEL_SHIFT);
 159                 break;
 160         default:
 161                 debug("pwm id = %d iomux error!\n", pwm_id);
 162                 break;
 163         }
 164 }
 165
 166 static void pinctrl_rk3328_i2c_config(struct rk3328_grf_regs *grf, int i2c_id)
 167 {
 168         switch (i2c_id) {
 169         case PERIPH_ID_I2C0:
 170                 rk_clrsetreg(&grf->gpio2d_iomux,
 171                              GPIO2D0_SEL_MASK | GPIO2D1_SEL_MASK,
 172                              GPIO2D0_I2C0_SCL << GPIO2D0_SEL_SHIFT |
 173                              GPIO2D1_I2C0_SDA << GPIO2D1_SEL_SHIFT);
 174                 break;
 175         case PERIPH_ID_I2C1:
 176                 rk_clrsetreg(&grf->gpio2a_iomux,
 177                              GPIO2A4_SEL_MASK | GPIO2A5_SEL_MASK,
 178                              GPIO2A5_I2C1_SCL << GPIO2A5_SEL_SHIFT |
 179                              GPIO2A4_I2C1_SDA << GPIO2A4_SEL_SHIFT);
 180                 break;
 181         case PERIPH_ID_I2C2:
 182                 rk_clrsetreg(&grf->gpio2bl_iomux,
 183                              GPIO2BL5_SEL_MASK | GPIO2BL6_SEL_MASK,
 184                              GPIO2BL6_I2C2_SCL << GPIO2BL6_SEL_SHIFT |
 185                              GPIO2BL5_I2C2_SDA << GPIO2BL5_SEL_SHIFT);
 186                 break;
 187         case PERIPH_ID_I2C3:
 188                 rk_clrsetreg(&grf->gpio0a_iomux,
 189                              GPIO0A5_SEL_MASK | GPIO0A6_SEL_MASK,
 190                              GPIO0A5_I2C3_SCL << GPIO0A5_SEL_SHIFT |
 191                              GPIO0A6_I2C3_SDA << GPIO0A6_SEL_SHIFT);
 192                 break;
 193         default:
 194                 debug("i2c id = %d iomux error!\n", i2c_id);
 195                 break;
 196         }
 197 }
 198
 199 static void pinctrl_rk3328_lcdc_config(struct rk3328_grf_regs *grf, int lcd_id)
 200 {
 201         switch (lcd_id) {
 202         case PERIPH_ID_LCDC0:
 203                 break;
 204         default:
 205                 debug("lcdc id = %d iomux error!\n", lcd_id);
 206                 break;
 207         }
 208 }
 209
 210 static int pinctrl_rk3328_spi_config(struct rk3328_grf_regs *grf,
 211                                      enum periph_id spi_id, int cs)
 212 {
 213         u32 com_iomux = readl(&grf->com_iomux);
 214
 215         if ((com_iomux & IOMUX_SEL_SPI_MASK) !=
 216                 IOMUX_SEL_SPI_M0 << IOMUX_SEL_SPI_SHIFT) {
 217                 debug("driver do not support iomux other than m0\n");
 218                 goto err;
 219         }
 220
 221         switch (spi_id) {
 222         case PERIPH_ID_SPI0:
 223                 switch (cs) {
 224                 case 0:
 225                         rk_clrsetreg(&grf->gpio2bl_iomux,
 226                                      GPIO2BL3_SEL_MASK,
 227                                      GPIO2BL3_SPI_CSN0_M0
 228                                      << GPIO2BL3_SEL_SHIFT);
 229                         break;
 230                 case 1:
 231                         rk_clrsetreg(&grf->gpio2bl_iomux,
 232                                      GPIO2BL4_SEL_MASK,
 233                                      GPIO2BL4_SPI_CSN1_M0
 234                                      << GPIO2BL4_SEL_SHIFT);
 235                         break;
 236                 default:
 237                         goto err;
 238                 }
 239                 rk_clrsetreg(&grf->gpio2bl_iomux,
 240                              GPIO2BL0_SEL_MASK,
 241                              GPIO2BL0_SPI_CLK_TX_RX_M0 << GPIO2BL0_SEL_SHIFT);
 242                 break;
 243         default:
 244                 goto err;
 245         }
 246
 247         return 0;
 248 err:
 249         debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
 250         return -ENOENT;
 251 }
 252
 253 static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id)
 254 {
 255         u32 com_iomux = readl(&grf->com_iomux);
 256
 257         switch (uart_id) {
 258         case PERIPH_ID_UART2:
 259                 break;
 260                 if (com_iomux & IOMUX_SEL_UART2_MASK)
 261                         rk_clrsetreg(&grf->gpio2a_iomux,
 262                                      GPIO2A0_SEL_MASK | GPIO2A1_SEL_MASK,
 263                                      GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT |
 264                                      GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
 265
 266                 break;
 267         case PERIPH_ID_UART0:
 268         case PERIPH_ID_UART1:
 269         case PERIPH_ID_UART3:
 270         case PERIPH_ID_UART4:
 271         default:
 272                 debug("uart id = %d iomux error!\n", uart_id);
 273                 break;
 274         }
 275 }
 276
 277 static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf,
 278                                         int mmc_id)
 279 {
 280         u32 com_iomux = readl(&grf->com_iomux);
 281
 282         switch (mmc_id) {
 283         case PERIPH_ID_EMMC:
 284                 rk_clrsetreg(&grf->gpio0a_iomux,
 285                              GPIO0A7_SEL_MASK,
 286                              GPIO0A7_EMMC_DATA0 << GPIO0A7_SEL_SHIFT);
 287                 rk_clrsetreg(&grf->gpio2d_iomux,
 288                              GPIO2D4_SEL_MASK,
 289                              GPIO2D4_EMMC_DATA1234 << GPIO2D4_SEL_SHIFT);
 290                 rk_clrsetreg(&grf->gpio3c_iomux,
 291                              GPIO3C0_SEL_MASK,
 292                              GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD
 293                              << GPIO3C0_SEL_SHIFT);
 294                 break;
 295         case PERIPH_ID_SDCARD:
 296                 /* SDMMC_PWREN use GPIO and init as regulator-fiexed  */
 297                 if (com_iomux & IOMUX_SEL_SDMMC_MASK)
 298                         rk_clrsetreg(&grf->gpio0d_iomux,
 299                                      GPIO0D6_SEL_MASK,
 300                                      GPIO0D6_GPIO << GPIO0D6_SEL_SHIFT);
 301                 else
 302                         rk_clrsetreg(&grf->gpio2a_iomux,
 303                                      GPIO2A7_SEL_MASK,
 304                                      GPIO2A7_GPIO << GPIO2A7_SEL_SHIFT);
 305                 rk_clrsetreg(&grf->gpio1a_iomux,
 306                              GPIO1A0_SEL_MASK,
 307                              GPIO1A0_CARD_DATA_CLK_CMD_DETN
 308                              << GPIO1A0_SEL_SHIFT);
 309                 break;
 310         default:
 311                 debug("mmc id = %d iomux error!\n", mmc_id);
 312                 break;
 313         }
 314 }
 315
 316 static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags)
 317 {
 318         struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
 319
 320         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 321         switch (func) {
 322         case PERIPH_ID_PWM0:
 323         case PERIPH_ID_PWM1:
 324         case PERIPH_ID_PWM2:
 325         case PERIPH_ID_PWM3:
 326                 pinctrl_rk3328_pwm_config(priv->grf, func);
 327                 break;
 328         case PERIPH_ID_I2C0:
 329         case PERIPH_ID_I2C1:
 330         case PERIPH_ID_I2C2:
 331         case PERIPH_ID_I2C3:
 332                 pinctrl_rk3328_i2c_config(priv->grf, func);
 333                 break;
 334         case PERIPH_ID_SPI0:
 335                 pinctrl_rk3328_spi_config(priv->grf, func, flags);
 336                 break;
 337         case PERIPH_ID_UART0:
 338         case PERIPH_ID_UART1:
 339         case PERIPH_ID_UART2:
 340         case PERIPH_ID_UART3:
 341         case PERIPH_ID_UART4:
 342                 pinctrl_rk3328_uart_config(priv->grf, func);
 343                 break;
 344         case PERIPH_ID_LCDC0:
 345         case PERIPH_ID_LCDC1:
 346                 pinctrl_rk3328_lcdc_config(priv->grf, func);
 347                 break;
 348         case PERIPH_ID_SDMMC0:
 349         case PERIPH_ID_SDMMC1:
 350                 pinctrl_rk3328_sdmmc_config(priv->grf, func);
 351                 break;
 352         default:
 353                 return -EINVAL;
 354         }
 355
 356         return 0;
 357 }
 358
 359 static int rk3328_pinctrl_get_periph_id(struct udevice *dev,
 360                                         struct udevice *periph)
 361 {
 362         u32 cell[3];
 363         int ret;
 364
 365         ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
 366         if (ret < 0)
 367                 return -EINVAL;
 368
 369         switch (cell[1]) {
 370         case 49:
 371                 return PERIPH_ID_SPI0;
 372         case 50:
 373                 return PERIPH_ID_PWM0;
 374         case 36:
 375                 return PERIPH_ID_I2C0;
 376         case 37: /* Note strange order */
 377                 return PERIPH_ID_I2C1;
 378         case 38:
 379                 return PERIPH_ID_I2C2;
 380         case 39:
 381                 return PERIPH_ID_I2C3;
 382         case 12:
 383                 return PERIPH_ID_SDCARD;
 384         case 14:
 385                 return PERIPH_ID_EMMC;
 386         }
 387
 388         return -ENOENT;
 389 }
 390
 391 static int rk3328_pinctrl_set_state_simple(struct udevice *dev,
 392                                            struct udevice *periph)
 393 {
 394         int func;
 395
 396         func = rk3328_pinctrl_get_periph_id(dev, periph);
 397         if (func < 0)
 398                 return func;
 399
 400         return rk3328_pinctrl_request(dev, func, 0);
 401 }
 402
 403 static struct pinctrl_ops rk3328_pinctrl_ops = {
 404         .set_state_simple       = rk3328_pinctrl_set_state_simple,
 405         .request        = rk3328_pinctrl_request,
 406         .get_periph_id  = rk3328_pinctrl_get_periph_id,
 407 };
 408
 409 static int rk3328_pinctrl_probe(struct udevice *dev)
 410 {
 411         struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
 412         int ret = 0;
 413
 414         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 415         debug("%s: grf=%p\n", __func__, priv->grf);
 416
 417         return ret;
 418 }
 419
 420 static const struct udevice_id rk3328_pinctrl_ids[] = {
 421         { .compatible = "rockchip,rk3328-pinctrl" },
 422         { }
 423 };
 424
 425 U_BOOT_DRIVER(pinctrl_rk3328) = {
 426         .name           = "rockchip_rk3328_pinctrl",
 427         .id             = UCLASS_PINCTRL,
 428         .of_match       = rk3328_pinctrl_ids,
 429         .priv_auto_alloc_size = sizeof(struct rk3328_pinctrl_priv),
 430         .ops            = &rk3328_pinctrl_ops,
 431         .bind           = dm_scan_fdt_dev,
 432         .probe          = rk3328_pinctrl_probe,
 433 };