git.sur5r.net Git - u-boot/blob - drivers/pinctrl/rockchip/pinctrl_rk3328.c

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <syscon.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/hardware.h>
  13 #include <asm/arch/grf_rk3328.h>
  14 #include <asm/arch/periph.h>
  15 #include <asm/io.h>
  16 #include <dm/pinctrl.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 struct rk3328_pinctrl_priv {
  21         struct rk3328_grf_regs *grf;
  22 };
  23
  24 static void pinctrl_rk3328_pwm_config(struct rk3328_grf_regs *grf, int pwm_id)
  25 {
  26         switch (pwm_id) {
  27         case PERIPH_ID_PWM0:
  28                 rk_clrsetreg(&grf->gpio2a_iomux,
  29                              GPIO2A4_SEL_MASK,
  30                              GPIO2A4_PWM_0 << GPIO2A4_SEL_SHIFT);
  31                 break;
  32         case PERIPH_ID_PWM1:
  33                 rk_clrsetreg(&grf->gpio2a_iomux,
  34                              GPIO2A5_SEL_MASK,
  35                              GPIO2A5_PWM_1 << GPIO2A5_SEL_SHIFT);
  36                 break;
  37         case PERIPH_ID_PWM2:
  38                 rk_clrsetreg(&grf->gpio2a_iomux,
  39                              GPIO2A6_SEL_MASK,
  40                              GPIO2A6_PWM_2 << GPIO2A6_SEL_SHIFT);
  41                 break;
  42         case PERIPH_ID_PWM3:
  43                 rk_clrsetreg(&grf->gpio2a_iomux,
  44                              GPIO2A2_SEL_MASK,
  45                              GPIO2A2_PWM_IR << GPIO2A2_SEL_SHIFT);
  46                 break;
  47         default:
  48                 debug("pwm id = %d iomux error!\n", pwm_id);
  49                 break;
  50         }
  51 }
  52
  53 static void pinctrl_rk3328_i2c_config(struct rk3328_grf_regs *grf, int i2c_id)
  54 {
  55         switch (i2c_id) {
  56         case PERIPH_ID_I2C0:
  57                 rk_clrsetreg(&grf->gpio2d_iomux,
  58                              GPIO2D0_SEL_MASK | GPIO2D1_SEL_MASK,
  59                              GPIO2D0_I2C0_SCL << GPIO2D0_SEL_SHIFT |
  60                              GPIO2D1_I2C0_SDA << GPIO2D1_SEL_SHIFT);
  61                 break;
  62         case PERIPH_ID_I2C1:
  63                 rk_clrsetreg(&grf->gpio2a_iomux,
  64                              GPIO2A4_SEL_MASK | GPIO2A5_SEL_MASK,
  65                              GPIO2A5_I2C1_SCL << GPIO2A5_SEL_SHIFT |
  66                              GPIO2A4_I2C1_SDA << GPIO2A4_SEL_SHIFT);
  67                 break;
  68         case PERIPH_ID_I2C2:
  69                 rk_clrsetreg(&grf->gpio2bl_iomux,
  70                              GPIO2BL5_SEL_MASK | GPIO2BL6_SEL_MASK,
  71                              GPIO2BL6_I2C2_SCL << GPIO2BL6_SEL_SHIFT |
  72                              GPIO2BL5_I2C2_SDA << GPIO2BL5_SEL_SHIFT);
  73                 break;
  74         case PERIPH_ID_I2C3:
  75                 rk_clrsetreg(&grf->gpio0a_iomux,
  76                              GPIO0A5_SEL_MASK | GPIO0A6_SEL_MASK,
  77                              GPIO0A5_I2C3_SCL << GPIO0A5_SEL_SHIFT |
  78                              GPIO0A6_I2C3_SDA << GPIO0A6_SEL_SHIFT);
  79                 break;
  80         default:
  81                 debug("i2c id = %d iomux error!\n", i2c_id);
  82                 break;
  83         }
  84 }
  85
  86 static void pinctrl_rk3328_lcdc_config(struct rk3328_grf_regs *grf, int lcd_id)
  87 {
  88         switch (lcd_id) {
  89         case PERIPH_ID_LCDC0:
  90                 break;
  91         default:
  92                 debug("lcdc id = %d iomux error!\n", lcd_id);
  93                 break;
  94         }
  95 }
  96
  97 static int pinctrl_rk3328_spi_config(struct rk3328_grf_regs *grf,
  98                                      enum periph_id spi_id, int cs)
  99 {
 100         rk_clrsetreg(&grf->com_iomux,
 101                      SPI_IOMUX_SEL_MASK,
 102                      SPI_IOMUX_SEL_M0 << SPI_IOMUX_SEL_SHIFT);
 103
 104         switch (spi_id) {
 105         case PERIPH_ID_SPI0:
 106                 switch (cs) {
 107                 case 0:
 108                         rk_clrsetreg(&grf->gpio2bl_iomux,
 109                                      GPIO2BL3_SEL_MASK,
 110                                      GPIO2BL3_SPI_CSN0_M0
 111                                      << GPIO2BL3_SEL_SHIFT);
 112                         break;
 113                 case 1:
 114                         rk_clrsetreg(&grf->gpio2bl_iomux,
 115                                      GPIO2BL4_SEL_MASK,
 116                                      GPIO2BL4_SPI_CSN1_M0
 117                                      << GPIO2BL4_SEL_SHIFT);
 118                         break;
 119                 default:
 120                         goto err;
 121                 }
 122                 rk_clrsetreg(&grf->gpio2bl_iomux,
 123                              GPIO2BL0_SEL_MASK,
 124                              GPIO2BL0_SPI_CLK_TX_RX_M0 << GPIO2BL0_SEL_SHIFT);
 125                 break;
 126         default:
 127                 goto err;
 128         }
 129
 130         return 0;
 131 err:
 132         debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
 133         return -ENOENT;
 134 }
 135
 136 static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id)
 137 {
 138         switch (uart_id) {
 139         case PERIPH_ID_UART2:
 140                 break;
 141                 /* uart2 iomux select m1 */
 142                 rk_clrsetreg(&grf->com_iomux,
 143                              UART2_IOMUX_SEL_MASK,
 144                              UART2_IOMUX_SEL_M1
 145                              << UART2_IOMUX_SEL_SHIFT);
 146                 rk_clrsetreg(&grf->gpio2a_iomux,
 147                              GPIO2A0_SEL_MASK | GPIO2A1_SEL_MASK,
 148                              GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT |
 149                              GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
 150                 break;
 151         case PERIPH_ID_UART0:
 152         case PERIPH_ID_UART1:
 153         case PERIPH_ID_UART3:
 154         case PERIPH_ID_UART4:
 155         default:
 156                 debug("uart id = %d iomux error!\n", uart_id);
 157                 break;
 158         }
 159 }
 160
 161 static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf,
 162                                         int mmc_id)
 163 {
 164         switch (mmc_id) {
 165         case PERIPH_ID_EMMC:
 166                 rk_clrsetreg(&grf->gpio0a_iomux,
 167                              GPIO0A7_SEL_MASK,
 168                              GPIO0A7_EMMC_DATA0 << GPIO0A7_SEL_SHIFT);
 169                 rk_clrsetreg(&grf->gpio2d_iomux,
 170                              GPIO2D4_SEL_MASK,
 171                              GPIO2D4_EMMC_DATA1234 << GPIO2D4_SEL_SHIFT);
 172                 rk_clrsetreg(&grf->gpio3c_iomux,
 173                              GPIO3C0_SEL_MASK,
 174                              GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD
 175                              << GPIO3C0_SEL_SHIFT);
 176                 break;
 177         case PERIPH_ID_SDCARD:
 178                 /* sdcard iomux select m0 */
 179                 rk_clrsetreg(&grf->com_iomux,
 180                              CARD_IOMUX_SEL_MASK,
 181                              CARD_IOMUX_SEL_M0 << CARD_IOMUX_SEL_SHIFT);
 182                 rk_clrsetreg(&grf->gpio2a_iomux,
 183                              GPIO2A7_SEL_MASK,
 184                              GPIO2A7_SDMMC0_PWRENM0 << GPIO2A7_SEL_SHIFT);
 185                 rk_clrsetreg(&grf->gpio1a_iomux,
 186                              GPIO1A0_SEL_MASK,
 187                              GPIO1A0_CARD_DATA_CLK_CMD_DETN
 188                              << GPIO1A0_SEL_SHIFT);
 189                 break;
 190         default:
 191                 debug("mmc id = %d iomux error!\n", mmc_id);
 192                 break;
 193         }
 194 }
 195
 196 static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags)
 197 {
 198         struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
 199
 200         debug("%s: func=%x, flags=%x\n", __func__, func, flags);
 201         switch (func) {
 202         case PERIPH_ID_PWM0:
 203         case PERIPH_ID_PWM1:
 204         case PERIPH_ID_PWM2:
 205         case PERIPH_ID_PWM3:
 206                 pinctrl_rk3328_pwm_config(priv->grf, func);
 207                 break;
 208         case PERIPH_ID_I2C0:
 209         case PERIPH_ID_I2C1:
 210         case PERIPH_ID_I2C2:
 211         case PERIPH_ID_I2C3:
 212                 pinctrl_rk3328_i2c_config(priv->grf, func);
 213                 break;
 214         case PERIPH_ID_SPI0:
 215                 pinctrl_rk3328_spi_config(priv->grf, func, flags);
 216                 break;
 217         case PERIPH_ID_UART0:
 218         case PERIPH_ID_UART1:
 219         case PERIPH_ID_UART2:
 220         case PERIPH_ID_UART3:
 221         case PERIPH_ID_UART4:
 222                 pinctrl_rk3328_uart_config(priv->grf, func);
 223                 break;
 224         case PERIPH_ID_LCDC0:
 225         case PERIPH_ID_LCDC1:
 226                 pinctrl_rk3328_lcdc_config(priv->grf, func);
 227                 break;
 228         case PERIPH_ID_SDMMC0:
 229         case PERIPH_ID_SDMMC1:
 230                 pinctrl_rk3328_sdmmc_config(priv->grf, func);
 231                 break;
 232         default:
 233                 return -EINVAL;
 234         }
 235
 236         return 0;
 237 }
 238
 239 static int rk3328_pinctrl_get_periph_id(struct udevice *dev,
 240                                         struct udevice *periph)
 241 {
 242         u32 cell[3];
 243         int ret;
 244
 245         ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
 246                                    "interrupts", cell, ARRAY_SIZE(cell));
 247         if (ret < 0)
 248                 return -EINVAL;
 249
 250         switch (cell[1]) {
 251         case 49:
 252                 return PERIPH_ID_SPI0;
 253         case 50:
 254                 return PERIPH_ID_PWM0;
 255         case 36:
 256                 return PERIPH_ID_I2C0;
 257         case 37: /* Note strange order */
 258                 return PERIPH_ID_I2C1;
 259         case 38:
 260                 return PERIPH_ID_I2C2;
 261         case 39:
 262                 return PERIPH_ID_I2C3;
 263         case 12:
 264                 return PERIPH_ID_SDCARD;
 265         case 14:
 266                 return PERIPH_ID_EMMC;
 267         }
 268
 269         return -ENOENT;
 270 }
 271
 272 static int rk3328_pinctrl_set_state_simple(struct udevice *dev,
 273                                            struct udevice *periph)
 274 {
 275         int func;
 276
 277         func = rk3328_pinctrl_get_periph_id(dev, periph);
 278         if (func < 0)
 279                 return func;
 280
 281         return rk3328_pinctrl_request(dev, func, 0);
 282 }
 283
 284 static struct pinctrl_ops rk3328_pinctrl_ops = {
 285         .set_state_simple       = rk3328_pinctrl_set_state_simple,
 286         .request        = rk3328_pinctrl_request,
 287         .get_periph_id  = rk3328_pinctrl_get_periph_id,
 288 };
 289
 290 static int rk3328_pinctrl_probe(struct udevice *dev)
 291 {
 292         struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
 293         int ret = 0;
 294
 295         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 296         debug("%s: grf=%p\n", __func__, priv->grf);
 297
 298         return ret;
 299 }
 300
 301 static const struct udevice_id rk3328_pinctrl_ids[] = {
 302         { .compatible = "rockchip,rk3328-pinctrl" },
 303         { }
 304 };
 305
 306 U_BOOT_DRIVER(pinctrl_rk3328) = {
 307         .name           = "rockchip_rk3328_pinctrl",
 308         .id             = UCLASS_PINCTRL,
 309         .of_match       = rk3328_pinctrl_ids,
 310         .priv_auto_alloc_size = sizeof(struct rk3328_pinctrl_priv),
 311         .ops            = &rk3328_pinctrl_ops,
 312         .bind           = dm_scan_fdt_dev,
 313         .probe          = rk3328_pinctrl_probe,
 314 };